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[88.29.179.57]) by smtp.gmail.com with ESMTPSA id e17-20020a5d4e91000000b002c559626a50sm13820228wru.13.2023.03.07.15.33.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Mar 2023 15:33:40 -0800 (PST) Message-ID: Date: Wed, 8 Mar 2023 00:33:38 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH] hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR Content-Language: en-US To: Jiaxun Yang , qemu-devel@nongnu.org Cc: balaton@eik.bme.hu, nathan@kernel.org, Rob Landley , Bernhard Beschow References: <20230223161958.48696-1-jiaxun.yang@flygoat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230223161958.48696-1-jiaxun.yang@flygoat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 23/2/23 17:19, Jiaxun Yang wrote: > 145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE > MemoryRegionOps") converted CFGADDR/CFGDATA registers to use PCI_HOST_BRIDGE's > accessor facility and enabled byte swap for both CFGADDR/CFGDATA register. > > However CFGADDR as a ISD internal register is not controled by MByteSwap > bit, it follows endian of all other ISD register, which means it ties to > little endian. > > Move mapping of CFGADDR out of gt64120_update_pci_cfgdata_mapping to disable > endian-swapping. > > This should fix some recent reports about poweroff hang. > > Fixes: 145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE MemoryRegionOps") > Signed-off-by: Jiaxun Yang > --- > hw/pci-host/gt64120.c | 18 ++++++------------ > 1 file changed, 6 insertions(+), 12 deletions(-) So this works on little-endian hosts, but fails on big-endian ones :( I.e. on Linux we have early_console_write() -> prom_putchar() looping: IN: prom_putchar 0x8010fab8: lbu v0,0(v1) 0x8010fabc: andi v0,v0,0x20 0x8010fac0: beqz v0,0x8010fab8 0x8010fac4: andi v0,a0,0xff gt64120: Illegal register read reg:0x3fc size:4 value:0x00000000 gt64120: Illegal register read reg:0x3fc size:4 value:0x00000000 gt64120: Illegal register read reg:0x3fc size:4 value:0x00000000 gt64120: Illegal register read reg:0x3fc size:4 value:0x00000000 gt64120: Illegal register read reg:0x3fc size:4 value:0x00000000 ...