From: Richard Henderson <richard.henderson@linaro.org>
To: "Christoph Müllner" <christoph.muellner@vrull.eu>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
"Alistair Francis" <alistair.francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Heiko Stübner" <heiko.stuebner@vrull.eu>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Nelson Chu" <nelson@rivosinc.com>,
"Kito Cheng" <kito.cheng@sifive.com>,
"Cooper Qu" <cooper.qu@linux.alibaba.com>,
"Lifang Xia" <lifang_xia@linux.alibaba.com>,
"Yunhai Shang" <yunhai@linux.alibaba.com>,
"Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs
Date: Thu, 8 Sep 2022 09:56:24 +0100 [thread overview]
Message-ID: <aa79c76c-fc8c-ca76-6224-ba5d85f3d966@linaro.org> (raw)
In-Reply-To: <CAEg0e7jEh+ix32xGs+BdpCZOCT9YAFC_Lb5Ti-FQcFJiDtHmnQ@mail.gmail.com>
On 9/8/22 09:23, Christoph Müllner wrote:
>
>
> On Thu, Sep 8, 2022 at 9:46 AM Richard Henderson <richard.henderson@linaro.org
> <mailto:richard.henderson@linaro.org>> wrote:
>
> On 9/6/22 13:22, Christoph Muellner wrote:
> > + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
> > + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C910, rv64_thead_c906_cpu_init),
>
> Why model both if they're identical?
>
>
> I figured that users might expect that (existence of "thead-c906" and "thead-c910").
> And using "thead-c9xx" feels like it would be regretted in the future.
>
> Should I drop "thead-c910"?
Quite possibly. For Arm, we don't try to supply every cpu model, only those that differ
in some substantial way.
r~
next prev parent reply other threads:[~2022-09-08 8:58 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-06 12:22 [PATCH 00/11] Add support for the T-Head vendor extensions Christoph Muellner
2022-09-06 12:22 ` [PATCH 01/11] riscv: Add privilege level to DisasContext Christoph Muellner
2022-09-16 2:46 ` LIU Zhiwei
2022-09-16 6:00 ` Richard Henderson
2022-09-16 6:05 ` Richard Henderson
2022-09-16 6:21 ` LIU Zhiwei
2022-09-06 12:22 ` [PATCH 02/11] RISC-V: Adding T-Head CMO instructions Christoph Muellner
2022-09-16 2:47 ` LIU Zhiwei
2022-09-16 6:43 ` LIU Zhiwei
2022-09-16 7:59 ` Richard Henderson
2022-09-06 12:22 ` [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions Christoph Muellner
2022-09-08 7:29 ` Richard Henderson
2022-09-09 17:21 ` Christoph Müllner
2022-12-12 9:12 ` LIU Zhiwei
2022-12-12 9:21 ` LIU Zhiwei
2022-09-06 12:22 ` [PATCH 04/11] RISC-V: Adding T-Head Bitmanip instructions Christoph Muellner
2022-09-16 9:12 ` LIU Zhiwei
2022-09-06 12:22 ` [PATCH 05/11] RISC-V: Adding T-Head CondMov instructions Christoph Muellner
2022-09-06 12:22 ` [PATCH 06/11] RISC-V: Adding T-Head multiply-accumulate instructions Christoph Muellner
2022-09-06 12:22 ` [PATCH 07/11] RISC-V: Adding T-Head XMAE support Christoph Muellner
2022-09-06 12:22 ` [PATCH 08/11] RISC-V: Adding T-Head MemPair extension Christoph Muellner
2022-09-06 12:22 ` [PATCH 09/11] RISC-V: Adding T-Head MemIdx extension Christoph Muellner
2022-09-06 12:22 ` [PATCH 10/11] RISC-V: Adding T-Head FMemIdx extension Christoph Muellner
2022-09-08 7:45 ` Richard Henderson
2022-09-09 17:21 ` Christoph Müllner
2022-09-06 12:22 ` [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs Christoph Muellner
2022-09-08 7:46 ` Richard Henderson
2022-09-08 8:23 ` Christoph Müllner
2022-09-08 8:56 ` Richard Henderson [this message]
2022-09-08 9:01 ` Christoph Müllner
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