Re: [PATCH v2 6/9] pnv/xive2: Enable VST NVG and NVC index compression

["Cédric Le Goater" <clg@kaod.org>]

On 7/15/24 20:33, Michael Kowal wrote:
> From: Frederic Barrat <fbarrat@linux.ibm.com>
> 
> Enable NVG and NVC VST tables for index compression which indicates the number
> of bits the address is shifted to the right for the table accesses.
> The compression values are defined as:
>     0000 - No compression
>     0001 - 1 bit shift
>     0010 - 2 bit shift
>     ....
>     1000 - 8 bit shift
>     1001-1111 - No compression
> 
> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
> Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com>


Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.


> ---
>   hw/intc/pnv_xive2_regs.h |  2 ++
>   hw/intc/pnv_xive2.c      | 20 ++++++++++++++++++++
>   2 files changed, 22 insertions(+)
> 
> diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h
> index ca05255d20..e8b87b3d2c 100644
> --- a/hw/intc/pnv_xive2_regs.h
> +++ b/hw/intc/pnv_xive2_regs.h
> @@ -427,6 +427,8 @@
>   #define X_PC_NXC_PROC_CONFIG                    0x28A
>   #define PC_NXC_PROC_CONFIG                      0x450
>   #define   PC_NXC_PROC_CONFIG_WATCH_ASSIGN       PPC_BITMASK(0, 3)
> +#define   PC_NXC_PROC_CONFIG_NVG_TABLE_COMPRESS PPC_BITMASK(32, 35)
> +#define   PC_NXC_PROC_CONFIG_NVC_TABLE_COMPRESS PPC_BITMASK(36, 39)
>   
>   /* NxC Cache Watch 0 Specification */
>   #define X_PC_NXC_WATCH0_SPEC                    0x2A0
> diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
> index 9e45161869..b14fad1b2e 100644
> --- a/hw/intc/pnv_xive2.c
> +++ b/hw/intc/pnv_xive2.c
> @@ -217,6 +217,20 @@ static uint64_t pnv_xive2_vst_addr_indirect(PnvXive2 *xive, uint32_t type,
>       return pnv_xive2_vst_addr_direct(xive, type, vsd, (idx % vst_per_page));
>   }
>   
> +static uint8_t pnv_xive2_nvc_table_compress_shift(PnvXive2 *xive)
> +{
> +    uint8_t shift =  GETFIELD(PC_NXC_PROC_CONFIG_NVC_TABLE_COMPRESS,
> +                              xive->pc_regs[PC_NXC_PROC_CONFIG >> 3]);
> +    return shift > 8 ? 0 : shift;
> +}
> +
> +static uint8_t pnv_xive2_nvg_table_compress_shift(PnvXive2 *xive)
> +{
> +    uint8_t shift = GETFIELD(PC_NXC_PROC_CONFIG_NVG_TABLE_COMPRESS,
> +                             xive->pc_regs[PC_NXC_PROC_CONFIG >> 3]);
> +    return shift > 8 ? 0 : shift;
> +}
> +
>   static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive, uint32_t type, uint8_t blk,
>                                      uint32_t idx)
>   {
> @@ -238,6 +252,12 @@ static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive, uint32_t type, uint8_t blk,
>           return xive ? pnv_xive2_vst_addr(xive, type, blk, idx) : 0;
>       }
>   
> +    if (type == VST_NVG) {
> +        idx >>= pnv_xive2_nvg_table_compress_shift(xive);
> +    } else if (type == VST_NVC) {
> +        idx >>= pnv_xive2_nvc_table_compress_shift(xive);
> +    }
> +
>       if (VSD_INDIRECT & vsd) {
>           return pnv_xive2_vst_addr_indirect(xive, type, vsd, idx);
>       }