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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4771e387aa9sm47102705e9.4.2025.10.29.06.32.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Oct 2025 06:32:41 -0700 (PDT) Message-ID: Date: Wed, 29 Oct 2025 14:32:40 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] accel/tcg: Introduce and use MO_ALIGN_TLB_ONLY Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: Peter Maydell References: <20251022001741.222499-1-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20251022001741.222499-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 22/10/25 02:17, Richard Henderson wrote: > For Arm, we need 3 cases: (1) the alignment required when accessing > Normal memory, (2) the alignment required when accessing Device memory, > and (3) the atomicity of the access. > > When we added TLB_CHECK_ALIGNED, we assumed that cases 2 and 3 were > identical, and thus used memop_atomicity_bits for TLB_CHECK_ALIGNED. > > This is incorrect for multiple reasons, including that the atomicity > of the access is adjusted depending on whether or not we are executing > within a serial context. > > For Arm, what is true is that there is an underlying alignment > requirement of the access, and for that access Normal memory > will support unalignement. > > Introduce MO_ALIGN_TLB_ONLY to indicate that the alignment > specified in MO_AMASK only applies when the TLB entry has > TLB_CHECK_ALIGNED set; otherwise no alignment required. > > Introduce memop_tlb_alignment_bits with an additional bool > argument that specifies whether TLB_CHECK_ALIGNED is set. > All other usage of memop_alignment_bits assumes it is not. > > Remove memop_atomicity_bits as unused; it didn't properly > support MO_ATOM_SUBWORD anyway. > > Update target/arm finalize_memop_atom to set MO_ALIGN_TLB_ONLY > when strict alignment isn't otherwise required. > > Suggested-by: Peter Maydell > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3171 > Signed-off-by: Richard Henderson > --- > > PS: There are a number of uses of align_mem for AdvSIMD, SVE and SME. > I have not re-familiarized myself with the effects of SCR.A and > Normal/Device memory for those cases. I may well have missed something. > > --- > include/exec/memop.h | 43 +++++++++++++++------------------ > target/arm/tcg/translate.h | 4 +-- > accel/tcg/cputlb.c | 13 +--------- > target/arm/ptw.c | 2 +- > target/arm/tcg/translate-a64.c | 10 +++----- > target/arm/tcg/translate-neon.c | 2 +- > tcg/tcg.c | 10 +++++--- > 7 files changed, 35 insertions(+), 49 deletions(-) To the best of my knowledge, Reviewed-by: Philippe Mathieu-Daudé