Re: [PATCH] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names

[Richard Henderson <richard.henderson@linaro.org>]

On 11/21/24 11:16, Michael Tokarev wrote:
> According to Cortex-R5 r1p2 manual, register with opcode2=0 is
> BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
> qemu labels them.  Just swap the labels to avoid confusion, -
> both registers are implemented as always-zero.
> 
> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
> ---
>   target/arm/tcg/cpu32.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index 20c2737f17..2a77701f8d 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -574,9 +574,9 @@ static void cortex_a15_initfn(Object *obj)
>   
>   static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
>       /* Dummy the TCM region regs for the moment */
> -    { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
> +    { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
>         .access = PL1_RW, .type = ARM_CP_CONST },
> -    { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
> +    { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
>         .access = PL1_RW, .type = ARM_CP_CONST },
>       { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
>         .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~