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Fri, 22 Nov 2024 12:16:35 -0800 (PST) Received: from [192.168.170.227] ([187.210.107.181]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5f071fa5201sm280632eaf.25.2024.11.22.12.16.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 Nov 2024 12:16:35 -0800 (PST) Message-ID: Date: Fri, 22 Nov 2024 14:16:30 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names To: Michael Tokarev , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell References: <20241121171602.3273252-1-mjt@tls.msk.ru> Content-Language: en-US From: Richard Henderson In-Reply-To: <20241121171602.3273252-1-mjt@tls.msk.ru> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/21/24 11:16, Michael Tokarev wrote: > According to Cortex-R5 r1p2 manual, register with opcode2=0 is > BTCM and with opcode2=1 is ATCM, - exactly the opposite from how > qemu labels them. Just swap the labels to avoid confusion, - > both registers are implemented as always-zero. > > Signed-off-by: Michael Tokarev > --- > target/arm/tcg/cpu32.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c > index 20c2737f17..2a77701f8d 100644 > --- a/target/arm/tcg/cpu32.c > +++ b/target/arm/tcg/cpu32.c > @@ -574,9 +574,9 @@ static void cortex_a15_initfn(Object *obj) > > static const ARMCPRegInfo cortexr5_cp_reginfo[] = { > /* Dummy the TCM region regs for the moment */ > - { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, > + { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, > .access = PL1_RW, .type = ARM_CP_CONST }, > - { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, > + { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, > .access = PL1_RW, .type = ARM_CP_CONST }, > { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, > .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, Reviewed-by: Richard Henderson r~