* [PATCH] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
@ 2024-11-21 17:16 Michael Tokarev
2024-11-22 20:16 ` Richard Henderson
2024-11-25 11:58 ` Peter Maydell
0 siblings, 2 replies; 3+ messages in thread
From: Michael Tokarev @ 2024-11-21 17:16 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Peter Maydell, Michael Tokarev
According to Cortex-R5 r1p2 manual, register with opcode2=0 is
BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
qemu labels them. Just swap the labels to avoid confusion, -
both registers are implemented as always-zero.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
---
target/arm/tcg/cpu32.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 20c2737f17..2a77701f8d 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -574,9 +574,9 @@ static void cortex_a15_initfn(Object *obj)
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
/* Dummy the TCM region regs for the moment */
- { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST },
- { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST },
{ .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
.opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
--
2.39.5
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
2024-11-21 17:16 [PATCH] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names Michael Tokarev
@ 2024-11-22 20:16 ` Richard Henderson
2024-11-25 11:58 ` Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2024-11-22 20:16 UTC (permalink / raw)
To: Michael Tokarev, qemu-arm, qemu-devel; +Cc: Peter Maydell
On 11/21/24 11:16, Michael Tokarev wrote:
> According to Cortex-R5 r1p2 manual, register with opcode2=0 is
> BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
> qemu labels them. Just swap the labels to avoid confusion, -
> both registers are implemented as always-zero.
>
> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
> ---
> target/arm/tcg/cpu32.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index 20c2737f17..2a77701f8d 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -574,9 +574,9 @@ static void cortex_a15_initfn(Object *obj)
>
> static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
> /* Dummy the TCM region regs for the moment */
> - { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
> + { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
> .access = PL1_RW, .type = ARM_CP_CONST },
> - { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
> + { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
> .access = PL1_RW, .type = ARM_CP_CONST },
> { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
> .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
2024-11-21 17:16 [PATCH] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names Michael Tokarev
2024-11-22 20:16 ` Richard Henderson
@ 2024-11-25 11:58 ` Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2024-11-25 11:58 UTC (permalink / raw)
To: Michael Tokarev; +Cc: qemu-arm, qemu-devel
On Thu, 21 Nov 2024 at 17:16, Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> According to Cortex-R5 r1p2 manual, register with opcode2=0 is
> BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
> qemu labels them. Just swap the labels to avoid confusion, -
> both registers are implemented as always-zero.
>
> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
> ---
> target/arm/tcg/cpu32.c | 4 ++--
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-11-21 17:16 [PATCH] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names Michael Tokarev
2024-11-22 20:16 ` Richard Henderson
2024-11-25 11:58 ` Peter Maydell
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