qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: Zihao Yu <yuzihao@ict.ac.cn>, qemu-riscv@nongnu.org
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Subject: Re: [PATCH] tcg,riscv: Fix illegal shift instructions
Date: Wed, 16 Dec 2020 10:10:16 -0600	[thread overview]
Message-ID: <ab311e75-0689-03aa-adb0-6fe826473511@linaro.org> (raw)
In-Reply-To: <20201216081206.9628-1-yuzihao@ict.ac.cn>

On 12/16/20 2:12 AM, Zihao Yu wrote:
> * This bug can be reproduced by running the following guest instructions
>   on a RISC-V host.
> 
>   (1) xor %ecx,%ecx
>   (2) sar %cl,%eax
>   (3) cmovne %edi,%eax
> 
>   After optimization, the tcg instructions of (2) are
> 
>   movi_i32 tmp3,$0xffffffffffffffff  pref=all
>   sar_i32 tmp3,eax,tmp3              dead: 2  pref=all
>   mov_i32 cc_dst,eax                 sync: 0  dead: 1 pref=0xffc0300
>   mov_i32 cc_src,tmp3                sync: 0  dead: 0 1  pref=all
>   movi_i32 cc_op,$0x31               sync: 0  dead: 0  pref=all
> 
>   And the target assembly instructions of (2) are
> 
>   0x200808d618:  fffa5b9b          illegal
>   0x200808d61c:  03442423          sw              s4,40(s0)
>   0x200808d620:  03742623          sw              s7,44(s0)
>   0x200808d624:  03100b93          addi            s7,zero,49
>   0x200808d628:  03742a23          sw              s7,52(s0)
> 
> * Note that the `illegal` target instruction above should be
>   `sraiw s7,s4,0x1f` (41fa5b9b).

More precisely, the 'illegal' instruction should be *anything*, except for
'illegal'.  The result of the out-of-range shift is undefined, but TCG requires
that it not trap.  The undefined result should be unused.

In this particular case this is so, because cc_op == 0x31 == CC_OP_CLR, which
does not use either of cc_dst or cc_src.

We have make the same patch for other hosts, e.g. 1fd959466574 for tcg/sparc/.

I have queued the patch to tcg-next.


r~


      reply	other threads:[~2020-12-16 16:12 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-16  8:12 [PATCH] tcg,riscv: Fix illegal shift instructions Zihao Yu
2020-12-16 16:10 ` Richard Henderson [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ab311e75-0689-03aa-adb0-6fe826473511@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=Alistair.Francis@wdc.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=yuzihao@ict.ac.cn \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).