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Wed, 16 Dec 2020 08:10:24 -0800 (PST) Received: from [192.168.71.34] ([172.58.27.195]) by smtp.gmail.com with ESMTPSA id g26sm1334760qkl.60.2020.12.16.08.10.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Dec 2020 08:10:23 -0800 (PST) Subject: Re: [PATCH] tcg,riscv: Fix illegal shift instructions To: Zihao Yu , qemu-riscv@nongnu.org References: <20201216081206.9628-1-yuzihao@ict.ac.cn> From: Richard Henderson Message-ID: Date: Wed, 16 Dec 2020 10:10:16 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201216081206.9628-1-yuzihao@ict.ac.cn> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , "open list:All patches CC here" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/16/20 2:12 AM, Zihao Yu wrote: > * This bug can be reproduced by running the following guest instructions > on a RISC-V host. > > (1) xor %ecx,%ecx > (2) sar %cl,%eax > (3) cmovne %edi,%eax > > After optimization, the tcg instructions of (2) are > > movi_i32 tmp3,$0xffffffffffffffff pref=all > sar_i32 tmp3,eax,tmp3 dead: 2 pref=all > mov_i32 cc_dst,eax sync: 0 dead: 1 pref=0xffc0300 > mov_i32 cc_src,tmp3 sync: 0 dead: 0 1 pref=all > movi_i32 cc_op,$0x31 sync: 0 dead: 0 pref=all > > And the target assembly instructions of (2) are > > 0x200808d618: fffa5b9b illegal > 0x200808d61c: 03442423 sw s4,40(s0) > 0x200808d620: 03742623 sw s7,44(s0) > 0x200808d624: 03100b93 addi s7,zero,49 > 0x200808d628: 03742a23 sw s7,52(s0) > > * Note that the `illegal` target instruction above should be > `sraiw s7,s4,0x1f` (41fa5b9b). More precisely, the 'illegal' instruction should be *anything*, except for 'illegal'. The result of the out-of-range shift is undefined, but TCG requires that it not trap. The undefined result should be unused. In this particular case this is so, because cc_op == 0x31 == CC_OP_CLR, which does not use either of cc_dst or cc_src. We have make the same patch for other hosts, e.g. 1fd959466574 for tcg/sparc/. I have queued the patch to tcg-next. r~