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([2a01:e0a:280:24f0:9db0:474c:ff43:9f5c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47a89f1eb60sm15735305e9.20.2025.12.11.07.14.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Dec 2025 07:14:25 -0800 (PST) Message-ID: Date: Thu, 11 Dec 2025 16:14:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 27/33] hw/arm/smmuv3-accel: Add a property to specify RIL support To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: eric.auger@redhat.com, peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, yi.l.liu@intel.com, kjaju@nvidia.com References: <20251120132213.56581-1-skolothumtho@nvidia.com> <20251120132213.56581-28-skolothumtho@nvidia.com> Content-Language: en-US, fr From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Autocrypt: addr=clg@redhat.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/20/25 14:22, Shameer Kolothum wrote: > Currently QEMU SMMUv3 has RIL support by default. But if accelerated mode > is enabled, RIL has to be compatible with host SMMUv3 support. > > Add a property so that the user can specify this. > > Reviewed-by: Jonathan Cameron > Tested-by: Zhangfei Gao > Reviewed-by: Eric Auger > Signed-off-by: Shameer Kolothum > --- > hw/arm/smmuv3-accel.c | 14 ++++++++++++-- > hw/arm/smmuv3-accel.h | 4 ++++ > hw/arm/smmuv3.c | 12 ++++++++++++ > include/hw/arm/smmuv3.h | 1 + > 4 files changed, 29 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > index aae7840c40..b6429c8b42 100644 > --- a/hw/arm/smmuv3-accel.c > +++ b/hw/arm/smmuv3-accel.c > @@ -62,8 +62,8 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, > return false; > } > > - /* QEMU SMMUv3 supports Range Invalidation by default */ > - if (FIELD_EX32(info->idr[3], IDR3, RIL) != > + /* User can disable QEMU SMMUv3 Range Invalidation support */ > + if (FIELD_EX32(info->idr[3], IDR3, RIL) > > FIELD_EX32(s->idr[3], IDR3, RIL)) { > error_setg(errp, "Host SMMUv3 doesn't support Range Invalidation"); > return false; > @@ -639,6 +639,16 @@ static const PCIIOMMUOps smmuv3_accel_ops = { > .get_msi_direct_gpa = smmuv3_accel_get_msi_gpa, > }; > > +void smmuv3_accel_idr_override(SMMUv3State *s) > +{ > + if (!s->accel) { > + return; > + } Those : if (s->accel) in the code reveal a modeling issue. > + > + /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it */ > + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); > +} > + > /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ > bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp) > { > diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h > index 7186817264..2f2904d86b 100644 > --- a/hw/arm/smmuv3-accel.h > +++ b/hw/arm/smmuv3-accel.h > @@ -47,6 +47,7 @@ bool smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange *range, > bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp); > bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev, > Error **errp); > +void smmuv3_accel_idr_override(SMMUv3State *s); > void smmuv3_accel_reset(SMMUv3State *s); > #else > static inline void smmuv3_accel_init(SMMUv3State *s) > @@ -74,6 +75,9 @@ smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev, > { > return true; > } > +static inline void smmuv3_accel_idr_override(SMMUv3State *s) > +{ > +} > static inline void smmuv3_accel_reset(SMMUv3State *s) > { > } > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 8352dd5757..296afbe503 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -305,6 +305,7 @@ static void smmuv3_init_id_regs(SMMUv3State *s) > s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); > s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); > s->aidr = 0x1; > + smmuv3_accel_idr_override(s); > } > > static void smmuv3_reset(SMMUv3State *s) > @@ -1924,6 +1925,13 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp) > return false; > } > #endif > + if (!s->accel) { > + if (!s->ril) { > + error_setg(errp, "ril can only be disabled if accel=on"); > + return false; > + } > + return true; > + } > return true; > } > > @@ -2047,6 +2055,8 @@ static const Property smmuv3_properties[] = { > DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), > /* GPA of MSI doorbell, for SMMUv3 accel use. */ > DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), > + /* RIL can be turned off for accel cases */ > + DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), yep. Adding a QOM model would clarify a lot of things. C. > }; > > static void smmuv3_instance_init(Object *obj) > @@ -2072,6 +2082,8 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data) > object_class_property_set_description(klass, "accel", > "Enable SMMUv3 accelerator support. Allows host SMMUv3 to be " > "configured in nested mode for vfio-pci dev assignment"); > + object_class_property_set_description(klass, "ril", > + "Disable range invalidation support (for accel=on)"); > } > > static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, > diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h > index 9c39acd5ca..533a2182e8 100644 > --- a/include/hw/arm/smmuv3.h > +++ b/include/hw/arm/smmuv3.h > @@ -69,6 +69,7 @@ struct SMMUv3State { > struct SMMUv3AccelState *s_accel; > uint64_t msi_gpa; > Error *migration_blocker; > + bool ril; > }; > > typedef enum {