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([2001:8003:3a49:fd00:d2cd:dac2:7e7f:5850]) by smtp.gmail.com with ESMTPSA id l191sm2284642pga.65.2022.02.04.12.55.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Feb 2022 12:55:59 -0800 (PST) Message-ID: Date: Sat, 5 Feb 2022 07:55:54 +1100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v4 5/5] tcg/sparc: Support unaligned access for user-only Content-Language: en-US To: Peter Maydell References: <20220204070011.573941-1-richard.henderson@linaro.org> <20220204070011.573941-6-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::430 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/5/22 06:07, Peter Maydell wrote: >> + /* >> + * Overalignment: When we're asking for really large alignment, >> + * the actual access is always done above and all we need to do >> + * here is invoke the handler for SIGBUS. >> + */ > > I thought the access was in an annulled delay slot and so won't > be "done above" ? Bad wording, I suppose. If the alignment check succeeds, then access is done above. If the alignment check fails, there is no access to be performed, only to report failure. >> + switch ((unsigned)memop) { >> + case MO_BEUW | MO_UNALN: >> + case MO_BESW | MO_UNALN: >> + case MO_BEUL | MO_ALIGN_2: >> + case MO_BESL | MO_ALIGN_2: >> + case MO_BEUQ | MO_ALIGN_4: >> + /* Two loads: shift and combine. */ >> + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, 0, >> + qemu_ld_opc[a_bits | MO_BE | (memop & MO_SIGN)]); >> + tcg_out_ldst(s, data, TCG_REG_T1, 1 << a_bits, >> + qemu_ld_opc[a_bits | MO_BE]); >> + tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, 8 << a_bits, SHIFT_SLLX); > > Why are we calculating the offset in memory of the second half of > the data and the amount to shift it by using the alignment-bits > rather than the size-bits ? Because of the cases we know that > here a_bits == s_bits - 1, but I think it would be clearer to > work in terms of the size. Ok. >> + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 3, ARITH_ANDN); >> + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, 0, LDUW); > > Doesn't this give the wrong fault-address value to the guest > (ie not the address it used for the load, but a rounded-down one) > if we take a SIGSEGV? Or do we fix that up elsewhere? Oops, no. Perhaps a single byte load to the zero register would fix that, without having to go to full load-by-parts. >> + case MO_BEUQ | MO_ALIGN_2: >> + /* >> + * An extra test to verify alignment 2 is 5 insns, which >> + * is more than we would save by using the slightly smaller >> + * unaligned sequence above. >> + */ >> + tcg_out_ldst(s, data, TCG_REG_T1, 0, LDUH); >> + for (int i = 2; i < 8; i += 2) { >> + tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, LDUW); > > Isn't this loading 2 + 3 * 4 == 14 bytes? Oops. Got confused with the qemu vs sparc "word" there for a moment. r~