From: Chao Liu <chao.liu.riscv@isrc.iscas.ac.cn>
To: dbarboza@ventanamicro.com
Cc: ajones@ventanamicro.com, alistair.francis@wdc.com,
liwei1518@gmail.com, palmer@dabbelt.com, qemu-devel@nongnu.org,
qemu-riscv@nongnu.org, wu.fei9@sanechips.com.cn,
zhiwei_liu@linux.alibaba.com
Subject: Re: [PATCH v3 2/4] target/riscv: Add server platform reference cpu
Date: Thu, 30 Oct 2025 23:01:57 +0800 [thread overview]
Message-ID: <ab8161b3-d4e9-4573-b13f-e13b9c6b322e@isrc.iscas.ac.cn> (raw)
In-Reply-To: <20250528200129.1548259-3-dbarboza@ventanamicro.com>
On Wed, May 28, 2025 at 05:01:29PM -0300, Daniel Henrique Barboza wrote:
>rom: Fei Wu <wu.fei9@sanechips.com.cn>
>
>he harts requirements of RISC-V server platform [1] require RVA23 ISA
>rofile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides
> virt CPU type (rvsp-ref) as compliant as possible.
>
>1] https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc
>
>igned-off-by: Fei Wu <fei2.wu@intel.com>
>igned-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>--
>target/riscv/cpu-qom.h | 1 +
>target/riscv/cpu.c | 11 +++++++++++
>2 files changed, 12 insertions(+)
>
>iff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
>ndex 1ee05eb393..70978fd53c 100644
>-- a/target/riscv/cpu-qom.h
>++ b/target/riscv/cpu-qom.h
>@ -55,6 +55,7 @@
>#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
>#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
>#define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu")
>#define TYPE_RISCV_CPU_RVSP_REF RISCV_CPU_TYPE_NAME("rvsp-ref")
>#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
>
>OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
>iff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>ndex 4a30cf8444..ec2fbc0e78 100644
>-- a/target/riscv/cpu.c
>++ b/target/riscv/cpu.c
>@ -3166,6 +3166,17 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .cfg.max_satp_mode = VM_1_10_SV39,
> ),
>
> DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSP_REF, TYPE_RISCV_VENDOR_CPU,
I'm not sure the parent type TYPE_RISCV_VENDOR_CPU is right here.
To be on the safe side, I tested this CPU type using an openEuler image that
can boot on a virtual machine. This image supports rva23s64, and my command is
as follows:
cmd="$QEMU_SYSTEM_RISCV64 \
-nographic -machine virt,pflash0=pflash0,pflash1=pflash1,acpi=off \
-cpu rvsp-ref \
-smp "$vcpu" -m "$memory"G \
-blockdev node-name=pflash0,driver=file,read-only=on,filename="$fw1" \
-blockdev node-name=pflash1,driver=file,filename="$fw2" \
-drive file="$drive",format=qcow2,id=hd0,if=none \
-object rng-random,filename=/dev/urandom,id=rng0 \
-device virtio-vga \
-device virtio-rng-device,rng=rng0 \
-device virtio-blk-device,drive=hd0 \
-device virtio-net-device,netdev=usernet \
-netdev user,id=usernet,hostfwd=tcp::"$ssh_port"-:22 \
-device qemu-xhci -usb -device usb-kbd -device usb-tablet"
This process gets stuck at the initialization stage:
```
Loading Linux 6.6.0-102.0.0.5.oe2509.riscv64 ...
Loading initial ramdisk ...
```
If I use the parameter `-cpu rva23s64`, the system can boot normally.
I tried changing TYPE_RISCV_VENDOR_CPU to TYPE_RISCV_BARE_CPU and found that
the system then boots normally.
However, I haven’t conducted an in-depth analysis yet, so the issue might be
with my system image.
Thanks,
Chao
> .misa_mxl_max = MXL_RV64,
> .profile = &RVA23S64,
>
> /* ISA extensions */
> .cfg.ext_zkr = true,
> .cfg.ext_svadu = true,
>
> .cfg.max_satp_mode = VM_1_10_SV57,
> ),
>
next prev parent reply other threads:[~2025-10-30 15:03 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-28 20:01 [PATCH v3 0/4] hw/riscv: Add Server Platform Reference Board Daniel Henrique Barboza
2025-05-28 20:01 ` [PATCH v3 1/4] target/riscv/cpu.c: remove 'bare' condition for .profile Daniel Henrique Barboza
2025-05-29 11:56 ` Andrew Jones
2025-05-28 20:01 ` [PATCH v3 2/4] target/riscv: Add server platform reference cpu Daniel Henrique Barboza
2025-05-29 11:56 ` Andrew Jones
2025-10-30 15:01 ` Chao Liu [this message]
2025-10-30 15:14 ` Daniel Henrique Barboza
2025-10-30 16:45 ` Chao Liu
2025-05-28 20:01 ` [PATCH v3 3/4] hw/riscv: Add server platform reference machine Daniel Henrique Barboza
2025-05-29 12:31 ` Andrew Jones
2025-10-30 22:27 ` Philippe Mathieu-Daudé
2025-05-28 20:01 ` [PATCH v3 4/4] hw/riscv/server_platform_ref.c: add riscv-iommu-sys Daniel Henrique Barboza
2025-05-29 12:33 ` Andrew Jones
2025-10-30 11:40 ` Chao Liu
2025-10-30 13:23 ` Daniel Henrique Barboza
2025-10-30 11:48 ` [PATCH v3 0/4] hw/riscv: Add Server Platform Reference Board Chao Liu
2025-10-30 13:33 ` Daniel Henrique Barboza
2025-10-30 15:23 ` Chao Liu
2025-10-30 15:37 ` Daniel Henrique Barboza
2025-10-30 20:53 ` Andrew Jones
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ab8161b3-d4e9-4573-b13f-e13b9c6b322e@isrc.iscas.ac.cn \
--to=chao.liu.riscv@isrc.iscas.ac.cn \
--cc=ajones@ventanamicro.com \
--cc=alistair.francis@wdc.com \
--cc=dbarboza@ventanamicro.com \
--cc=liwei1518@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=wu.fei9@sanechips.com.cn \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).