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([2605:ef80:80c3:3064:7ddf:d6a7:e3e2:a0bf]) by smtp.gmail.com with ESMTPSA id q16-20020a056e02079000b002eb75fb01dbsm7695827ils.28.2022.09.15.01.16.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Sep 2022 01:16:15 -0700 (PDT) Message-ID: Date: Thu, 15 Sep 2022 09:16:03 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [RFC PATCH 3/4] hw/intc/gic: use MxTxAttrs to divine accessing CPU Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell References: <20220914160955.812151-1-alex.bennee@linaro.org> <20220914160955.812151-4-alex.bennee@linaro.org> From: Richard Henderson In-Reply-To: <20220914160955.812151-4-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::d36; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd36.google.com X-Spam_score_int: -36 X-Spam_score: -3.7 X-Spam_bar: --- X-Spam_report: (-3.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.583, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/14/22 17:09, Alex Bennée wrote: > Now that MxTxAttrs encodes a CPU we should use that to figure it out. > This solves edge cases like accessing via gdbstub or qtest. > > Signed-off-by: Alex Bennée > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 > --- > hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- > 1 file changed, 22 insertions(+), 17 deletions(-) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index 492b2421ab..7feedac735 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -56,17 +56,22 @@ static const uint8_t gic_id_gicv2[] = { > 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 > }; > > -static inline int gic_get_current_cpu(GICState *s) > +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) > { > - if (!qtest_enabled() && s->num_cpu > 1) { > - return current_cpu->cpu_index; > - } > - return 0; > + /* > + * Something other than a CPU accessing the GIC would be a bug as > + * would a CPU index higher than the GICState expects to be > + * handling > + */ > + g_assert(attrs.requester_cpu == 1); Better without "== 1" -- this field ought to be boolean. > + g_assert(attrs.requester_id < s->num_cpu); Do we still need the qtest_enabled test to short circuit the num_cpu test within the assert? I guess if tests aren't failing then perhaps we don't... Otherwise, Reviewed-by: Richard Henderson r~