From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [PATCH v1 1/1] target/riscv: Print CPU and privledge in disas
Date: Thu, 26 Sep 2019 17:45:30 -0700 [thread overview]
Message-ID: <ab8f108eceb973aaee565bb1fe347fcf8c788f5b.1569545120.git.alistair.francis@wdc.com> (raw)
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index adeddb85f6..537af0003e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -810,7 +810,14 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
{
+#ifndef CONFIG_USER_ONLY
+ RISCVCPU *rvcpu = RISCV_CPU(cpu);
+ CPURISCVState *env = &rvcpu->env;
+#endif
qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+#ifndef CONFIG_USER_ONLY
+ qemu_log("CPU: %d; priv: "TARGET_FMT_ld"\n", cpu->cpu_index, env->priv);
+#endif
log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
}
--
2.23.0
next reply other threads:[~2019-09-27 0:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-27 0:45 Alistair Francis [this message]
2019-09-27 3:07 ` [PATCH v1 1/1] target/riscv: Print CPU and privledge in disas Bin Meng
2019-09-27 9:09 ` Philippe Mathieu-Daudé
2019-09-27 17:03 ` Alistair Francis
2019-09-27 17:17 ` Richard Henderson
2019-09-27 17:23 ` Alistair Francis
2019-09-27 17:53 ` Richard Henderson
2019-09-27 21:29 ` Alistair Francis
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