From: liweiwei <liweiwei@iscas.ac.cn>
To: CHEN Yi <chenyi2000@zju.edu.cn>, qemu-devel@nongnu.org
Cc: liweiwei@iscas.ac.cn, Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
"open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap
Date: Thu, 9 Mar 2023 23:27:45 +0800 [thread overview]
Message-ID: <aba228b8-03fa-c096-72bf-1b920cbe4f9f@iscas.ac.cn> (raw)
In-Reply-To: <3b6c6f15.8a1c1.186c6e4ff7d.Coremail.chenyi2000@zju.edu.cn>
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On 2023/3/9 23:02, CHEN Yi wrote:
>
>
>
> -----Original Messages-----
> *From:*liweiwei <liweiwei@iscas.ac.cn>
> *Sent Time:*2023-03-09 15:48:17 (Thursday)
> *To:* chenyi2000@zju.edu.cn, qemu-devel@nongnu.org
> *Cc:* "Palmer Dabbelt" <palmer@dabbelt.com>, "Alistair Francis"
> <alistair.francis@wdc.com>, "Bin Meng" <bin.meng@windriver.com>,
> "Daniel Henrique Barboza" <dbarboza@ventanamicro.com>, "Liu
> Zhiwei" <zhiwei_liu@linux.alibaba.com>, "open list:RISC-V TCG
> CPUs" <qemu-riscv@nongnu.org>
> *Subject:* Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap
>
>
> On 2023/3/8 20:34, chenyi2000@zju.edu.cn wrote:
>> From: Yi Chen<chenyi2000@zju.edu.cn> Trap accesses to hgatp if MSTATUS_TVM is enabled.
>> Don't trap accesses to vsatp even if MSTATUS_TVM is enabled.
>>
>> Signed-off-by: Yi Chen<chenyi2000@zju.edu.cn> ---
>> target/riscv/csr.c | 18 ++++++++++++++----
>> 1 file changed, 14 insertions(+), 4 deletions(-)
>>
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index ab56663..09bc780 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -2655,7 +2655,7 @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
>> return RISCV_EXCP_NONE;
>> }
>>
>> - if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
>> + if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) && get_field(env->mstatus, MSTATUS_TVM)) {
>> return RISCV_EXCP_ILLEGAL_INST;
>
> This line seems too long (> 80).
>
> And hstatus.VTVM should also be taken into consideration.
>
> Similar to following write_satp.
>
>> } else {
>> *val = env->satp;
>> @@ -2683,7 +2683,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
>> }
>>
>> if (vm && mask) {
>> - if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
>> + if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) && get_field(env->mstatus, MSTATUS_TVM)) {
>> return RISCV_EXCP_ILLEGAL_INST;
>> } else {
>> /*
>
>
> Thanks a lot. In the next version, I will fix the code style issue and
> consider hstatus.VTVM.
>
>
>> @@ -3047,14 +3047,24 @@ static RISCVException read_hgeip(CPURISCVState *env, int csrno,
>> static RISCVException read_hgatp(CPURISCVState *env, int csrno,
>> target_ulong *val)
>> {
>> - *val = env->hgatp;
>> + if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
>> + return RISCV_EXCP_ILLEGAL_INST;
>
> This check will do before privilege check in riscv_csrrw_check. So
> it will make VS mode access trigger
>
> ILLEGAL_INST exception, However, it should be VIRTUAL_INST
> exception in this case.
>
> Regards,
>
> Weiwei Li
>
>
>
> In riscv_csrrw(), riscv_csrrw_check() is called before
> riscv_csrrw_do64(). So I think VIRTUAL_INST will be triggered. Could
> you please explain why this check will do before the privilege check
> in riscv_csrrw_check? I'm new to Qemu source code and am sorry I can't
> understand that.
>
>
Yeah, You are right. Sorry that I mistook this check for check in the
predicate.
By the way, I think this check is better to be done in the predicate.
Regards,
Weiwei Li
>> + } else {
>> + *val = env->hgatp;
>> + }
>> +
>> return RISCV_EXCP_NONE;
>> }
>>
>> static RISCVException write_hgatp(CPURISCVState *env, int csrno,
>> target_ulong val)
>> {
>> - env->hgatp = val;
>> + if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
>> + return RISCV_EXCP_ILLEGAL_INST;
>> + } else {
>> + env->hgatp = val;
>> + }
>> +
>> return RISCV_EXCP_NONE;
>> }
>>
>
>
> Thanks,
>
> Yi
>
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next prev parent reply other threads:[~2023-03-09 15:28 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-08 12:34 [PATCH] target/riscv/csr.c: fix H extension TVM trap chenyi2000
2023-03-08 19:44 ` Daniel Henrique Barboza
2023-03-09 14:42 ` CHEN Yi
2023-03-09 7:48 ` liweiwei
2023-03-09 15:02 ` CHEN Yi
2023-03-09 15:27 ` liweiwei [this message]
2023-03-10 2:12 ` LIU Zhiwei
2023-03-10 9:08 ` CHEN Yi
2023-03-10 9:18 ` LIU Zhiwei
2023-03-10 10:33 ` CHEN Yi
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