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Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v5 17/36] tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64} Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: alex.bennee@linaro.org References: <20230126043824.54819-1-richard.henderson@linaro.org> <20230126043824.54819-18-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230126043824.54819-18-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.15, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 26/1/23 05:38, Richard Henderson wrote: > Normally this is automatically handled by the CF_PARALLEL checks > with in tcg_gen_atomic_cmpxchg_i{32,64}, but x86 has a special > case of !PREFIX_LOCK where it always wants the non-atomic version. > > Split these out so that x86 does not have to roll its own. > > Signed-off-by: Richard Henderson > --- > include/tcg/tcg-op.h | 4 ++ > tcg/tcg-op.c | 154 +++++++++++++++++++++++++++---------------- > 2 files changed, 101 insertions(+), 57 deletions(-) > +void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, > + TCGv_i64 newv, TCGArg idx, MemOp memop) > +{ > + TCGv_i64 t1, t2; > + This block from here ... > + if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { > + tcg_gen_nonatomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), > + TCGV_LOW(newv), idx, memop); > + if (memop & MO_SIGN) { > + tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); > + } else { > + tcg_gen_movi_i32(TCGV_HIGH(retv), 0); > + } > + return; > + } ... to here, > + t1 = tcg_temp_new_i64(); > + t2 = tcg_temp_new_i64(); > + > + tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); > + > + tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); > + tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); > + tcg_gen_qemu_st_i64(t2, addr, idx, memop); > + tcg_temp_free_i64(t2); > + > + if (memop & MO_SIGN) { > + tcg_gen_ext_i64(retv, t1, memop); > + } else { > + tcg_gen_mov_i64(retv, t1); > + } > + tcg_temp_free_i64(t1); > } > > void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, > TCGv_i64 newv, TCGArg idx, MemOp memop) > { > - memop = tcg_canonicalize_memop(memop, 1, 0); > - > if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { > - TCGv_i64 t1 = tcg_temp_new_i64(); > - TCGv_i64 t2 = tcg_temp_new_i64(); > + tcg_gen_nonatomic_cmpxchg_i64(retv, addr, cmpv, newv, idx, memop); > + return; > + } > > - tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); > - > - tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); > - tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); > - tcg_gen_qemu_st_i64(t2, addr, idx, memop); > - tcg_temp_free_i64(t2); > - > - if (memop & MO_SIGN) { > - tcg_gen_ext_i64(retv, t1, memop); > - } else { > - tcg_gen_mov_i64(retv, t1); > - } > - tcg_temp_free_i64(t1); > - } else if ((memop & MO_SIZE) == MO_64) { > -#ifdef CONFIG_ATOMIC64 > + if ((memop & MO_SIZE) == MO_64) { > gen_atomic_cx_i64 gen; > - MemOpIdx oi; > > + memop = tcg_canonicalize_memop(memop, 1, 0); > gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; > - tcg_debug_assert(gen != NULL); > + if (gen) { > + MemOpIdx oi = make_memop_idx(memop, idx); > + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); > + return; > + } > > - oi = make_memop_idx(memop, idx); > - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); > -#else > gen_helper_exit_atomic(cpu_env); > - /* Produce a result, so that we have a well-formed opcode stream > - with respect to uses of the result in the (dead) code following. */ > + > + /* > + * Produce a result for a well-formed opcode stream. This satisfies > + * liveness for set before used, which happens before this dead code > + * is removed. > + */ > tcg_gen_movi_i64(retv, 0); > -#endif /* CONFIG_ATOMIC64 */ > + return; > + } and this one here: > + if (TCG_TARGET_REG_BITS == 32) { > + tcg_gen_atomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), > + TCGV_LOW(newv), idx, memop); > + if (memop & MO_SIGN) { > + tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); > + } else { > + tcg_gen_movi_i32(TCGV_HIGH(retv), 0); > + } belong to a subsequent patch IMO. Otherwise LGTM. > } else { > TCGv_i32 c32 = tcg_temp_new_i32(); > TCGv_i32 n32 = tcg_temp_new_i32();