From: Richard Henderson <richard.henderson@linaro.org>
To: Deepak Gupta <debug@rivosinc.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
andy.chiu@sifive.com, kito.cheng@sifive.com
Subject: Re: [PATCH v12 11/20] target/riscv: introduce ssp and enabling controls for zicfiss
Date: Fri, 30 Aug 2024 15:20:04 +1000 [thread overview]
Message-ID: <abc033ff-7638-4d2d-b2d7-65b3c88311e8@linaro.org> (raw)
In-Reply-To: <20240829233425.1005029-12-debug@rivosinc.com>
On 8/30/24 09:34, Deepak Gupta wrote:
> +bool cpu_get_bcfien(CPURISCVState *env)
It occurs to me that a better name would be "cpu_get_sspen".
The backward cfi is merely a consequence of the shadow stack.
> +{
> + /* no cfi extension, return false */
> + if (!env_archcpu(env)->cfg.ext_zicfiss) {
> + return false;
> + }
> +
> + switch (env->priv) {
> + case PRV_U:
> + if (riscv_has_ext(env, RVS)) {
> + return env->senvcfg & SENVCFG_SSE;
> + }
> + return env->menvcfg & MENVCFG_SSE;
> +#ifndef CONFIG_USER_ONLY
> + case PRV_S:
> + if (env->virt_enabled) {
> + return env->henvcfg & HENVCFG_SSE;
> + }
> + return env->menvcfg & MENVCFG_SSE;
> + case PRV_M: /* M-mode shadow stack is always on if hart implements */
> + return true;
From the manual:
Activating Zicfiss in M-mode is currently not supported. Additionally, when S-mode is not
implemented, activation in U-mode is also not supported.
So two of the cases above are wrong.
r~
next prev parent reply other threads:[~2024-08-30 5:20 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-29 23:34 [PATCH v12 00/20] riscv support for control flow integrity extensions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 01/20] target/riscv: expose *envcfg csr and priv to qemu-user as well Deepak Gupta
2024-08-30 2:10 ` Richard Henderson
2024-08-29 23:34 ` [PATCH v12 02/20] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 04/20] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-30 2:13 ` Richard Henderson
2024-08-29 23:34 ` [PATCH v12 05/20] target/riscv: additional code information for sw check Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 07/20] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 08/20] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 09/20] target/riscv: Expose zicfilp extension as a cpu property Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 10/20] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 11/20] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-30 5:20 ` Richard Henderson [this message]
2024-08-30 5:56 ` Deepak Gupta
2024-08-30 16:30 ` Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 12/20] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 13/20] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 14/20] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 15/20] target/riscv: update `decode_save_opc` to store extra word2 Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 16/20] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 17/20] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 18/20] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 19/20] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 20/20] target/riscv: Expose zicfiss extension as a cpu property Deepak Gupta
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=abc033ff-7638-4d2d-b2d7-65b3c88311e8@linaro.org \
--to=richard.henderson@linaro.org \
--cc=Alistair.Francis@wdc.com \
--cc=andy.chiu@sifive.com \
--cc=bmeng.cn@gmail.com \
--cc=dbarboza@ventanamicro.com \
--cc=debug@rivosinc.com \
--cc=jim.shu@sifive.com \
--cc=kito.cheng@sifive.com \
--cc=liwei1518@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).