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([2a02:c7c:74db:8d00:ad29:f02c:48a2:269c]) by smtp.gmail.com with ESMTPSA id x24-20020a1c7c18000000b003f183127434sm36428174wmc.30.2023.05.02.12.19.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 May 2023 12:19:39 -0700 (PDT) Message-ID: Date: Tue, 2 May 2023 20:19:38 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v3 00/57] tcg: Improve atomicity support Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, philmd@linaro.org References: <20230425193146.2106111-1-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.422, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/2/23 17:11, Peter Maydell wrote: > On Tue, 25 Apr 2023 at 20:32, Richard Henderson > wrote: >> >> v1: https://lore.kernel.org/qemu-devel/20221118094754.242910-1-richard.henderson@linaro.org/ >> v2: https://lore.kernel.org/qemu-devel/20230216025739.1211680-1-richard.henderson@linaro.org/ >> >> Based-on: 20230424054105.1579315-1-richard.henderson@linaro.org >> ("[PATCH v3 00/57] tcg: Simplify calls to load/store helpers") >> >> The main objective here is to support Arm FEAT_LSE2, which says that any >> single memory access that does not cross a 16-byte boundary is atomic. >> This is the MO_ATOM_WITHIN16 control. >> >> While I'm touching all of this, a secondary objective is to handle the >> atomicity of the IBM machines. Both Power and s390x treat misaligned >> accesses as atomic on the lsb of the pointer. For instance, an 8-byte >> access at ptr % 8 == 4 will appear as two atomic 4-byte accesses, and >> ptr % 4 == 2 will appear as four 3-byte accesses. > > I hope you mean "four 2-byte accesses", although I'm never > quite sure how odd s390x can get :-) Heh. Yes, of course. r~