From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair23@gmail.com>,
Atish Kumar Patra <atishp@rivosinc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
qemu-devel@nongnu.org,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL 26/30] target/riscv: Do not setup pmu timer if OF is disabled
Date: Tue, 23 Jul 2024 10:49:57 +1000 [thread overview]
Message-ID: <abef9f20-b5be-44ca-8bd6-a1184ac53b25@linaro.org> (raw)
In-Reply-To: <CAKmqyKM_gcuNvR=2Rff29C5EAFTNiyz3XNTH5H4wt9W5JbmO+w@mail.gmail.com>
On 7/23/24 10:43, Alistair Francis wrote:
>>> #define get_field(reg, mask) (((reg) & \
>>> (uint64_t)(mask)) / ((mask) & ~((mask) << 1)))
>>>
>>> Notice that part of this expression is "(mask) << 1". So Coverity complains
>>> that we took a constant value and shifted it right off the top.
>>>
>>> I think this is probably a false positive, but why is target/riscv
>>> using its own ad-hoc macros for extracting bitfields? We have
>>> a standard set of extract/deposit macros in bitops.h, and not
>>
>> Thanks for pointing those out. I checked the get_field usage from the
>> beginning of riscv support 6 years back.
>> There are tons of users of get_field in a bunch of riscv sources. I
>> guess it was just added once and everybody kept using it
>> without switching to generic functions.
>
> I think you are right about that
I think this macro comes from spike, and it was copied in with a bunch of other basic isa
defines at the start of the qemu port.
r~
next prev parent reply other threads:[~2024-07-23 0:51 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-18 2:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
2024-07-18 2:09 ` [PULL 01/30] target/riscv: Add zimop extension Alistair Francis
2024-07-18 2:09 ` [PULL 02/30] disas/riscv: Support zimop disassemble Alistair Francis
2024-07-18 2:09 ` [PULL 03/30] target/riscv: Add zcmop extension Alistair Francis
2024-07-18 2:09 ` [PULL 04/30] disas/riscv: Support zcmop disassemble Alistair Francis
2024-07-18 2:09 ` [PULL 05/30] target/riscv: Support Zama16b extension Alistair Francis
2024-07-22 23:32 ` Alistair Francis
2024-07-23 1:15 ` LIU Zhiwei
2024-07-18 2:09 ` [PULL 06/30] target/riscv: Move gen_amo before implement Zabha Alistair Francis
2024-07-18 2:09 ` [PULL 07/30] target/riscv: Add AMO instructions for Zabha Alistair Francis
2024-07-18 2:09 ` [PULL 08/30] target/riscv: Move gen_cmpxchg before adding amocas.[b|h] Alistair Francis
2024-07-18 2:09 ` [PULL 09/30] target/riscv: Add amocas.[b|h] for Zabha Alistair Francis
2024-07-18 2:09 ` [PULL 10/30] target/riscv: Expose zabha extension as a cpu property Alistair Francis
2024-07-18 2:09 ` [PULL 11/30] disas/riscv: Support zabha disassemble Alistair Francis
2024-07-18 2:09 ` [PULL 12/30] target/riscv: Validate the mode in write_vstvec Alistair Francis
2024-07-18 2:09 ` [PULL 13/30] disas/riscv: Add decode for Zawrs extension Alistair Francis
2024-07-18 2:09 ` [PULL 14/30] target/riscv/kvm: update KVM regs to Linux 6.10-rc5 Alistair Francis
2024-07-18 2:09 ` [PULL 15/30] target/riscv: Combine set_mode and set_virt functions Alistair Francis
2024-07-18 2:09 ` [PULL 16/30] target/riscv: Fix the predicate functions for mhpmeventhX CSRs Alistair Francis
2024-07-18 2:09 ` [PULL 17/30] target/riscv: Add cycle & instret privilege mode filtering properties Alistair Francis
2024-07-18 2:10 ` [PULL 18/30] target/riscv: Add cycle & instret privilege mode filtering definitions Alistair Francis
2024-07-18 2:10 ` [PULL 19/30] target/riscv: Add cycle & instret privilege mode filtering support Alistair Francis
2024-07-18 2:10 ` [PULL 20/30] target/riscv: Only set INH fields if priv mode is available Alistair Francis
2024-07-18 2:10 ` [PULL 21/30] target/riscv: Implement privilege mode filtering for cycle/instret Alistair Francis
2024-07-20 14:43 ` Peter Maydell
2024-07-22 23:24 ` Atish Kumar Patra
2025-08-21 9:25 ` Philippe Mathieu-Daudé
2025-10-03 1:39 ` Alistair Francis
2024-07-18 2:10 ` [PULL 22/30] target/riscv: Save counter values during countinhibit update Alistair Francis
2024-07-18 2:10 ` [PULL 23/30] target/riscv: Enforce WARL behavior for scounteren/hcounteren Alistair Francis
2024-07-18 2:10 ` [PULL 24/30] target/riscv: Start counters from both mhpmcounter and mcountinhibit Alistair Francis
2024-07-18 2:10 ` [PULL 25/30] target/riscv: More accurately model priv mode filtering Alistair Francis
2024-07-18 2:10 ` [PULL 26/30] target/riscv: Do not setup pmu timer if OF is disabled Alistair Francis
2024-07-20 15:19 ` Peter Maydell
2024-07-22 23:33 ` Atish Kumar Patra
2024-07-23 0:43 ` Alistair Francis
2024-07-23 0:49 ` Richard Henderson [this message]
2024-07-24 19:00 ` Daniel Henrique Barboza
2024-07-24 21:30 ` Richard Henderson
2024-07-25 14:05 ` Peter Maydell
2024-07-18 2:10 ` [PULL 27/30] target/riscv: Expose the Smcntrpmf config Alistair Francis
2024-07-18 2:10 ` [PULL 28/30] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR Alistair Francis
2024-07-18 2:10 ` [PULL 29/30] hw/riscv/virt.c: re-insert and deprecate 'riscv, delegate' Alistair Francis
2024-07-18 2:10 ` [PULL 30/30] roms/opensbi: Update to v1.5 Alistair Francis
2024-07-18 21:01 ` [PULL 00/30] riscv-to-apply queue Richard Henderson
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