[PATCH 0/3] target/ppc: Replace target_ulong -> uint64_t for TARGET_PPC64

[PATCH 0/3] target/ppc: Replace target_ulong -> uint64_t for TARGET_PPC64

[Philippe Mathieu-Daudé]

The 'target_ulong' should only be used for fields when have
different size on 32 / 64-bit builds. For fields whicn are
only available on 64-bit builds, directly use the 'uint64_t'
type.

Philippe Mathieu-Daudé (3):
  target/ppc: Explicitly declare CFAR register as 64-bit
  target/ppc: Explicitly declare 'cpu_reserve_val2' register as 64-bit
  target/ppc: Explicitly declare BHRB related register as 64-bit

 target/ppc/cpu.h       | 14 ++++++-------
 target/ppc/machine.c   |  4 ++--
 target/ppc/translate.c | 47 +++++++++++++++++++++---------------------
 3 files changed, 33 insertions(+), 32 deletions(-)

-- 
2.53.0

[PATCH 1/3] target/ppc: Explicitly declare CFAR register as 64-bit

[Philippe Mathieu-Daudé]

The Come-From Address Register (CFAR) register is only available
on 64-bit CPUs, and is 64-bit wide. Prefer the 64-bit APIs over
the 'target-long' one. No logical change intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/cpu.h       |  2 +-
 target/ppc/translate.c | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index aba8109bbba..63c8fa25acc 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1285,7 +1285,7 @@ struct CPUArchState {
     target_ulong ctr;
     uint32_t crf[8];       /* condition register */
 #if defined(TARGET_PPC64)
-    target_ulong cfar;
+    uint64_t cfar;
 #endif
     target_ulong xer;      /* XER (with SO, OV, CA split out) */
     target_ulong so;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f26b0281737..0fc81570a8b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -69,7 +69,7 @@ static TCGv cpu_msr;
 static TCGv cpu_ctr;
 static TCGv cpu_lr;
 #if defined(TARGET_PPC64)
-static TCGv cpu_cfar;
+static TCGv_i64 cpu_cfar;
 #endif
 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
 static TCGv cpu_reserve;
@@ -124,8 +124,8 @@ void ppc_translate_init(void)
                                 offsetof(CPUPPCState, lr), "lr");
 
 #if defined(TARGET_PPC64)
-    cpu_cfar = tcg_global_mem_new(tcg_env,
-                                  offsetof(CPUPPCState, cfar), "cfar");
+    cpu_cfar = tcg_global_mem_new_i64(tcg_env,
+                                    offsetof(CPUPPCState, cfar), "cfar");
 #endif
 
     cpu_xer = tcg_global_mem_new(tcg_env,
@@ -626,12 +626,12 @@ void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
 /* CFAR */
 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
 {
-    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
+    tcg_gen_mov_i64(cpu_gpr[gprn], cpu_cfar);
 }
 
 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
 {
-    tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
+    tcg_gen_mov_i64(cpu_cfar, cpu_gpr[gprn]);
 }
 
 /* Breakpoint */
-- 
2.53.0

[PATCH 2/3] target/ppc: Explicitly declare 'cpu_reserve_val2' register as 64-bit

[Philippe Mathieu-Daudé]

When TARGET_PPC64 is set, the 'target_ulong' type expand to
the 'uint64_t' one. Use the latter which is more explicity,
similarly with the TCG and migration APIs. No logical change
intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/cpu.h       | 2 +-
 target/ppc/machine.c   | 2 +-
 target/ppc/translate.c | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 63c8fa25acc..f4438982928 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1298,7 +1298,7 @@ struct CPUArchState {
     target_ulong reserve_length; /* Reservation larx op size (bytes) */
     target_ulong reserve_val;    /* Reservation value */
 #if defined(TARGET_PPC64)
-    target_ulong reserve_val2;
+    uint64_t reserve_val2;
 #endif
 
     /* These are used in supervisor mode only */
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 49cfdc6d674..b44c3ccf0ae 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -682,7 +682,7 @@ static const VMStateDescription vmstate_reservation = {
         VMSTATE_UINTTL(env.reserve_length, PowerPCCPU),
         VMSTATE_UINTTL(env.reserve_val, PowerPCCPU),
 #if defined(TARGET_PPC64)
-        VMSTATE_UINTTL(env.reserve_val2, PowerPCCPU),
+        VMSTATE_UINT64(env.reserve_val2, PowerPCCPU),
 #endif
         VMSTATE_END_OF_LIST()
     }
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0fc81570a8b..ecf75c1376e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -76,7 +76,7 @@ static TCGv cpu_reserve;
 static TCGv cpu_reserve_length;
 static TCGv cpu_reserve_val;
 #if defined(TARGET_PPC64)
-static TCGv cpu_reserve_val2;
+static TCGv_i64 cpu_reserve_val2;
 #endif
 static TCGv cpu_fpscr;
 static TCGv_i32 cpu_access_type;
@@ -152,7 +152,7 @@ void ppc_translate_init(void)
                                          offsetof(CPUPPCState, reserve_val),
                                          "reserve_val");
 #if defined(TARGET_PPC64)
-    cpu_reserve_val2 = tcg_global_mem_new(tcg_env,
+    cpu_reserve_val2 = tcg_global_mem_new_i64(tcg_env,
                                           offsetof(CPUPPCState, reserve_val2),
                                           "reserve_val2");
 #endif
-- 
2.53.0

[PATCH 3/3] target/ppc: Explicitly declare BHRB related register as 64-bit

[Philippe Mathieu-Daudé]

When TARGET_PPC64 is set, the 'target_ulong' type expand to
the 'uint64_t' one. Use the latter which is more explicity,
similarly with the TCG and migration APIs. No logical change
intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/cpu.h       | 10 +++++-----
 target/ppc/machine.c   |  2 +-
 target/ppc/translate.c | 33 +++++++++++++++++----------------
 3 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f4438982928..2332c509524 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1373,11 +1373,11 @@ struct CPUArchState {
 
 #ifdef TARGET_PPC64
     /* Branch History Rolling Buffer (BHRB) resources */
-    target_ulong bhrb_num_entries;
-    intptr_t     bhrb_base;
-    target_ulong bhrb_filter;
-    target_ulong bhrb_offset;
-    target_ulong bhrb_offset_mask;
+    uint64_t bhrb_num_entries;
+    intptr_t bhrb_base;
+    uint64_t bhrb_filter;
+    uint64_t bhrb_offset;
+    uint64_t bhrb_offset_mask;
     uint64_t bhrb[BHRB_MAX_NUM_ENTRIES];
 #endif
 
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index b44c3ccf0ae..65594f5e1a6 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -723,7 +723,7 @@ static const VMStateDescription vmstate_bhrb = {
     .minimum_version_id = 1,
     .needed = bhrb_needed,
     .fields = (VMStateField[]) {
-        VMSTATE_UINTTL(env.bhrb_offset, PowerPCCPU),
+        VMSTATE_UINT64(env.bhrb_offset, PowerPCCPU),
         VMSTATE_UINT64_ARRAY(env.bhrb, PowerPCCPU, BHRB_MAX_NUM_ENTRIES),
         VMSTATE_END_OF_LIST()
     }
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ecf75c1376e..996e6551436 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3502,7 +3502,8 @@ static void gen_rvwinkle(DisasContext *ctx)
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
-static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, TCGv value)
+static TCGv gen_write_bhrb(TCGv_ptr base, TCGv_i64 offset,
+                           TCGv_i64 mask, TCGv_i64 value)
 {
     TCGv_ptr tmp = tcg_temp_new_ptr();
 
@@ -3513,10 +3514,10 @@ static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, TCGv va
     tcg_gen_st_i64(value, tmp, 0);
 
     /* add 8 to current bhrb_offset */
-    tcg_gen_addi_tl(offset, offset, 8);
+    tcg_gen_addi_i64(offset, offset, 8);
 
     /* apply offset mask */
-    tcg_gen_and_tl(offset, offset, mask);
+    tcg_gen_and_i64(offset, offset, mask);
 
     return offset;
 }
@@ -3529,13 +3530,13 @@ static inline void gen_update_branch_history(DisasContext *ctx,
 {
 #if defined(TARGET_PPC64)
     TCGv_ptr base;
-    TCGv tmp;
-    TCGv offset;
-    TCGv mask;
+    TCGv_i64 tmp;
+    TCGv_i64 offset;
+    TCGv_i64 mask;
     TCGLabel *no_update;
 
     if (ctx->has_cfar) {
-        tcg_gen_movi_tl(cpu_cfar, nip);
+        tcg_gen_movi_i64(cpu_cfar, nip);
     }
 
     if (!ctx->has_bhrb ||
@@ -3548,22 +3549,22 @@ static inline void gen_update_branch_history(DisasContext *ctx,
     no_update = gen_new_label();
 
     /* check for bhrb filtering */
-    tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUPPCState, bhrb_filter));
-    tcg_gen_andi_tl(tmp, tmp, inst_type);
-    tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, 0, no_update);
+    tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUPPCState, bhrb_filter));
+    tcg_gen_andi_i64(tmp, tmp, inst_type);
+    tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, no_update);
 
     base = tcg_temp_new_ptr();
-    offset = tcg_temp_new();
-    mask = tcg_temp_new();
+    offset = tcg_temp_new_i64();
+    mask = tcg_temp_new_i64();
 
     /* load bhrb base address */
     tcg_gen_ld_ptr(base, tcg_env, offsetof(CPUPPCState, bhrb_base));
 
     /* load current bhrb_offset */
-    tcg_gen_ld_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
+    tcg_gen_ld_i64(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
 
     /* load a BHRB offset mask */
-    tcg_gen_ld_tl(mask, tcg_env, offsetof(CPUPPCState, bhrb_offset_mask));
+    tcg_gen_ld_i64(mask, tcg_env, offsetof(CPUPPCState, bhrb_offset_mask));
 
     offset = gen_write_bhrb(base, offset, mask, tcg_constant_i64(nip));
 
@@ -3571,13 +3572,13 @@ static inline void gen_update_branch_history(DisasContext *ctx,
     if (inst_type & BHRB_TYPE_XL_FORM) {
 
         /* Set the 'T' bit for target entries */
-        tcg_gen_ori_tl(tmp, target, 0x2);
+        tcg_gen_ori_i64(tmp, target, 0x2);
 
         offset = gen_write_bhrb(base, offset, mask, tmp);
     }
 
     /* save updated bhrb_offset for next time */
-    tcg_gen_st_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
+    tcg_gen_st_i64(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
 
     gen_set_label(no_update);
 #endif
-- 
2.53.0

Re: [PATCH 1/3] target/ppc: Explicitly declare CFAR register as 64-bit

[Anton Johansson via qemu development]

On 15/03/26, Philippe Mathieu-Daudé wrote:
> The Come-From Address Register (CFAR) register is only available
> on 64-bit CPUs, and is 64-bit wide. Prefer the 64-bit APIs over
> the 'target-long' one. No logical change intended.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/ppc/cpu.h       |  2 +-
>  target/ppc/translate.c | 10 +++++-----
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index aba8109bbba..63c8fa25acc 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1285,7 +1285,7 @@ struct CPUArchState {
>      target_ulong ctr;
>      uint32_t crf[8];       /* condition register */
>  #if defined(TARGET_PPC64)
> -    target_ulong cfar;
> +    uint64_t cfar;
>  #endif
>      target_ulong xer;      /* XER (with SO, OV, CA split out) */
>      target_ulong so;
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index f26b0281737..0fc81570a8b 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -69,7 +69,7 @@ static TCGv cpu_msr;
>  static TCGv cpu_ctr;
>  static TCGv cpu_lr;
>  #if defined(TARGET_PPC64)
> -static TCGv cpu_cfar;
> +static TCGv_i64 cpu_cfar;
>  #endif
>  static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
>  static TCGv cpu_reserve;
> @@ -124,8 +124,8 @@ void ppc_translate_init(void)
>                                  offsetof(CPUPPCState, lr), "lr");
>  
>  #if defined(TARGET_PPC64)
> -    cpu_cfar = tcg_global_mem_new(tcg_env,
> -                                  offsetof(CPUPPCState, cfar), "cfar");
> +    cpu_cfar = tcg_global_mem_new_i64(tcg_env,
> +                                    offsetof(CPUPPCState, cfar), "cfar");
>  #endif
>  
>      cpu_xer = tcg_global_mem_new(tcg_env,
> @@ -626,12 +626,12 @@ void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
>  /* CFAR */
>  void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
>  {
> -    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
> +    tcg_gen_mov_i64(cpu_gpr[gprn], cpu_cfar);
>  }
>  
>  void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
>  {
> -    tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
> +    tcg_gen_mov_i64(cpu_cfar, cpu_gpr[gprn]);
>  }
>  
>  /* Breakpoint */
> -- 
> 2.53.0
> 
> 

Change of 

  - tcg_gen_movi_tl(cpu_cfar, nip);
  + tcg_gen_movi_i64(cpu_cfar, nip);

in gen_update_branch_history() should be in this patch and not the last
one, I'm guessing you just missed it when splitting.

Other than that

Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH 2/3] target/ppc: Explicitly declare 'cpu_reserve_val2' register as 64-bit

[Anton Johansson via qemu development]

On 15/03/26, Philippe Mathieu-Daudé wrote:
> When TARGET_PPC64 is set, the 'target_ulong' type expand to
> the 'uint64_t' one. Use the latter which is more explicity,
> similarly with the TCG and migration APIs. No logical change
> intended.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/ppc/cpu.h       | 2 +-
>  target/ppc/machine.c   | 2 +-
>  target/ppc/translate.c | 4 ++--
>  3 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 63c8fa25acc..f4438982928 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1298,7 +1298,7 @@ struct CPUArchState {
>      target_ulong reserve_length; /* Reservation larx op size (bytes) */
>      target_ulong reserve_val;    /* Reservation value */
>  #if defined(TARGET_PPC64)
> -    target_ulong reserve_val2;
> +    uint64_t reserve_val2;
>  #endif
>  
>      /* These are used in supervisor mode only */
> diff --git a/target/ppc/machine.c b/target/ppc/machine.c
> index 49cfdc6d674..b44c3ccf0ae 100644
> --- a/target/ppc/machine.c
> +++ b/target/ppc/machine.c
> @@ -682,7 +682,7 @@ static const VMStateDescription vmstate_reservation = {
>          VMSTATE_UINTTL(env.reserve_length, PowerPCCPU),
>          VMSTATE_UINTTL(env.reserve_val, PowerPCCPU),
>  #if defined(TARGET_PPC64)
> -        VMSTATE_UINTTL(env.reserve_val2, PowerPCCPU),
> +        VMSTATE_UINT64(env.reserve_val2, PowerPCCPU),
>  #endif
>          VMSTATE_END_OF_LIST()
>      }
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 0fc81570a8b..ecf75c1376e 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -76,7 +76,7 @@ static TCGv cpu_reserve;
>  static TCGv cpu_reserve_length;
>  static TCGv cpu_reserve_val;
>  #if defined(TARGET_PPC64)
> -static TCGv cpu_reserve_val2;
> +static TCGv_i64 cpu_reserve_val2;
>  #endif
>  static TCGv cpu_fpscr;
>  static TCGv_i32 cpu_access_type;
> @@ -152,7 +152,7 @@ void ppc_translate_init(void)
>                                           offsetof(CPUPPCState, reserve_val),
>                                           "reserve_val");
>  #if defined(TARGET_PPC64)
> -    cpu_reserve_val2 = tcg_global_mem_new(tcg_env,
> +    cpu_reserve_val2 = tcg_global_mem_new_i64(tcg_env,
>                                            offsetof(CPUPPCState, reserve_val2),
>                                            "reserve_val2");
>  #endif
> -- 
> 2.53.0
> 
> 

There's a use left in gen_stqcx_()

    tcg_gen_xor_tl(t1, t1, cpu_reserve_val2);

since the entire function is guarded by TARGET_PPC64 we can just use
tcg_gen_*_i64() throughout?

Otherwise,

Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH 3/3] target/ppc: Explicitly declare BHRB related register as 64-bit

[Anton Johansson via qemu development]

On 15/03/26, Philippe Mathieu-Daudé wrote:
> When TARGET_PPC64 is set, the 'target_ulong' type expand to
> the 'uint64_t' one. Use the latter which is more explicity,
> similarly with the TCG and migration APIs. No logical change
> intended.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/ppc/cpu.h       | 10 +++++-----
>  target/ppc/machine.c   |  2 +-
>  target/ppc/translate.c | 33 +++++++++++++++++----------------
>  3 files changed, 23 insertions(+), 22 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index f4438982928..2332c509524 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1373,11 +1373,11 @@ struct CPUArchState {
>  
>  #ifdef TARGET_PPC64
>      /* Branch History Rolling Buffer (BHRB) resources */
> -    target_ulong bhrb_num_entries;
> -    intptr_t     bhrb_base;
> -    target_ulong bhrb_filter;
> -    target_ulong bhrb_offset;
> -    target_ulong bhrb_offset_mask;
> +    uint64_t bhrb_num_entries;
> +    intptr_t bhrb_base;
> +    uint64_t bhrb_filter;
> +    uint64_t bhrb_offset;
> +    uint64_t bhrb_offset_mask;
>      uint64_t bhrb[BHRB_MAX_NUM_ENTRIES];
>  #endif
>  
> diff --git a/target/ppc/machine.c b/target/ppc/machine.c
> index b44c3ccf0ae..65594f5e1a6 100644
> --- a/target/ppc/machine.c
> +++ b/target/ppc/machine.c
> @@ -723,7 +723,7 @@ static const VMStateDescription vmstate_bhrb = {
>      .minimum_version_id = 1,
>      .needed = bhrb_needed,
>      .fields = (VMStateField[]) {
> -        VMSTATE_UINTTL(env.bhrb_offset, PowerPCCPU),
> +        VMSTATE_UINT64(env.bhrb_offset, PowerPCCPU),
>          VMSTATE_UINT64_ARRAY(env.bhrb, PowerPCCPU, BHRB_MAX_NUM_ENTRIES),
>          VMSTATE_END_OF_LIST()
>      }
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index ecf75c1376e..996e6551436 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -3502,7 +3502,8 @@ static void gen_rvwinkle(DisasContext *ctx)
>  #endif /* defined(CONFIG_USER_ONLY) */
>  }
>  
> -static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, TCGv value)
> +static TCGv gen_write_bhrb(TCGv_ptr base, TCGv_i64 offset,
> +                           TCGv_i64 mask, TCGv_i64 value)
>  {
>      TCGv_ptr tmp = tcg_temp_new_ptr();
>  
> @@ -3513,10 +3514,10 @@ static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, TCGv va
>      tcg_gen_st_i64(value, tmp, 0);
>  
>      /* add 8 to current bhrb_offset */
> -    tcg_gen_addi_tl(offset, offset, 8);
> +    tcg_gen_addi_i64(offset, offset, 8);
>  
>      /* apply offset mask */
> -    tcg_gen_and_tl(offset, offset, mask);
> +    tcg_gen_and_i64(offset, offset, mask);
>  
>      return offset;
>  }
> @@ -3529,13 +3530,13 @@ static inline void gen_update_branch_history(DisasContext *ctx,
>  {
>  #if defined(TARGET_PPC64)
>      TCGv_ptr base;
> -    TCGv tmp;
> -    TCGv offset;
> -    TCGv mask;
> +    TCGv_i64 tmp;
> +    TCGv_i64 offset;
> +    TCGv_i64 mask;
>      TCGLabel *no_update;
>  
>      if (ctx->has_cfar) {
> -        tcg_gen_movi_tl(cpu_cfar, nip);
> +        tcg_gen_movi_i64(cpu_cfar, nip);
>      }

Move to cpu_cfar patch!:)


>  
>      if (!ctx->has_bhrb ||
> @@ -3548,22 +3549,22 @@ static inline void gen_update_branch_history(DisasContext *ctx,
>      no_update = gen_new_label();
>  
>      /* check for bhrb filtering */
> -    tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUPPCState, bhrb_filter));
> -    tcg_gen_andi_tl(tmp, tmp, inst_type);
> -    tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, 0, no_update);
> +    tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUPPCState, bhrb_filter));
> +    tcg_gen_andi_i64(tmp, tmp, inst_type);
> +    tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, no_update);
>  
>      base = tcg_temp_new_ptr();
> -    offset = tcg_temp_new();
> -    mask = tcg_temp_new();
> +    offset = tcg_temp_new_i64();
> +    mask = tcg_temp_new_i64();
>  
>      /* load bhrb base address */
>      tcg_gen_ld_ptr(base, tcg_env, offsetof(CPUPPCState, bhrb_base));
>  
>      /* load current bhrb_offset */
> -    tcg_gen_ld_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
> +    tcg_gen_ld_i64(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
>  
>      /* load a BHRB offset mask */
> -    tcg_gen_ld_tl(mask, tcg_env, offsetof(CPUPPCState, bhrb_offset_mask));
> +    tcg_gen_ld_i64(mask, tcg_env, offsetof(CPUPPCState, bhrb_offset_mask));
>  
>      offset = gen_write_bhrb(base, offset, mask, tcg_constant_i64(nip));
>  
> @@ -3571,13 +3572,13 @@ static inline void gen_update_branch_history(DisasContext *ctx,
>      if (inst_type & BHRB_TYPE_XL_FORM) {
>  
>          /* Set the 'T' bit for target entries */
> -        tcg_gen_ori_tl(tmp, target, 0x2);
> +        tcg_gen_ori_i64(tmp, target, 0x2);
>  
>          offset = gen_write_bhrb(base, offset, mask, tmp);
>      }
>  
>      /* save updated bhrb_offset for next time */
> -    tcg_gen_st_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
> +    tcg_gen_st_i64(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
>  
>      gen_set_label(no_update);
>  #endif
> -- 
> 2.53.0
> 
> 

Otherwise,

Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH 0/3] target/ppc: Replace target_ulong -> uint64_t for TARGET_PPC64

[Anton Johansson via qemu development]

On 15/03/26, Philippe Mathieu-Daudé wrote:
> The 'target_ulong' should only be used for fields when have
> different size on 32 / 64-bit builds. For fields whicn are

                                                   ^- spelling:)


> only available on 64-bit builds, directly use the 'uint64_t'
> type.
> 
> Philippe Mathieu-Daudé (3):
>   target/ppc: Explicitly declare CFAR register as 64-bit
>   target/ppc: Explicitly declare 'cpu_reserve_val2' register as 64-bit
>   target/ppc: Explicitly declare BHRB related register as 64-bit
> 
>  target/ppc/cpu.h       | 14 ++++++-------
>  target/ppc/machine.c   |  4 ++--
>  target/ppc/translate.c | 47 +++++++++++++++++++++---------------------
>  3 files changed, 33 insertions(+), 32 deletions(-)
> 
> -- 
> 2.53.0
> 
> 

Re: [PATCH 3/3] target/ppc: Explicitly declare BHRB related register as 64-bit

[Miles Glenn]

Reviewed-by: Glenn Miles <milesg@linux.ibm.com>

Thanks,

Glenn

On Sun, 2026-03-15 at 18:08 +0100, Philippe Mathieu-Daudé wrote:
> When TARGET_PPC64 is set, the 'target_ulong' type expand to
> the 'uint64_t' one. Use the latter which is more explicity,
> similarly with the TCG and migration APIs. No logical change
> intended.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/ppc/cpu.h       | 10 +++++-----
>  target/ppc/machine.c   |  2 +-
>  target/ppc/translate.c | 33 +++++++++++++++++----------------
>  3 files changed, 23 insertions(+), 22 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index f4438982928..2332c509524 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1373,11 +1373,11 @@ struct CPUArchState {
>  
>  #ifdef TARGET_PPC64
>      /* Branch History Rolling Buffer (BHRB) resources */
> -    target_ulong bhrb_num_entries;
> -    intptr_t     bhrb_base;
> -    target_ulong bhrb_filter;
> -    target_ulong bhrb_offset;
> -    target_ulong bhrb_offset_mask;
> +    uint64_t bhrb_num_entries;
> +    intptr_t bhrb_base;
> +    uint64_t bhrb_filter;
> +    uint64_t bhrb_offset;
> +    uint64_t bhrb_offset_mask;
>      uint64_t bhrb[BHRB_MAX_NUM_ENTRIES];
>  #endif
>  
> diff --git a/target/ppc/machine.c b/target/ppc/machine.c
> index b44c3ccf0ae..65594f5e1a6 100644
> --- a/target/ppc/machine.c
> +++ b/target/ppc/machine.c
> @@ -723,7 +723,7 @@ static const VMStateDescription vmstate_bhrb = {
>      .minimum_version_id = 1,
>      .needed = bhrb_needed,
>      .fields = (VMStateField[]) {
> -        VMSTATE_UINTTL(env.bhrb_offset, PowerPCCPU),
> +        VMSTATE_UINT64(env.bhrb_offset, PowerPCCPU),
>          VMSTATE_UINT64_ARRAY(env.bhrb, PowerPCCPU, BHRB_MAX_NUM_ENTRIES),
>          VMSTATE_END_OF_LIST()
>      }
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index ecf75c1376e..996e6551436 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -3502,7 +3502,8 @@ static void gen_rvwinkle(DisasContext *ctx)
>  #endif /* defined(CONFIG_USER_ONLY) */
>  }
>  
> -static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, TCGv value)
> +static TCGv gen_write_bhrb(TCGv_ptr base, TCGv_i64 offset,
> +                           TCGv_i64 mask, TCGv_i64 value)
>  {
>      TCGv_ptr tmp = tcg_temp_new_ptr();
>  
> @@ -3513,10 +3514,10 @@ static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, TCGv va
>      tcg_gen_st_i64(value, tmp, 0);
>  
>      /* add 8 to current bhrb_offset */
> -    tcg_gen_addi_tl(offset, offset, 8);
> +    tcg_gen_addi_i64(offset, offset, 8);
>  
>      /* apply offset mask */
> -    tcg_gen_and_tl(offset, offset, mask);
> +    tcg_gen_and_i64(offset, offset, mask);
>  
>      return offset;
>  }
> @@ -3529,13 +3530,13 @@ static inline void gen_update_branch_history(DisasContext *ctx,
>  {
>  #if defined(TARGET_PPC64)
>      TCGv_ptr base;
> -    TCGv tmp;
> -    TCGv offset;
> -    TCGv mask;
> +    TCGv_i64 tmp;
> +    TCGv_i64 offset;
> +    TCGv_i64 mask;
>      TCGLabel *no_update;
>  
>      if (ctx->has_cfar) {
> -        tcg_gen_movi_tl(cpu_cfar, nip);
> +        tcg_gen_movi_i64(cpu_cfar, nip);
>      }
>  
>      if (!ctx->has_bhrb ||
> @@ -3548,22 +3549,22 @@ static inline void gen_update_branch_history(DisasContext *ctx,
>      no_update = gen_new_label();
>  
>      /* check for bhrb filtering */
> -    tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUPPCState, bhrb_filter));
> -    tcg_gen_andi_tl(tmp, tmp, inst_type);
> -    tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, 0, no_update);
> +    tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUPPCState, bhrb_filter));
> +    tcg_gen_andi_i64(tmp, tmp, inst_type);
> +    tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, no_update);
>  
>      base = tcg_temp_new_ptr();
> -    offset = tcg_temp_new();
> -    mask = tcg_temp_new();
> +    offset = tcg_temp_new_i64();
> +    mask = tcg_temp_new_i64();
>  
>      /* load bhrb base address */
>      tcg_gen_ld_ptr(base, tcg_env, offsetof(CPUPPCState, bhrb_base));
>  
>      /* load current bhrb_offset */
> -    tcg_gen_ld_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
> +    tcg_gen_ld_i64(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
>  
>      /* load a BHRB offset mask */
> -    tcg_gen_ld_tl(mask, tcg_env, offsetof(CPUPPCState, bhrb_offset_mask));
> +    tcg_gen_ld_i64(mask, tcg_env, offsetof(CPUPPCState, bhrb_offset_mask));
>  
>      offset = gen_write_bhrb(base, offset, mask, tcg_constant_i64(nip));
>  
> @@ -3571,13 +3572,13 @@ static inline void gen_update_branch_history(DisasContext *ctx,
>      if (inst_type & BHRB_TYPE_XL_FORM) {
>  
>          /* Set the 'T' bit for target entries */
> -        tcg_gen_ori_tl(tmp, target, 0x2);
> +        tcg_gen_ori_i64(tmp, target, 0x2);
>  
>          offset = gen_write_bhrb(base, offset, mask, tmp);
>      }
>  
>      /* save updated bhrb_offset for next time */
> -    tcg_gen_st_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
> +    tcg_gen_st_i64(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
>  
>      gen_set_label(no_update);
>  #endif

Re: [PATCH 2/3] target/ppc: Explicitly declare 'cpu_reserve_val2' register as 64-bit

[Miles Glenn]

Reviewed-by: Glenn Miles <milesg@linux.ibm.com>

Thanks,

Glenn

On Sun, 2026-03-15 at 18:08 +0100, Philippe Mathieu-Daudé wrote:
> When TARGET_PPC64 is set, the 'target_ulong' type expand to
> the 'uint64_t' one. Use the latter which is more explicity,
> similarly with the TCG and migration APIs. No logical change
> intended.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/ppc/cpu.h       | 2 +-
>  target/ppc/machine.c   | 2 +-
>  target/ppc/translate.c | 4 ++--
>  3 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 63c8fa25acc..f4438982928 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1298,7 +1298,7 @@ struct CPUArchState {
>      target_ulong reserve_length; /* Reservation larx op size (bytes) */
>      target_ulong reserve_val;    /* Reservation value */
>  #if defined(TARGET_PPC64)
> -    target_ulong reserve_val2;
> +    uint64_t reserve_val2;
>  #endif
>  
>      /* These are used in supervisor mode only */
> diff --git a/target/ppc/machine.c b/target/ppc/machine.c
> index 49cfdc6d674..b44c3ccf0ae 100644
> --- a/target/ppc/machine.c
> +++ b/target/ppc/machine.c
> @@ -682,7 +682,7 @@ static const VMStateDescription vmstate_reservation = {
>          VMSTATE_UINTTL(env.reserve_length, PowerPCCPU),
>          VMSTATE_UINTTL(env.reserve_val, PowerPCCPU),
>  #if defined(TARGET_PPC64)
> -        VMSTATE_UINTTL(env.reserve_val2, PowerPCCPU),
> +        VMSTATE_UINT64(env.reserve_val2, PowerPCCPU),
>  #endif
>          VMSTATE_END_OF_LIST()
>      }
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 0fc81570a8b..ecf75c1376e 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -76,7 +76,7 @@ static TCGv cpu_reserve;
>  static TCGv cpu_reserve_length;
>  static TCGv cpu_reserve_val;
>  #if defined(TARGET_PPC64)
> -static TCGv cpu_reserve_val2;
> +static TCGv_i64 cpu_reserve_val2;
>  #endif
>  static TCGv cpu_fpscr;
>  static TCGv_i32 cpu_access_type;
> @@ -152,7 +152,7 @@ void ppc_translate_init(void)
>                                           offsetof(CPUPPCState, reserve_val),
>                                           "reserve_val");
>  #if defined(TARGET_PPC64)
> -    cpu_reserve_val2 = tcg_global_mem_new(tcg_env,
> +    cpu_reserve_val2 = tcg_global_mem_new_i64(tcg_env,
>                                            offsetof(CPUPPCState, reserve_val2),
>                                            "reserve_val2");
>  #endif

Re: [PATCH 1/3] target/ppc: Explicitly declare CFAR register as 64-bit

[Miles Glenn]

Reviewed-by: Glenn Miles <milesg@linux.ibm.com>

Thanks,

Glenn

On Sun, 2026-03-15 at 18:08 +0100, Philippe Mathieu-Daudé wrote:
> The Come-From Address Register (CFAR) register is only available
> on 64-bit CPUs, and is 64-bit wide. Prefer the 64-bit APIs over
> the 'target-long' one. No logical change intended.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/ppc/cpu.h       |  2 +-
>  target/ppc/translate.c | 10 +++++-----
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index aba8109bbba..63c8fa25acc 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1285,7 +1285,7 @@ struct CPUArchState {
>      target_ulong ctr;
>      uint32_t crf[8];       /* condition register */
>  #if defined(TARGET_PPC64)
> -    target_ulong cfar;
> +    uint64_t cfar;
>  #endif
>      target_ulong xer;      /* XER (with SO, OV, CA split out) */
>      target_ulong so;
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index f26b0281737..0fc81570a8b 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -69,7 +69,7 @@ static TCGv cpu_msr;
>  static TCGv cpu_ctr;
>  static TCGv cpu_lr;
>  #if defined(TARGET_PPC64)
> -static TCGv cpu_cfar;
> +static TCGv_i64 cpu_cfar;
>  #endif
>  static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
>  static TCGv cpu_reserve;
> @@ -124,8 +124,8 @@ void ppc_translate_init(void)
>                                  offsetof(CPUPPCState, lr), "lr");
>  
>  #if defined(TARGET_PPC64)
> -    cpu_cfar = tcg_global_mem_new(tcg_env,
> -                                  offsetof(CPUPPCState, cfar), "cfar");
> +    cpu_cfar = tcg_global_mem_new_i64(tcg_env,
> +                                    offsetof(CPUPPCState, cfar), "cfar");
>  #endif
>  
>      cpu_xer = tcg_global_mem_new(tcg_env,
> @@ -626,12 +626,12 @@ void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
>  /* CFAR */
>  void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
>  {
> -    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
> +    tcg_gen_mov_i64(cpu_gpr[gprn], cpu_cfar);
>  }
>  
>  void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
>  {
> -    tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
> +    tcg_gen_mov_i64(cpu_cfar, cpu_gpr[gprn]);
>  }
>  
>  /* Breakpoint */

Re: [PATCH 3/3] target/ppc: Explicitly declare BHRB related register as 64-bit

[Chinmay Rath]

On 3/15/26 22:38, Philippe Mathieu-Daudé wrote:
> When TARGET_PPC64 is set, the 'target_ulong' type expand to
> the 'uint64_t' one. Use the latter which is more explicity,
> similarly with the TCG and migration APIs. No logical change
> intended.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/ppc/cpu.h       | 10 +++++-----
>   target/ppc/machine.c   |  2 +-
>   target/ppc/translate.c | 33 +++++++++++++++++----------------
>   3 files changed, 23 insertions(+), 22 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index f4438982928..2332c509524 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1373,11 +1373,11 @@ struct CPUArchState {
>   
>   #ifdef TARGET_PPC64
>       /* Branch History Rolling Buffer (BHRB) resources */
> -    target_ulong bhrb_num_entries;
> -    intptr_t     bhrb_base;
> -    target_ulong bhrb_filter;
> -    target_ulong bhrb_offset;
> -    target_ulong bhrb_offset_mask;
> +    uint64_t bhrb_num_entries;
> +    intptr_t bhrb_base;
> +    uint64_t bhrb_filter;
> +    uint64_t bhrb_offset;
> +    uint64_t bhrb_offset_mask;
>       uint64_t bhrb[BHRB_MAX_NUM_ENTRIES];
>   #endif
>   
> diff --git a/target/ppc/machine.c b/target/ppc/machine.c
> index b44c3ccf0ae..65594f5e1a6 100644
> --- a/target/ppc/machine.c
> +++ b/target/ppc/machine.c
> @@ -723,7 +723,7 @@ static const VMStateDescription vmstate_bhrb = {
>       .minimum_version_id = 1,
>       .needed = bhrb_needed,
>       .fields = (VMStateField[]) {
> -        VMSTATE_UINTTL(env.bhrb_offset, PowerPCCPU),
> +        VMSTATE_UINT64(env.bhrb_offset, PowerPCCPU),
>           VMSTATE_UINT64_ARRAY(env.bhrb, PowerPCCPU, BHRB_MAX_NUM_ENTRIES),
>           VMSTATE_END_OF_LIST()
>       }
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index ecf75c1376e..996e6551436 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -3502,7 +3502,8 @@ static void gen_rvwinkle(DisasContext *ctx)
>   #endif /* defined(CONFIG_USER_ONLY) */
>   }
>   
> -static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, TCGv value)
> +static TCGv gen_write_bhrb(TCGv_ptr base, TCGv_i64 offset,
> +                           TCGv_i64 mask, TCGv_i64 value
Hey was it intentional to leave out 'inline' here ?

Regards,
Chinmay
>   {
>       TCGv_ptr tmp = tcg_temp_new_ptr();
>   
> @@ -3513,10 +3514,10 @@ static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, TCGv va
>       tcg_gen_st_i64(value, tmp, 0);
>   
>       /* add 8 to current bhrb_offset */
> -    tcg_gen_addi_tl(offset, offset, 8);
> +    tcg_gen_addi_i64(offset, offset, 8);
>   
>       /* apply offset mask */
> -    tcg_gen_and_tl(offset, offset, mask);
> +    tcg_gen_and_i64(offset, offset, mask);
>   
>       return offset;
>   }
> @@ -3529,13 +3530,13 @@ static inline void gen_update_branch_history(DisasContext *ctx,
>   {
>   #if defined(TARGET_PPC64)
>       TCGv_ptr base;
> -    TCGv tmp;
> -    TCGv offset;
> -    TCGv mask;
> +    TCGv_i64 tmp;
> +    TCGv_i64 offset;
> +    TCGv_i64 mask;
>       TCGLabel *no_update;
>   
>       if (ctx->has_cfar) {
> -        tcg_gen_movi_tl(cpu_cfar, nip);
> +        tcg_gen_movi_i64(cpu_cfar, nip);
>       }
>   
>       if (!ctx->has_bhrb ||
> @@ -3548,22 +3549,22 @@ static inline void gen_update_branch_history(DisasContext *ctx,
>       no_update = gen_new_label();
>   
>       /* check for bhrb filtering */
> -    tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUPPCState, bhrb_filter));
> -    tcg_gen_andi_tl(tmp, tmp, inst_type);
> -    tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, 0, no_update);
> +    tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUPPCState, bhrb_filter));
> +    tcg_gen_andi_i64(tmp, tmp, inst_type);
> +    tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, no_update);
>   
>       base = tcg_temp_new_ptr();
> -    offset = tcg_temp_new();
> -    mask = tcg_temp_new();
> +    offset = tcg_temp_new_i64();
> +    mask = tcg_temp_new_i64();
>   
>       /* load bhrb base address */
>       tcg_gen_ld_ptr(base, tcg_env, offsetof(CPUPPCState, bhrb_base));
>   
>       /* load current bhrb_offset */
> -    tcg_gen_ld_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
> +    tcg_gen_ld_i64(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
>   
>       /* load a BHRB offset mask */
> -    tcg_gen_ld_tl(mask, tcg_env, offsetof(CPUPPCState, bhrb_offset_mask));
> +    tcg_gen_ld_i64(mask, tcg_env, offsetof(CPUPPCState, bhrb_offset_mask));
>   
>       offset = gen_write_bhrb(base, offset, mask, tcg_constant_i64(nip));
>   
> @@ -3571,13 +3572,13 @@ static inline void gen_update_branch_history(DisasContext *ctx,
>       if (inst_type & BHRB_TYPE_XL_FORM) {
>   
>           /* Set the 'T' bit for target entries */
> -        tcg_gen_ori_tl(tmp, target, 0x2);
> +        tcg_gen_ori_i64(tmp, target, 0x2);
>   
>           offset = gen_write_bhrb(base, offset, mask, tmp);
>       }
>   
>       /* save updated bhrb_offset for next time */
> -    tcg_gen_st_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
> +    tcg_gen_st_i64(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset));
>   
>       gen_set_label(no_update);
>   #endif