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[176.184.8.67]) by smtp.gmail.com with ESMTPSA id q9-20020aa7cc09000000b00558a3e892b3sm16257147edt.41.2024.01.24.04.37.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 24 Jan 2024 04:37:44 -0800 (PST) Message-ID: Date: Wed, 24 Jan 2024 13:37:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/riscv/cpu.h: mcountinhibit, mcounteren and scounteren always 32-bit Content-Language: en-US To: Vadim Shakirov , "open list:All patches CC here" Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org References: <20240124120658.695350-1-vadim.shakirov@syntacore.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240124120658.695350-1-vadim.shakirov@syntacore.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=philmd@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Vadim, On 24/1/24 13:06, Vadim Shakirov wrote: > mcountinhibit, mcounteren and scounteren must always be 32-bit by > privileged spec > > Signed-off-by: Vadim Shakirov > --- > target/riscv/cpu.h | 6 +++--- > target/riscv/machine.c | 6 +++--- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 5b0824ef8f..3cf059199c 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -317,10 +317,10 @@ struct CPUArchState { > */ > bool two_stage_indirect_lookup; > > - target_ulong scounteren; > - target_ulong mcounteren; > + uint32_t scounteren; > + uint32_t mcounteren; > > - target_ulong mcountinhibit; > + uint32_t mcountinhibit; > > /* PMU counter state */ > PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index fdde243e04..daab121799 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -398,9 +398,9 @@ const VMStateDescription vmstate_riscv_cpu = { > VMSTATE_UINTTL(env.mtval, RISCVCPU), > VMSTATE_UINTTL(env.miselect, RISCVCPU), > VMSTATE_UINTTL(env.siselect, RISCVCPU), > - VMSTATE_UINTTL(env.scounteren, RISCVCPU), > - VMSTATE_UINTTL(env.mcounteren, RISCVCPU), > - VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), > + VMSTATE_UINT32(env.scounteren, RISCVCPU), > + VMSTATE_UINT32(env.mcounteren, RISCVCPU), > + VMSTATE_UINT32(env.mcountinhibit, RISCVCPU), When changing a migrated field size, you need to bump the version_id, see https://www.qemu.org/docs/master/devel/migration/main.html#versions. Regards, Phil.