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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-451f99196efsm27015635e9.28.2025.06.05.07.47.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Jun 2025 07:47:07 -0700 (PDT) Message-ID: Date: Thu, 5 Jun 2025 16:47:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] hw/arm/smmuv3: Fix incorrect reserved mask for SMMU CR0 register Content-Language: en-US To: taotang2025@gmail.com, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org References: <20250605022640.598308-1-taotang2025@gmail.com> From: Eric Auger In-Reply-To: <20250605022640.598308-1-taotang2025@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.132, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, On 6/5/25 4:26 AM, taotang2025@gmail.com wrote: > From: Tao Tang > > The current definition of the SMMU_CR0_RESERVED mask is incorrect. > It mistakenly treats bit 10 (DPT_WALK_EN) as a reserved bit while > treating bit 9 (RES0) as an implemented bit. > > According to the SMMU architecture specification, the layout for CR0 is: > | 31:11| RES0 | > | 10 | DPT_WALK_EN | > | 9 | RES0 | > | 8:6 | VMW | > | 5 | RES0 | > | 4 | ATSCHK | > | 3 | CMDQEN | > | 2 | EVENTQEN | > | 1 | PRIQEN | > | 0 | SMMUEN | > > Signed-off-by: Tao Tang Reviewed-by: Eric Auger Thanks! Eric > --- > hw/arm/smmuv3-internal.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index b6b7399347..42ac77e654 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -120,7 +120,7 @@ REG32(CR0, 0x20) > FIELD(CR0, EVENTQEN, 2, 1) > FIELD(CR0, CMDQEN, 3, 1) > > -#define SMMU_CR0_RESERVED 0xFFFFFC20 > +#define SMMU_CR0_RESERVED 0xFFFFFA20 > > REG32(CR0ACK, 0x24) > REG32(CR1, 0x28)