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From: Yi Liu <yi.l.liu@intel.com>
To: Zhenzhong Duan <zhenzhong.duan@intel.com>, <qemu-devel@nongnu.org>
Cc: <mst@redhat.com>, <jasowang@redhat.com>,
	<clement.mathieu--drif@eviden.com>, <chao.p.peng@intel.com>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	Eduardo Habkost <eduardo@habkost.net>
Subject: Re: [PATCH 3/3] intel_iommu: Add missed reserved bit check for IEC descriptor
Date: Tue, 5 Nov 2024 14:56:36 +0800	[thread overview]
Message-ID: <ac55daf3-c8ab-475a-bed3-2e3e3e8fb661@intel.com> (raw)
In-Reply-To: <20241104125536.1236118-4-zhenzhong.duan@intel.com>

On 2024/11/4 20:55, Zhenzhong Duan wrote:
> IEC descriptor is 128-bit invalidation descriptor, must be padded with
> 128-bits of 0s in the upper bytes to create a 256-bit descriptor when
> the invalidation queue is configured for 256-bit descriptors (IQA_REG.DW=1).
> 
> Fixes: 02a2cbc872df ("x86-iommu: introduce IEC notifiers")
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> ---
>   hw/i386/intel_iommu_internal.h | 3 +++
>   hw/i386/intel_iommu.c          | 8 ++++++++
>   2 files changed, 11 insertions(+)

It might be updated if patch 02 of this series has been respined. But this
patch is already in good shape.

Reviewed-by: Yi Liu <yi.l.liu@intel.com>

> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> index 75ccd501b0..4323fc5d6d 100644
> --- a/hw/i386/intel_iommu_internal.h
> +++ b/hw/i386/intel_iommu_internal.h
> @@ -410,6 +410,9 @@ typedef union VTDInvDesc VTDInvDesc;
>   #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI 0xffeULL
>   #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0f1f0
>   
> +/* Masks for Interrupt Entry Invalidate Descriptor */
> +#define VTD_INV_DESC_IEC_RSVD           0xffff000007fff1e0ULL
> +
>   /* Rsvd field masks for spte */
>   #define VTD_SPTE_SNP 0x800ULL
>   
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 2fc3866433..4c0d1d7d47 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -2692,6 +2692,14 @@ static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
>   static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
>                                        VTDInvDesc *inv_desc)
>   {
> +    uint64_t mask[4] = {VTD_INV_DESC_IEC_RSVD, VTD_INV_DESC_ALL_ONE,
> +                        VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE};
> +
> +    if (!vtd_inv_desc_reserved_check(s, inv_desc, mask, false,
> +                                     __func__, "iec inv")) {
> +        return false;
> +    }
> +
>       trace_vtd_inv_desc_iec(inv_desc->iec.granularity,
>                              inv_desc->iec.index,
>                              inv_desc->iec.index_mask);

-- 
Regards,
Yi Liu


      parent reply	other threads:[~2024-11-05  6:52 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-04 12:55 [PATCH 0/3] intel_iommu: Add missed sanity check for invalidae descriptor Zhenzhong Duan
2024-11-04 12:55 ` [PATCH 1/3] intel_iommu: Send IQE event when setting reserved bit in IQT_TAIL Zhenzhong Duan
2024-11-05  6:37   ` CLEMENT MATHIEU--DRIF
2024-11-05  6:52   ` Yi Liu
2024-11-04 12:55 ` [PATCH 2/3] intel_iommu: Add missed sanity check for 256-bit invalidation queue Zhenzhong Duan
2024-11-04 14:46   ` Michael S. Tsirkin
2024-11-05  2:40     ` Duan, Zhenzhong
2024-11-05  5:05   ` Yi Liu
2024-11-05  6:12     ` Duan, Zhenzhong
2024-11-05  6:50       ` Yi Liu
2024-11-05  7:43         ` Duan, Zhenzhong
2024-11-05  6:36   ` CLEMENT MATHIEU--DRIF
2024-11-05  7:38     ` Duan, Zhenzhong
2024-11-05  8:03       ` CLEMENT MATHIEU--DRIF
2024-11-04 12:55 ` [PATCH 3/3] intel_iommu: Add missed reserved bit check for IEC descriptor Zhenzhong Duan
2024-11-05  6:37   ` CLEMENT MATHIEU--DRIF
2024-11-05  6:56   ` Yi Liu [this message]

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