From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, peter.maydell@linaro.org,
alex.bennee@linaro.org,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [PATCH] fpu: Add conversions between bfloat16 and [u]int8
Date: Thu, 1 Jun 2023 09:49:30 +0800 [thread overview]
Message-ID: <ac6dff2d-b9ef-19a8-274a-4e33a5b97d7f@linux.alibaba.com> (raw)
In-Reply-To: <686ffc58-4d2d-f9a9-49b0-722dcedc2dc5@linaro.org>
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On 2023/6/1 1:47, Richard Henderson wrote:
> On 5/30/23 23:54, LIU Zhiwei wrote:
>> We missed these functions when upstreaming the bfloat16 support.
>>
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>
> They look ok, so far as it goes. What will they be used for?
T-Head Xuantie CPUs custom extension need these interfaces. It uses a
custom CSR(still not upstream) to switch between the fp16 and bfloat16.
All fp16 instructions(Zfh) can process the bfloat16 types. In its custom
matrix extension[1] or vector extension, this feature is also supported.
As a side note, the RISC-V port support for custom extension at least
should have these aspects:
* ISA decoding (Ready, Philipp Tomsich)
* CSR (WIP, Andes?)
* Disassemble(Under review, Christopher)
* Errata(Not start)
* Split TB flags like ARM for custom(In the wild for the Xuantie CPUs)
1.
https://github.com/T-head-Semi/riscv-matrix-extension-spec/releases/tag/v0.1.0
>
>
> r~
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next prev parent reply other threads:[~2023-06-01 1:50 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-31 6:54 [PATCH] fpu: Add conversions between bfloat16 and [u]int8 LIU Zhiwei
[not found] ` <686ffc58-4d2d-f9a9-49b0-722dcedc2dc5@linaro.org>
2023-06-01 1:49 ` LIU Zhiwei [this message]
2023-09-13 9:54 ` LIU Zhiwei
2023-09-15 12:35 ` Richard Henderson
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