* [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-29 17:03 ` Cédric Le Goater
2025-01-30 3:27 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops Jamin Lin via
` (17 subsequent siblings)
18 siblings, 2 replies; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
The design of the INTC has significant changes in the AST2700 A1. In the
AST2700 A0, there was one INTC controller, whereas in the AST2700 A1,
there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O DIE).
The previous INTC model only supported the AST2700 A0 and was implemented for
the INTC0 (CPU DIE). To support the future INTC1 (I/O DIE) model, rename INTC
to INTC0.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 6 +--
hw/intc/aspeed_intc.c | 90 +++++++++++++++++------------------
include/hw/arm/aspeed_soc.h | 2 +-
include/hw/intc/aspeed_intc.h | 2 +-
4 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 4114e15ddd..ba461fcd3c 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -56,7 +56,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_ETH2] = 0x14060000,
[ASPEED_DEV_ETH3] = 0x14070000,
[ASPEED_DEV_EMMC] = 0x12090000,
- [ASPEED_DEV_INTC] = 0x12100000,
+ [ASPEED_DEV_INTC0] = 0x12100000,
[ASPEED_DEV_SLI] = 0x12C17000,
[ASPEED_DEV_SLIIO] = 0x14C1E000,
[ASPEED_GIC_DIST] = 0x12200000,
@@ -372,7 +372,7 @@ static void aspeed_soc_ast2700_init(Object *obj)
object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO);
- object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC);
+ object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC0);
snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
object_initialize_child(obj, "adc", &s->adc, typename);
@@ -517,7 +517,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
}
aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
- sc->memmap[ASPEED_DEV_INTC]);
+ sc->memmap[ASPEED_DEV_INTC0]);
/* GICINT orgates -> INTC -> GIC */
for (i = 0; i < ic->num_ints; i++) {
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 126b711b94..df4da759e1 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -14,27 +14,27 @@
#include "hw/registerfields.h"
#include "qapi/error.h"
-/* INTC Registers */
-REG32(GICINT128_EN, 0x1000)
-REG32(GICINT128_STATUS, 0x1004)
-REG32(GICINT129_EN, 0x1100)
-REG32(GICINT129_STATUS, 0x1104)
-REG32(GICINT130_EN, 0x1200)
-REG32(GICINT130_STATUS, 0x1204)
-REG32(GICINT131_EN, 0x1300)
-REG32(GICINT131_STATUS, 0x1304)
-REG32(GICINT132_EN, 0x1400)
-REG32(GICINT132_STATUS, 0x1404)
-REG32(GICINT133_EN, 0x1500)
-REG32(GICINT133_STATUS, 0x1504)
-REG32(GICINT134_EN, 0x1600)
-REG32(GICINT134_STATUS, 0x1604)
-REG32(GICINT135_EN, 0x1700)
-REG32(GICINT135_STATUS, 0x1704)
-REG32(GICINT136_EN, 0x1800)
-REG32(GICINT136_STATUS, 0x1804)
-
-#define GICINT_STATUS_BASE R_GICINT128_STATUS
+/* AST2700 INTC0 Registers */
+REG32(INTC0_GICINT128_EN, 0x1000)
+REG32(INTC0_GICINT128_STATUS, 0x1004)
+REG32(INTC0_GICINT129_EN, 0x1100)
+REG32(INTC0_GICINT129_STATUS, 0x1104)
+REG32(INTC0_GICINT130_EN, 0x1200)
+REG32(INTC0_GICINT130_STATUS, 0x1204)
+REG32(INTC0_GICINT131_EN, 0x1300)
+REG32(INTC0_GICINT131_STATUS, 0x1304)
+REG32(INTC0_GICINT132_EN, 0x1400)
+REG32(INTC0_GICINT132_STATUS, 0x1404)
+REG32(INTC0_GICINT133_EN, 0x1500)
+REG32(INTC0_GICINT133_STATUS, 0x1504)
+REG32(INTC0_GICINT134_EN, 0x1600)
+REG32(INTC0_GICINT134_STATUS, 0x1604)
+REG32(INTC0_GICINT135_EN, 0x1700)
+REG32(INTC0_GICINT135_STATUS, 0x1704)
+REG32(INTC0_GICINT136_EN, 0x1800)
+REG32(INTC0_GICINT136_STATUS, 0x1804)
+
+#define GICINT_STATUS_BASE R_INTC0_GICINT128_STATUS
static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
{
@@ -153,15 +153,15 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
trace_aspeed_intc_write(offset, size, data);
switch (addr) {
- case R_GICINT128_EN:
- case R_GICINT129_EN:
- case R_GICINT130_EN:
- case R_GICINT131_EN:
- case R_GICINT132_EN:
- case R_GICINT133_EN:
- case R_GICINT134_EN:
- case R_GICINT135_EN:
- case R_GICINT136_EN:
+ case R_INTC0_GICINT128_EN:
+ case R_INTC0_GICINT129_EN:
+ case R_INTC0_GICINT130_EN:
+ case R_INTC0_GICINT131_EN:
+ case R_INTC0_GICINT132_EN:
+ case R_INTC0_GICINT133_EN:
+ case R_INTC0_GICINT134_EN:
+ case R_INTC0_GICINT135_EN:
+ case R_INTC0_GICINT136_EN:
irq = (offset & 0x0f00) >> 8;
if (irq >= aic->num_ints) {
@@ -202,15 +202,15 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
}
s->regs[addr] = data;
break;
- case R_GICINT128_STATUS:
- case R_GICINT129_STATUS:
- case R_GICINT130_STATUS:
- case R_GICINT131_STATUS:
- case R_GICINT132_STATUS:
- case R_GICINT133_STATUS:
- case R_GICINT134_STATUS:
- case R_GICINT135_STATUS:
- case R_GICINT136_STATUS:
+ case R_INTC0_GICINT128_STATUS:
+ case R_INTC0_GICINT129_STATUS:
+ case R_INTC0_GICINT130_STATUS:
+ case R_INTC0_GICINT131_STATUS:
+ case R_INTC0_GICINT132_STATUS:
+ case R_INTC0_GICINT133_STATUS:
+ case R_INTC0_GICINT134_STATUS:
+ case R_INTC0_GICINT135_STATUS:
+ case R_INTC0_GICINT136_STATUS:
irq = (offset & 0x0f00) >> 8;
if (irq >= aic->num_ints) {
@@ -336,26 +336,26 @@ static const TypeInfo aspeed_intc_info = {
.abstract = true,
};
-static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
+static void aspeed_2700_intc0_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
- dc->desc = "ASPEED 2700 INTC Controller";
+ dc->desc = "ASPEED 2700 INTC 0 Controller";
aic->num_lines = 32;
aic->num_ints = 9;
}
-static const TypeInfo aspeed_2700_intc_info = {
- .name = TYPE_ASPEED_2700_INTC,
+static const TypeInfo aspeed_2700_intc0_info = {
+ .name = TYPE_ASPEED_2700_INTC0,
.parent = TYPE_ASPEED_INTC,
- .class_init = aspeed_2700_intc_class_init,
+ .class_init = aspeed_2700_intc0_class_init,
};
static void aspeed_intc_register_types(void)
{
type_register_static(&aspeed_intc_info);
- type_register_static(&aspeed_2700_intc_info);
+ type_register_static(&aspeed_2700_intc0_info);
}
type_init(aspeed_intc_register_types);
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 689f52dae8..51e585e3e4 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -194,7 +194,7 @@ enum {
ASPEED_DEV_EHCI1,
ASPEED_DEV_EHCI2,
ASPEED_DEV_VIC,
- ASPEED_DEV_INTC,
+ ASPEED_DEV_INTC0,
ASPEED_DEV_SDMC,
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 18cb43476c..10718ed4a1 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -13,7 +13,7 @@
#include "hw/or-irq.h"
#define TYPE_ASPEED_INTC "aspeed.intc"
-#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
+#define TYPE_ASPEED_2700_INTC0 TYPE_ASPEED_INTC "0" "-ast2700"
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
#define ASPEED_INTC_NR_REGS (0x2000 >> 2)
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
2025-01-21 7:04 ` [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0 Jamin Lin via
@ 2025-01-29 17:03 ` Cédric Le Goater
2025-01-30 3:22 ` Andrew Jeffery
2025-01-30 3:27 ` Andrew Jeffery
1 sibling, 1 reply; 54+ messages in thread
From: Cédric Le Goater @ 2025-01-29 17:03 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On 1/21/25 08:04, Jamin Lin wrote:
> The design of the INTC has significant changes in the AST2700 A1. In the
> AST2700 A0, there was one INTC controller, whereas in the AST2700 A1,
> there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O DIE).
>
> The previous INTC model only supported the AST2700 A0 and was implemented for
> the INTC0 (CPU DIE). To support the future INTC1 (I/O DIE) model, rename INTC
> to INTC0.
Why not introduce definitions with _INTC_IO_ and leave alone the current
instead ? Do we expect to have more than 2 INTC controllers ?
Thanks,
C.
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> hw/arm/aspeed_ast27x0.c | 6 +--
> hw/intc/aspeed_intc.c | 90 +++++++++++++++++------------------
> include/hw/arm/aspeed_soc.h | 2 +-
> include/hw/intc/aspeed_intc.h | 2 +-
> 4 files changed, 50 insertions(+), 50 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 4114e15ddd..ba461fcd3c 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -56,7 +56,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_ETH2] = 0x14060000,
> [ASPEED_DEV_ETH3] = 0x14070000,
> [ASPEED_DEV_EMMC] = 0x12090000,
> - [ASPEED_DEV_INTC] = 0x12100000,
> + [ASPEED_DEV_INTC0] = 0x12100000,
> [ASPEED_DEV_SLI] = 0x12C17000,
> [ASPEED_DEV_SLIIO] = 0x14C1E000,
> [ASPEED_GIC_DIST] = 0x12200000,
> @@ -372,7 +372,7 @@ static void aspeed_soc_ast2700_init(Object *obj)
>
> object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
> object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO);
> - object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC);
> + object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC0);
>
> snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
> object_initialize_child(obj, "adc", &s->adc, typename);
> @@ -517,7 +517,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> }
>
> aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
> - sc->memmap[ASPEED_DEV_INTC]);
> + sc->memmap[ASPEED_DEV_INTC0]);
>
> /* GICINT orgates -> INTC -> GIC */
> for (i = 0; i < ic->num_ints; i++) {
> diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
> index 126b711b94..df4da759e1 100644
> --- a/hw/intc/aspeed_intc.c
> +++ b/hw/intc/aspeed_intc.c
> @@ -14,27 +14,27 @@
> #include "hw/registerfields.h"
> #include "qapi/error.h"
>
> -/* INTC Registers */
> -REG32(GICINT128_EN, 0x1000)
> -REG32(GICINT128_STATUS, 0x1004)
> -REG32(GICINT129_EN, 0x1100)
> -REG32(GICINT129_STATUS, 0x1104)
> -REG32(GICINT130_EN, 0x1200)
> -REG32(GICINT130_STATUS, 0x1204)
> -REG32(GICINT131_EN, 0x1300)
> -REG32(GICINT131_STATUS, 0x1304)
> -REG32(GICINT132_EN, 0x1400)
> -REG32(GICINT132_STATUS, 0x1404)
> -REG32(GICINT133_EN, 0x1500)
> -REG32(GICINT133_STATUS, 0x1504)
> -REG32(GICINT134_EN, 0x1600)
> -REG32(GICINT134_STATUS, 0x1604)
> -REG32(GICINT135_EN, 0x1700)
> -REG32(GICINT135_STATUS, 0x1704)
> -REG32(GICINT136_EN, 0x1800)
> -REG32(GICINT136_STATUS, 0x1804)
> -
> -#define GICINT_STATUS_BASE R_GICINT128_STATUS
> +/* AST2700 INTC0 Registers */
> +REG32(INTC0_GICINT128_EN, 0x1000)
> +REG32(INTC0_GICINT128_STATUS, 0x1004)
> +REG32(INTC0_GICINT129_EN, 0x1100)
> +REG32(INTC0_GICINT129_STATUS, 0x1104)
> +REG32(INTC0_GICINT130_EN, 0x1200)
> +REG32(INTC0_GICINT130_STATUS, 0x1204)
> +REG32(INTC0_GICINT131_EN, 0x1300)
> +REG32(INTC0_GICINT131_STATUS, 0x1304)
> +REG32(INTC0_GICINT132_EN, 0x1400)
> +REG32(INTC0_GICINT132_STATUS, 0x1404)
> +REG32(INTC0_GICINT133_EN, 0x1500)
> +REG32(INTC0_GICINT133_STATUS, 0x1504)
> +REG32(INTC0_GICINT134_EN, 0x1600)
> +REG32(INTC0_GICINT134_STATUS, 0x1604)
> +REG32(INTC0_GICINT135_EN, 0x1700)
> +REG32(INTC0_GICINT135_STATUS, 0x1704)
> +REG32(INTC0_GICINT136_EN, 0x1800)
> +REG32(INTC0_GICINT136_STATUS, 0x1804)
> +
> +#define GICINT_STATUS_BASE R_INTC0_GICINT128_STATUS
>
> static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
> {
> @@ -153,15 +153,15 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
> trace_aspeed_intc_write(offset, size, data);
>
> switch (addr) {
> - case R_GICINT128_EN:
> - case R_GICINT129_EN:
> - case R_GICINT130_EN:
> - case R_GICINT131_EN:
> - case R_GICINT132_EN:
> - case R_GICINT133_EN:
> - case R_GICINT134_EN:
> - case R_GICINT135_EN:
> - case R_GICINT136_EN:
> + case R_INTC0_GICINT128_EN:
> + case R_INTC0_GICINT129_EN:
> + case R_INTC0_GICINT130_EN:
> + case R_INTC0_GICINT131_EN:
> + case R_INTC0_GICINT132_EN:
> + case R_INTC0_GICINT133_EN:
> + case R_INTC0_GICINT134_EN:
> + case R_INTC0_GICINT135_EN:
> + case R_INTC0_GICINT136_EN:
> irq = (offset & 0x0f00) >> 8;
>
> if (irq >= aic->num_ints) {
> @@ -202,15 +202,15 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
> }
> s->regs[addr] = data;
> break;
> - case R_GICINT128_STATUS:
> - case R_GICINT129_STATUS:
> - case R_GICINT130_STATUS:
> - case R_GICINT131_STATUS:
> - case R_GICINT132_STATUS:
> - case R_GICINT133_STATUS:
> - case R_GICINT134_STATUS:
> - case R_GICINT135_STATUS:
> - case R_GICINT136_STATUS:
> + case R_INTC0_GICINT128_STATUS:
> + case R_INTC0_GICINT129_STATUS:
> + case R_INTC0_GICINT130_STATUS:
> + case R_INTC0_GICINT131_STATUS:
> + case R_INTC0_GICINT132_STATUS:
> + case R_INTC0_GICINT133_STATUS:
> + case R_INTC0_GICINT134_STATUS:
> + case R_INTC0_GICINT135_STATUS:
> + case R_INTC0_GICINT136_STATUS:
> irq = (offset & 0x0f00) >> 8;
>
> if (irq >= aic->num_ints) {
> @@ -336,26 +336,26 @@ static const TypeInfo aspeed_intc_info = {
> .abstract = true,
> };
>
> -static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
> +static void aspeed_2700_intc0_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
>
> - dc->desc = "ASPEED 2700 INTC Controller";
> + dc->desc = "ASPEED 2700 INTC 0 Controller";
> aic->num_lines = 32;
> aic->num_ints = 9;
> }
>
> -static const TypeInfo aspeed_2700_intc_info = {
> - .name = TYPE_ASPEED_2700_INTC,
> +static const TypeInfo aspeed_2700_intc0_info = {
> + .name = TYPE_ASPEED_2700_INTC0,
> .parent = TYPE_ASPEED_INTC,
> - .class_init = aspeed_2700_intc_class_init,
> + .class_init = aspeed_2700_intc0_class_init,
> };
>
> static void aspeed_intc_register_types(void)
> {
> type_register_static(&aspeed_intc_info);
> - type_register_static(&aspeed_2700_intc_info);
> + type_register_static(&aspeed_2700_intc0_info);
> }
>
> type_init(aspeed_intc_register_types);
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 689f52dae8..51e585e3e4 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -194,7 +194,7 @@ enum {
> ASPEED_DEV_EHCI1,
> ASPEED_DEV_EHCI2,
> ASPEED_DEV_VIC,
> - ASPEED_DEV_INTC,
> + ASPEED_DEV_INTC0,
> ASPEED_DEV_SDMC,
> ASPEED_DEV_SCU,
> ASPEED_DEV_ADC,
> diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
> index 18cb43476c..10718ed4a1 100644
> --- a/include/hw/intc/aspeed_intc.h
> +++ b/include/hw/intc/aspeed_intc.h
> @@ -13,7 +13,7 @@
> #include "hw/or-irq.h"
>
> #define TYPE_ASPEED_INTC "aspeed.intc"
> -#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
> +#define TYPE_ASPEED_2700_INTC0 TYPE_ASPEED_INTC "0" "-ast2700"
> OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
>
> #define ASPEED_INTC_NR_REGS (0x2000 >> 2)
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
2025-01-29 17:03 ` Cédric Le Goater
@ 2025-01-30 3:22 ` Andrew Jeffery
2025-02-04 6:50 ` Jamin Lin
0 siblings, 1 reply; 54+ messages in thread
From: Andrew Jeffery @ 2025-01-30 3:22 UTC (permalink / raw)
To: Cédric Le Goater, Jamin Lin, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On Wed, 2025-01-29 at 18:03 +0100, Cédric Le Goater wrote:
> On 1/21/25 08:04, Jamin Lin wrote:
> > The design of the INTC has significant changes in the AST2700 A1.
> > In the
> > AST2700 A0, there was one INTC controller, whereas in the AST2700
> > A1,
> > there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O
> > DIE).
> >
> > The previous INTC model only supported the AST2700 A0 and was
> > implemented for
> > the INTC0 (CPU DIE). To support the future INTC1 (I/O DIE) model,
> > rename INTC
> > to INTC0.
>
>
> Why not introduce definitions with _INTC_IO_ and leave alone the
> current
> instead ? Do we expect to have more than 2 INTC controllers ?
>
There was similar discussion on the devicetree bindings for the SCU a
while back:
https://lore.kernel.org/all/94efc2d4ff280a112b869124fc9d7e35ac031596.camel@codeconstruct.com.au/
Ryan didn't like deviating from their internal documentation :(
Andrew
^ permalink raw reply [flat|nested] 54+ messages in thread
* RE: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
2025-01-30 3:22 ` Andrew Jeffery
@ 2025-02-04 6:50 ` Jamin Lin
2025-02-04 7:34 ` Cédric Le Goater
0 siblings, 1 reply; 54+ messages in thread
From: Jamin Lin @ 2025-02-04 6:50 UTC (permalink / raw)
To: Andrew Jeffery, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hi Cedric, Andrew
> From: Andrew Jeffery <andrew@codeconstruct.com.au>
> Sent: Thursday, January 30, 2025 11:22 AM
> To: Cédric Le Goater <clg@kaod.org>; Jamin Lin <jamin_lin@aspeedtech.com>;
> Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel Stanley
> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
>
> On Wed, 2025-01-29 at 18:03 +0100, Cédric Le Goater wrote:
> > On 1/21/25 08:04, Jamin Lin wrote:
> > > The design of the INTC has significant changes in the AST2700 A1.
> > > In the
> > > AST2700 A0, there was one INTC controller, whereas in the AST2700
> > > A1, there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O
> > > DIE).
> > >
> > > The previous INTC model only supported the AST2700 A0 and was
> > > implemented for the INTC0 (CPU DIE). To support the future INTC1
> > > (I/O DIE) model, rename INTC to INTC0.
> >
> >
> > Why not introduce definitions with _INTC_IO_ and leave alone the
> > current instead ? Do we expect to have more than 2 INTC controllers ?
> >
>
> There was similar discussion on the devicetree bindings for the SCU a
> while back:
>
> https://lore.kernel.org/all/94efc2d4ff280a112b869124fc9d7e35ac031596.cam
> el@codeconstruct.com.au/
>
> Ryan didn't like deviating from their internal documentation :(
>
> Andrew
Thanks for your suggestion.
Last year, Troy and I implemented the SCU(CPU Die) and SCU_IO(IO Die) models to support the AST2700.
https://github.com/qemu/qemu/blob/master/hw/misc/aspeed_scu.c#L1073
https://github.com/qemu/qemu/blob/master/hw/misc/aspeed_scu.c#L1080
I am fine with keeping the INTC(CPU Die) naming and creating a new INTC_IO(IO Die) model to support the AST2700 A1.
I have a question regarding the INTC_IO model implementation:
Can I define separate "intc_io_class_init" and "intcio_class_realize" functions for INTC_IO, similar to the SCU/SCU_IO models?
If yes, I think the patch “2 Support different memory region ops” can be omitted.
Additionally, I suggest that both INTC and INTC_IO have their own MMIO callback functions, as their register addresses are different.
Thanks-Jamin
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
2025-02-04 6:50 ` Jamin Lin
@ 2025-02-04 7:34 ` Cédric Le Goater
2025-02-04 8:22 ` Jamin Lin
0 siblings, 1 reply; 54+ messages in thread
From: Cédric Le Goater @ 2025-02-04 7:34 UTC (permalink / raw)
To: Jamin Lin, Andrew Jeffery, Peter Maydell, Steven Lee, Troy Lee,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
On 2/4/25 07:50, Jamin Lin wrote:
> Hi Cedric, Andrew
>
>> From: Andrew Jeffery <andrew@codeconstruct.com.au>
>> Sent: Thursday, January 30, 2025 11:22 AM
>> To: Cédric Le Goater <clg@kaod.org>; Jamin Lin <jamin_lin@aspeedtech.com>;
>> Peter Maydell <peter.maydell@linaro.org>; Steven Lee
>> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel Stanley
>> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
>> list:All patches CC here <qemu-devel@nongnu.org>
>> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
>> <yunlin.tang@aspeedtech.com>
>> Subject: Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
>>
>> On Wed, 2025-01-29 at 18:03 +0100, Cédric Le Goater wrote:
>>> On 1/21/25 08:04, Jamin Lin wrote:
>>>> The design of the INTC has significant changes in the AST2700 A1.
>>>> In the
>>>> AST2700 A0, there was one INTC controller, whereas in the AST2700
>>>> A1, there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O
>>>> DIE).
>>>>
>>>> The previous INTC model only supported the AST2700 A0 and was
>>>> implemented for the INTC0 (CPU DIE). To support the future INTC1
>>>> (I/O DIE) model, rename INTC to INTC0.
>>>
>>>
>>> Why not introduce definitions with _INTC_IO_ and leave alone the
>>> current instead ? Do we expect to have more than 2 INTC controllers ?
>>>
>>
>> There was similar discussion on the devicetree bindings for the SCU a
>> while back:
>>
>> https://lore.kernel.org/all/94efc2d4ff280a112b869124fc9d7e35ac031596.cam
>> el@codeconstruct.com.au/
>>
>> Ryan didn't like deviating from their internal documentation :(
>>
>> Andrew
>
>
> Thanks for your suggestion.
>
> Last year, Troy and I implemented the SCU(CPU Die) and SCU_IO(IO Die) models to support the AST2700.
> https://github.com/qemu/qemu/blob/master/hw/misc/aspeed_scu.c#L1073
> https://github.com/qemu/qemu/blob/master/hw/misc/aspeed_scu.c#L1080
> > I am fine with keeping the INTC(CPU Die) naming and creating a new INTC_IO(IO Die) model to support the AST2700 A1.
Good. I think this will reduce the changes and clarify the models.
> I have a question regarding the INTC_IO model implementation:
> Can I define separate "intc_io_class_init" and "intcio_class_realize" functions for INTC_IO, similar to the SCU/SCU_IO models?
Looks OK to me.
> If yes, I think the patch “2 Support different memory region ops” can be omitted.
> Additionally, I suggest that both INTC and INTC_IO have their own MMIO callback functions, as their register addresses are different.
Do you mean the register offset in the MMIO aperture ? We try
to avoid duplication unless the code becomes too complex.
Please send a v2, splitting your series in 3 as requested in
the other email.
Thanks,
C.
^ permalink raw reply [flat|nested] 54+ messages in thread
* RE: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
2025-02-04 7:34 ` Cédric Le Goater
@ 2025-02-04 8:22 ` Jamin Lin
2025-02-04 10:26 ` Cédric Le Goater
0 siblings, 1 reply; 54+ messages in thread
From: Jamin Lin @ 2025-02-04 8:22 UTC (permalink / raw)
To: Cédric Le Goater, Andrew Jeffery, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hi Cedric,
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Tuesday, February 4, 2025 3:35 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Andrew Jeffery
> <andrew@codeconstruct.com.au>; Peter Maydell <peter.maydell@linaro.org>;
> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>;
> Joel Stanley <joel@jms.id.au>; open list:ASPEED BMCs
> <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
>
> On 2/4/25 07:50, Jamin Lin wrote:
> > Hi Cedric, Andrew
> >
> >> From: Andrew Jeffery <andrew@codeconstruct.com.au>
> >> Sent: Thursday, January 30, 2025 11:22 AM
> >> To: Cédric Le Goater <clg@kaod.org>; Jamin Lin
> >> <jamin_lin@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>;
> >> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee
> <leetroy@gmail.com>;
> >> Joel Stanley <joel@jms.id.au>; open list:ASPEED BMCs
> >> <qemu-arm@nongnu.org>; open list:All patches CC here
> >> <qemu-devel@nongnu.org>
> >> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> >> <yunlin.tang@aspeedtech.com>
> >> Subject: Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
> >>
> >> On Wed, 2025-01-29 at 18:03 +0100, Cédric Le Goater wrote:
> >>> On 1/21/25 08:04, Jamin Lin wrote:
> >>>> The design of the INTC has significant changes in the AST2700 A1.
> >>>> In the
> >>>> AST2700 A0, there was one INTC controller, whereas in the AST2700
> >>>> A1, there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O
> >>>> DIE).
> >>>>
> >>>> The previous INTC model only supported the AST2700 A0 and was
> >>>> implemented for the INTC0 (CPU DIE). To support the future INTC1
> >>>> (I/O DIE) model, rename INTC to INTC0.
> >>>
> >>>
> >>> Why not introduce definitions with _INTC_IO_ and leave alone the
> >>> current instead ? Do we expect to have more than 2 INTC controllers ?
> >>>
> >>
> >> There was similar discussion on the devicetree bindings for the SCU a
> >> while back:
> >>
> >> https://lore.kernel.org/all/94efc2d4ff280a112b869124fc9d7e35ac031596.
> >> cam
> >> el@codeconstruct.com.au/
> >>
> >> Ryan didn't like deviating from their internal documentation :(
> >>
> >> Andrew
> >
> >
> > Thanks for your suggestion.
> >
> > Last year, Troy and I implemented the SCU(CPU Die) and SCU_IO(IO Die)
> models to support the AST2700.
> > https://github.com/qemu/qemu/blob/master/hw/misc/aspeed_scu.c#L1073
> > https://github.com/qemu/qemu/blob/master/hw/misc/aspeed_scu.c#L1080
> > > I am fine with keeping the INTC(CPU Die) naming and creating a new
> INTC_IO(IO Die) model to support the AST2700 A1.
>
> Good. I think this will reduce the changes and clarify the models.
>
> > I have a question regarding the INTC_IO model implementation:
> > Can I define separate "intc_io_class_init" and "intcio_class_realize" functions
> for INTC_IO, similar to the SCU/SCU_IO models?
>
> Looks OK to me.
>
> > If yes, I think the patch “2 Support different memory region ops” can be
> omitted.
> > Additionally, I suggest that both INTC and INTC_IO have their own MMIO
> callback functions, as their register addresses are different.
>
> Do you mean the register offset in the MMIO aperture ? We try to avoid
> duplication unless the code becomes too complex.
I means both INTC_IO and INTC_CPU use the same offset but different register definitions.
INTC0:
INTC0_10
INTC0_14
INTC1:
INTC1_10
INTC1_14
I will implement as following
static void aspeed_intc_register_types(void)
{
type_register_static(&aspeed_intc_info);
type_register_static(&aspeed_2700_intc_info);
type_register_static(&aspeed_intcio_info);
type_register_static(&aspeed_2700_intcio_info);
}
static void aspeed_2700_intcio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
dc->desc = "ASPEED 2700 INTC IO Controller";
}
static const TypeInfo aspeed_2700_intcio_info = {
.name = TYPE_ASPEED_2700_INTCIO,
.parent = TYPE_ASPEED_INTCIO,
.class_init = aspeed_2700_intcio_class_init,
};
static void aspeed_intcio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "ASPEED INTC IO Controller";
dc->realize = aspeed_intcio_realize;
device_class_set_legacy_reset(dc, aspeed_intcio_reset);
dc->vmsd = NULL;
}
static const TypeInfo aspeed_intcio_info = {
.name = TYPE_ASPEED_INTCIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_init = aspeed_intcio_instance_init,
.instance_size = sizeof(AspeedINTCIOState),
.class_init = aspeed_intcio_class_init,
.class_size = sizeof(AspeedINTCIOClass),
.abstract = true,
};
static void aspeed_intcio_realize(DeviceState *dev, Error **errp)
{
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intcio_ops, s,
TYPE_ASPEED_INTCIO ".regs", ASPEED_INTC_NR_REGS << 2);
}
static void aspeed_intcio_reset(DeviceState *dev)
{
}
static void aspeed_intcio_instance_init(Object *obj)
{
}
I want to create aspeed_intcio_read and aspeed_intcio_write call back functions.
static const MemoryRegionOps aspeed_intcio_ops = {
.read = aspeed_intcio_read,
.write = aspeed_intcio_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
}
};
Thanks-Jamin
>
> Please send a v2, splitting your series in 3 as requested in the other email.
>
Will resend
> Thanks,
>
> C.
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
2025-02-04 8:22 ` Jamin Lin
@ 2025-02-04 10:26 ` Cédric Le Goater
0 siblings, 0 replies; 54+ messages in thread
From: Cédric Le Goater @ 2025-02-04 10:26 UTC (permalink / raw)
To: Jamin Lin, Andrew Jeffery, Peter Maydell, Steven Lee, Troy Lee,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
On 2/4/25 09:22, Jamin Lin wrote:
> Hi Cedric,
>
>> From: Cédric Le Goater <clg@kaod.org>
>> Sent: Tuesday, February 4, 2025 3:35 PM
>> To: Jamin Lin <jamin_lin@aspeedtech.com>; Andrew Jeffery
>> <andrew@codeconstruct.com.au>; Peter Maydell <peter.maydell@linaro.org>;
>> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>;
>> Joel Stanley <joel@jms.id.au>; open list:ASPEED BMCs
>> <qemu-arm@nongnu.org>; open list:All patches CC here
>> <qemu-devel@nongnu.org>
>> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
>> <yunlin.tang@aspeedtech.com>
>> Subject: Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
>>
>> On 2/4/25 07:50, Jamin Lin wrote:
>>> Hi Cedric, Andrew
>>>
>>>> From: Andrew Jeffery <andrew@codeconstruct.com.au>
>>>> Sent: Thursday, January 30, 2025 11:22 AM
>>>> To: Cédric Le Goater <clg@kaod.org>; Jamin Lin
>>>> <jamin_lin@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>;
>>>> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee
>> <leetroy@gmail.com>;
>>>> Joel Stanley <joel@jms.id.au>; open list:ASPEED BMCs
>>>> <qemu-arm@nongnu.org>; open list:All patches CC here
>>>> <qemu-devel@nongnu.org>
>>>> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
>>>> <yunlin.tang@aspeedtech.com>
>>>> Subject: Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
>>>>
>>>> On Wed, 2025-01-29 at 18:03 +0100, Cédric Le Goater wrote:
>>>>> On 1/21/25 08:04, Jamin Lin wrote:
>>>>>> The design of the INTC has significant changes in the AST2700 A1.
>>>>>> In the
>>>>>> AST2700 A0, there was one INTC controller, whereas in the AST2700
>>>>>> A1, there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O
>>>>>> DIE).
>>>>>>
>>>>>> The previous INTC model only supported the AST2700 A0 and was
>>>>>> implemented for the INTC0 (CPU DIE). To support the future INTC1
>>>>>> (I/O DIE) model, rename INTC to INTC0.
>>>>>
>>>>>
>>>>> Why not introduce definitions with _INTC_IO_ and leave alone the
>>>>> current instead ? Do we expect to have more than 2 INTC controllers ?
>>>>>
>>>>
>>>> There was similar discussion on the devicetree bindings for the SCU a
>>>> while back:
>>>>
>>>> https://lore.kernel.org/all/94efc2d4ff280a112b869124fc9d7e35ac031596.
>>>> cam
>>>> el@codeconstruct.com.au/
>>>>
>>>> Ryan didn't like deviating from their internal documentation :(
>>>>
>>>> Andrew
>>>
>>>
>>> Thanks for your suggestion.
>>>
>>> Last year, Troy and I implemented the SCU(CPU Die) and SCU_IO(IO Die)
>> models to support the AST2700.
>>> https://github.com/qemu/qemu/blob/master/hw/misc/aspeed_scu.c#L1073
>>> https://github.com/qemu/qemu/blob/master/hw/misc/aspeed_scu.c#L1080
>>>> I am fine with keeping the INTC(CPU Die) naming and creating a new
>> INTC_IO(IO Die) model to support the AST2700 A1.
>>
>> Good. I think this will reduce the changes and clarify the models.
>>
>>> I have a question regarding the INTC_IO model implementation:
>>> Can I define separate "intc_io_class_init" and "intcio_class_realize" functions
>> for INTC_IO, similar to the SCU/SCU_IO models?
>>
>> Looks OK to me.
>>
>>> If yes, I think the patch “2 Support different memory region ops” can be
>> omitted.
>>> Additionally, I suggest that both INTC and INTC_IO have their own MMIO
>> callback functions, as their register addresses are different.
>>
>> Do you mean the register offset in the MMIO aperture ? We try to avoid
>> duplication unless the code becomes too complex.
>
>
> I means both INTC_IO and INTC_CPU use the same offset but different register definitions.
>
> INTC0:
> INTC0_10
> INTC0_14
>
> INTC1:
> INTC1_10
> INTC1_14
can you define them as
INTC_xxx
to avoid all the duplication below ?
Thanks,
C.
> I will implement as following
>
> static void aspeed_intc_register_types(void)
> {
> type_register_static(&aspeed_intc_info);
> type_register_static(&aspeed_2700_intc_info);
> type_register_static(&aspeed_intcio_info);
> type_register_static(&aspeed_2700_intcio_info);
> }
>
> static void aspeed_2700_intcio_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
>
> dc->desc = "ASPEED 2700 INTC IO Controller";
> }
>
> static const TypeInfo aspeed_2700_intcio_info = {
> .name = TYPE_ASPEED_2700_INTCIO,
> .parent = TYPE_ASPEED_INTCIO,
> .class_init = aspeed_2700_intcio_class_init,
> };
>
> static void aspeed_intcio_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> dc->desc = "ASPEED INTC IO Controller";
> dc->realize = aspeed_intcio_realize;
> device_class_set_legacy_reset(dc, aspeed_intcio_reset);
> dc->vmsd = NULL;
> }
>
> static const TypeInfo aspeed_intcio_info = {
> .name = TYPE_ASPEED_INTCIO,
> .parent = TYPE_SYS_BUS_DEVICE,
> .instance_init = aspeed_intcio_instance_init,
> .instance_size = sizeof(AspeedINTCIOState),
> .class_init = aspeed_intcio_class_init,
> .class_size = sizeof(AspeedINTCIOClass),
> .abstract = true,
> };
>
> static void aspeed_intcio_realize(DeviceState *dev, Error **errp)
> {
> memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intcio_ops, s,
> TYPE_ASPEED_INTCIO ".regs", ASPEED_INTC_NR_REGS << 2);
> }
> static void aspeed_intcio_reset(DeviceState *dev)
> {
> }
> static void aspeed_intcio_instance_init(Object *obj)
> {
> }
>
> I want to create aspeed_intcio_read and aspeed_intcio_write call back functions.
>
> static const MemoryRegionOps aspeed_intcio_ops = {
> .read = aspeed_intcio_read,
> .write = aspeed_intcio_write,
> .endianness = DEVICE_LITTLE_ENDIAN,
> .valid = {
> .min_access_size = 4,
> .max_access_size = 4,
> }
> };
>
> Thanks-Jamin
>>
>> Please send a v2, splitting your series in 3 as requested in the other email.
>>
> Will resend
>> Thanks,
>>
>> C.
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
2025-01-21 7:04 ` [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0 Jamin Lin via
2025-01-29 17:03 ` Cédric Le Goater
@ 2025-01-30 3:27 ` Andrew Jeffery
1 sibling, 0 replies; 54+ messages in thread
From: Andrew Jeffery @ 2025-01-30 3:27 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The design of the INTC has significant changes in the AST2700 A1. In
> the
> AST2700 A0, there was one INTC controller, whereas in the AST2700 A1,
> there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O DIE).
>
> The previous INTC model only supported the AST2700 A0 and was
> implemented for
> the INTC0 (CPU DIE). To support the future INTC1 (I/O DIE) model,
> rename INTC
> to INTC0.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> hw/arm/aspeed_ast27x0.c | 6 +--
> hw/intc/aspeed_intc.c | 90 +++++++++++++++++----------------
> --
> include/hw/arm/aspeed_soc.h | 2 +-
> include/hw/intc/aspeed_intc.h | 2 +-
> 4 files changed, 50 insertions(+), 50 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 4114e15ddd..ba461fcd3c 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -56,7 +56,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_ETH2] = 0x14060000,
> [ASPEED_DEV_ETH3] = 0x14070000,
> [ASPEED_DEV_EMMC] = 0x12090000,
> - [ASPEED_DEV_INTC] = 0x12100000,
> + [ASPEED_DEV_INTC0] = 0x12100000,
> [ASPEED_DEV_SLI] = 0x12C17000,
> [ASPEED_DEV_SLIIO] = 0x14C1E000,
> [ASPEED_GIC_DIST] = 0x12200000,
> @@ -372,7 +372,7 @@ static void aspeed_soc_ast2700_init(Object *obj)
>
> object_initialize_child(obj, "sli", &s->sli,
> TYPE_ASPEED_2700_SLI);
> object_initialize_child(obj, "sliio", &s->sliio,
> TYPE_ASPEED_2700_SLIIO);
> - object_initialize_child(obj, "intc", &a->intc,
> TYPE_ASPEED_2700_INTC);
> + object_initialize_child(obj, "intc", &a->intc,
> TYPE_ASPEED_2700_INTC0);
Shouldn't we also change the propname to "intc0" (... if we're to
continue with that style of naming)?
Andrew
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0 Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-30 3:32 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 03/18] hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 Jamin Lin via
` (16 subsequent siblings)
18 siblings, 1 reply; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC0 (CPU DIE).
To support the INTC1 (I/O DIE) model, introduces a new "reg_ops" class
attribute. This allows setting different memory region operations to support
different INTC models.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 5 ++++-
include/hw/intc/aspeed_intc.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index df4da759e1..628f69ea88 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -302,7 +302,7 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
int i;
- memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s,
+ memory_region_init_io(&s->iomem, OBJECT(s), aic->reg_ops, s,
TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS << 2);
sysbus_init_mmio(sbd, &s->iomem);
@@ -319,11 +319,14 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
static void aspeed_intc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
dc->desc = "ASPEED INTC Controller";
dc->realize = aspeed_intc_realize;
device_class_set_legacy_reset(dc, aspeed_intc_reset);
dc->vmsd = NULL;
+
+ aic->reg_ops = &aspeed_intc_ops;
}
static const TypeInfo aspeed_intc_info = {
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 10718ed4a1..9a73661403 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -39,6 +39,7 @@ struct AspeedINTCClass {
uint32_t num_lines;
uint32_t num_ints;
+ const MemoryRegionOps *reg_ops;
};
#endif /* ASPEED_INTC_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops
2025-01-21 7:04 ` [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops Jamin Lin via
@ 2025-01-30 3:32 ` Andrew Jeffery
2025-02-04 7:00 ` Jamin Lin
0 siblings, 1 reply; 54+ messages in thread
From: Andrew Jeffery @ 2025-01-30 3:32 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The previous implementation set the "aspeed_intc_ops" struct,
> containing read
> and write callbacks, to be used when I/O is performed on the INTC
> region.
> Both "aspeed_intc_read" and "aspeed_intc_write" callback functions
> were used
> for INTC0 (CPU DIE).
>
> To support the INTC1 (I/O DIE) model, introduces a new "reg_ops"
> class
> attribute. This allows setting different memory region operations to
> support
> different INTC models.
Is there a reason not to make it a different type altogether? I'm not
sure I like the idea of playing tricks with the memory ops. The timer
model does something similar, but I was toying with the idea of
removing that part of its implementation...
Andrew
^ permalink raw reply [flat|nested] 54+ messages in thread
* RE: [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops
2025-01-30 3:32 ` Andrew Jeffery
@ 2025-02-04 7:00 ` Jamin Lin
0 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin @ 2025-02-04 7:00 UTC (permalink / raw)
To: Andrew Jeffery, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hi Andrew,
> From: Andrew Jeffery <andrew@codeconstruct.com.au>
> Sent: Thursday, January 30, 2025 11:32 AM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
> Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel Stanley
> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 02/18] hw/intc/aspeed: Support different memory
> region ops
>
> On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> > The previous implementation set the "aspeed_intc_ops" struct,
> > containing read and write callbacks, to be used when I/O is performed
> > on the INTC region.
> > Both "aspeed_intc_read" and "aspeed_intc_write" callback functions
> > were used for INTC0 (CPU DIE).
> >
> > To support the INTC1 (I/O DIE) model, introduces a new "reg_ops"
> > class
> > attribute. This allows setting different memory region operations to
> > support different INTC models.
>
> Is there a reason not to make it a different type altogether? I'm not sure I like
> the idea of playing tricks with the memory ops. The timer model does
> something similar, but I was toying with the idea of removing that part of its
> implementation...
>
Please see my comments in Patch 1.
The reason for the changes is that INTC0 and INTC1 have different address space and register definitions.
So, I created a separate callback functions for INTC0 and INTC1 register read/write operations.
INTC0:
INTC0_10
INTC0_14
INTC1:
INTC1_10
INTC1_14
Thanks-Jamin
> Andrew
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v1 03/18] hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 04/18] hw/intc/aspeed: Support setting different memory and register size Jamin Lin via
` (15 subsequent siblings)
18 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
Rename "aspeed_intc_read" to "aspeed_2700_intc0_read" and "aspeed_intc_write" to
"aspeed_2700_intc0_write".
Introduce a new memory region operation, "aspeed_2700_intc0_ops", for the
AST2700 INTC0 model.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 628f69ea88..219ca02940 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -114,7 +114,8 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
}
}
-static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int size)
+static uint64_t aspeed_2700_intc0_read(void *opaque, hwaddr offset,
+ unsigned int size)
{
AspeedINTCState *s = ASPEED_INTC(opaque);
uint32_t addr = offset >> 2;
@@ -133,8 +134,8 @@ static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int size)
return value;
}
-static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
- unsigned size)
+static void aspeed_2700_intc0_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size)
{
AspeedINTCState *s = ASPEED_INTC(opaque);
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
@@ -261,8 +262,6 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
}
static const MemoryRegionOps aspeed_intc_ops = {
- .read = aspeed_intc_read,
- .write = aspeed_intc_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
@@ -339,6 +338,16 @@ static const TypeInfo aspeed_intc_info = {
.abstract = true,
};
+static const MemoryRegionOps aspeed_2700_intc0_ops = {
+ .read = aspeed_2700_intc0_read,
+ .write = aspeed_2700_intc0_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
static void aspeed_2700_intc0_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -347,6 +356,7 @@ static void aspeed_2700_intc0_class_init(ObjectClass *klass, void *data)
dc->desc = "ASPEED 2700 INTC 0 Controller";
aic->num_lines = 32;
aic->num_ints = 9;
+ aic->reg_ops = &aspeed_2700_intc0_ops;
}
static const TypeInfo aspeed_2700_intc0_info = {
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v1 04/18] hw/intc/aspeed: Support setting different memory and register size
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (2 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 03/18] hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 05/18] hw/intc/aspeed: Introduce helper functions for enable and status registers Jamin Lin via
` (14 subsequent siblings)
18 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
According to the AST2700 datasheet, the INTC0 (CPU DIE) controller has 16KB
(0x4000) of register space, and the INTC1 (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.
Introduced a new class attribute "reg_size" to set different register sizes for
the INTC models in AST2700.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 17 +++++++++++++----
include/hw/intc/aspeed_intc.h | 4 ++++
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 219ca02940..25035c65ca 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -118,10 +118,11 @@ static uint64_t aspeed_2700_intc0_read(void *opaque, hwaddr offset,
unsigned int size)
{
AspeedINTCState *s = ASPEED_INTC(opaque);
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
uint32_t addr = offset >> 2;
uint32_t value = 0;
- if (addr >= ASPEED_INTC_NR_REGS) {
+ if (offset >= aic->reg_size) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
@@ -144,7 +145,7 @@ static void aspeed_2700_intc0_write(void *opaque, hwaddr offset, uint64_t data,
uint32_t change;
uint32_t irq;
- if (addr >= ASPEED_INTC_NR_REGS) {
+ if (offset >= aic->reg_size) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
@@ -301,10 +302,16 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
int i;
+ memory_region_init(&s->iomem_container, OBJECT(s),
+ TYPE_ASPEED_INTC ".container", aic->mem_size);
+
+ sysbus_init_mmio(sbd, &s->iomem_container);
+
memory_region_init_io(&s->iomem, OBJECT(s), aic->reg_ops, s,
- TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS << 2);
+ TYPE_ASPEED_INTC ".regs", aic->reg_size);
+
+ memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem);
- sysbus_init_mmio(sbd, &s->iomem);
qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints);
for (i = 0; i < aic->num_ints; i++) {
@@ -357,6 +364,8 @@ static void aspeed_2700_intc0_class_init(ObjectClass *klass, void *data)
aic->num_lines = 32;
aic->num_ints = 9;
aic->reg_ops = &aspeed_2700_intc0_ops;
+ aic->mem_size = 0x4000;
+ aic->reg_size = 0x2000;
}
static const TypeInfo aspeed_2700_intc0_info = {
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 9a73661403..d881cb7088 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -25,6 +25,8 @@ struct AspeedINTCState {
/*< public >*/
MemoryRegion iomem;
+ MemoryRegion iomem_container;
+
uint32_t regs[ASPEED_INTC_NR_REGS];
OrIRQState orgates[ASPEED_INTC_NR_INTS];
qemu_irq output_pins[ASPEED_INTC_NR_INTS];
@@ -40,6 +42,8 @@ struct AspeedINTCClass {
uint32_t num_lines;
uint32_t num_ints;
const MemoryRegionOps *reg_ops;
+ uint64_t mem_size;
+ uint64_t reg_size;
};
#endif /* ASPEED_INTC_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v1 05/18] hw/intc/aspeed: Introduce helper functions for enable and status registers
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (3 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 04/18] hw/intc/aspeed: Support setting different memory and register size Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
` (13 subsequent siblings)
18 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
The behavior of the enable and status registers is almost identical between
INTC0 and INTC1. To reduce duplicated code, adds
"aspeed_2700_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_2700_intc_status_handler" functions to handle status
register write behavior.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 189 ++++++++++++++++++++++++------------------
1 file changed, 107 insertions(+), 82 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 25035c65ca..7dff5e6039 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -114,6 +114,111 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
}
}
+static void aspeed_2700_intc_enable_handler(AspeedINTCState *s, uint32_t addr,
+ uint64_t data)
+{
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
+ uint32_t offset = addr << 2;
+ uint32_t old_enable;
+ uint32_t change;
+ uint32_t irq;
+
+ irq = (offset & 0x0f00) >> 8;
+
+ if (irq >= aic->num_ints) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
+ __func__, irq);
+ return;
+ }
+
+ /*
+ * The enable registers are used to enable source interrupts.
+ * They also handle masking and unmasking of source interrupts
+ * during the execution of the source ISR.
+ */
+
+ /* disable all source interrupt */
+ if (!data && !s->enable[irq]) {
+ s->regs[addr] = data;
+ return;
+ }
+
+ old_enable = s->enable[irq];
+ s->enable[irq] |= data;
+
+ /* enable new source interrupt */
+ if (old_enable != s->enable[irq]) {
+ trace_aspeed_intc_enable(s->enable[irq]);
+ s->regs[addr] = data;
+ return;
+ }
+
+ /* mask and unmask source interrupt */
+ change = s->regs[addr] ^ data;
+ if (change & data) {
+ s->mask[irq] &= ~change;
+ trace_aspeed_intc_unmask(change, s->mask[irq]);
+ } else {
+ s->mask[irq] |= change;
+ trace_aspeed_intc_mask(change, s->mask[irq]);
+ }
+ s->regs[addr] = data;
+}
+
+static void aspeed_2700_intc_status_handler(AspeedINTCState *s, uint32_t addr,
+ uint64_t data)
+{
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
+ uint32_t offset = addr << 2;
+ uint32_t irq;
+
+ irq = (offset & 0x0f00) >> 8;
+
+ if (!data) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__);
+ return;
+ }
+
+ if (irq >= aic->num_ints) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
+ __func__, irq);
+ return;
+ }
+
+ /* clear status */
+ s->regs[addr] &= ~data;
+
+ /*
+ * The status registers are used for notify sources ISR are executed.
+ * If one source ISR is executed, it will clear one bit.
+ * If it clear all bits, it means to initialize this register status
+ * rather than sources ISR are executed.
+ */
+ if (data == 0xffffffff) {
+ return;
+ }
+
+ /* All source ISR execution are done */
+ if (!s->regs[addr]) {
+ trace_aspeed_intc_all_isr_done(irq);
+ if (s->pending[irq]) {
+ /*
+ * handle pending source interrupt
+ * notify firmware which source interrupt are pending
+ * by setting status register
+ */
+ s->regs[addr] = s->pending[irq];
+ s->pending[irq] = 0;
+ trace_aspeed_intc_trigger_irq(irq, s->regs[addr]);
+ aspeed_intc_update(s, irq, 1);
+ } else {
+ /* clear irq */
+ trace_aspeed_intc_clear_irq(irq, 0);
+ aspeed_intc_update(s, irq, 0);
+ }
+ }
+}
+
static uint64_t aspeed_2700_intc0_read(void *opaque, hwaddr offset,
unsigned int size)
{
@@ -141,9 +246,6 @@ static void aspeed_2700_intc0_write(void *opaque, hwaddr offset, uint64_t data,
AspeedINTCState *s = ASPEED_INTC(opaque);
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
uint32_t addr = offset >> 2;
- uint32_t old_enable;
- uint32_t change;
- uint32_t irq;
if (offset >= aic->reg_size) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -164,45 +266,7 @@ static void aspeed_2700_intc0_write(void *opaque, hwaddr offset, uint64_t data,
case R_INTC0_GICINT134_EN:
case R_INTC0_GICINT135_EN:
case R_INTC0_GICINT136_EN:
- irq = (offset & 0x0f00) >> 8;
-
- if (irq >= aic->num_ints) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
- __func__, irq);
- return;
- }
-
- /*
- * These registers are used for enable sources interrupt and
- * mask and unmask source interrupt while executing source ISR.
- */
-
- /* disable all source interrupt */
- if (!data && !s->enable[irq]) {
- s->regs[addr] = data;
- return;
- }
-
- old_enable = s->enable[irq];
- s->enable[irq] |= data;
-
- /* enable new source interrupt */
- if (old_enable != s->enable[irq]) {
- trace_aspeed_intc_enable(s->enable[irq]);
- s->regs[addr] = data;
- return;
- }
-
- /* mask and unmask source interrupt */
- change = s->regs[addr] ^ data;
- if (change & data) {
- s->mask[irq] &= ~change;
- trace_aspeed_intc_unmask(change, s->mask[irq]);
- } else {
- s->mask[irq] |= change;
- trace_aspeed_intc_mask(change, s->mask[irq]);
- }
- s->regs[addr] = data;
+ aspeed_2700_intc_enable_handler(s, addr, data);
break;
case R_INTC0_GICINT128_STATUS:
case R_INTC0_GICINT129_STATUS:
@@ -213,46 +277,7 @@ static void aspeed_2700_intc0_write(void *opaque, hwaddr offset, uint64_t data,
case R_INTC0_GICINT134_STATUS:
case R_INTC0_GICINT135_STATUS:
case R_INTC0_GICINT136_STATUS:
- irq = (offset & 0x0f00) >> 8;
-
- if (irq >= aic->num_ints) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
- __func__, irq);
- return;
- }
-
- /* clear status */
- s->regs[addr] &= ~data;
-
- /*
- * These status registers are used for notify sources ISR are executed.
- * If one source ISR is executed, it will clear one bit.
- * If it clear all bits, it means to initialize this register status
- * rather than sources ISR are executed.
- */
- if (data == 0xffffffff) {
- return;
- }
-
- /* All source ISR execution are done */
- if (!s->regs[addr]) {
- trace_aspeed_intc_all_isr_done(irq);
- if (s->pending[irq]) {
- /*
- * handle pending source interrupt
- * notify firmware which source interrupt are pending
- * by setting status register
- */
- s->regs[addr] = s->pending[irq];
- s->pending[irq] = 0;
- trace_aspeed_intc_trigger_irq(irq, s->regs[addr]);
- aspeed_intc_update(s, irq, 1);
- } else {
- /* clear irq */
- trace_aspeed_intc_clear_irq(irq, 0);
- aspeed_intc_update(s, irq, 0);
- }
- }
+ aspeed_2700_intc_status_handler(s, addr, data);
break;
default:
s->regs[addr] = data;
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (4 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 05/18] hw/intc/aspeed: Introduce helper functions for enable and status registers Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-30 3:55 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Jamin Lin via
` (12 subsequent siblings)
18 siblings, 1 reply; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
The INTC0 controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC0 controller also supports GICINT192_201, mapping 1 input IRQ
pin to 10 output IRQ pins. The pin numbers for input and output are different.
Additionally, the INTC0 controller supports routing to GIC, SSP, TSP, and
BOOTMCU, making it difficult to use a formula to determine the index number of
INTC0 model supported input and output IRQs.
To simplify and improve readability, introduces the AspeedINTCIRQ structure to
save the input/output IRQ index and its enable/status register address.
Introduce the "aspeed_2700_intc0_irqs" table to store IRQ information for INTC0.
Introduce the "aspeed_intc_get_irq" function to retrieve the input/output IRQ
pin index from the provided status/enable register address.
Update the code to use "num_inpins" and "num_outpins" instead of "num_ints".
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 2 +-
hw/intc/aspeed_intc.c | 165 ++++++++++++++++++++++------------
hw/intc/trace-events | 12 +--
include/hw/intc/aspeed_intc.h | 26 ++++--
4 files changed, 135 insertions(+), 70 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index ba461fcd3c..d5e521cd38 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -520,7 +520,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_INTC0]);
/* GICINT orgates -> INTC -> GIC */
- for (i = 0; i < ic->num_ints; i++) {
+ for (i = 0; i < ic->num_inpins; i++) {
qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
qdev_get_gpio_in(DEVICE(&a->intc), i));
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 7dff5e6039..45f1c59a4b 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -34,20 +34,61 @@ REG32(INTC0_GICINT135_STATUS, 0x1704)
REG32(INTC0_GICINT136_EN, 0x1800)
REG32(INTC0_GICINT136_STATUS, 0x1804)
-#define GICINT_STATUS_BASE R_INTC0_GICINT128_STATUS
+static AspeedINTCIRQ aspeed_2700_intc0_irqs[ASPEED_INTC_MAX_INPINS] = {
+ {0, 0, 1, R_INTC0_GICINT128_EN, R_INTC0_GICINT128_STATUS},
+ {1, 1, 1, R_INTC0_GICINT129_EN, R_INTC0_GICINT129_STATUS},
+ {2, 2, 1, R_INTC0_GICINT130_EN, R_INTC0_GICINT130_STATUS},
+ {3, 3, 1, R_INTC0_GICINT131_EN, R_INTC0_GICINT131_STATUS},
+ {4, 4, 1, R_INTC0_GICINT132_EN, R_INTC0_GICINT132_STATUS},
+ {5, 5, 1, R_INTC0_GICINT133_EN, R_INTC0_GICINT133_STATUS},
+ {6, 6, 1, R_INTC0_GICINT134_EN, R_INTC0_GICINT134_STATUS},
+ {7, 7, 1, R_INTC0_GICINT135_EN, R_INTC0_GICINT135_STATUS},
+ {8, 8, 1, R_INTC0_GICINT136_EN, R_INTC0_GICINT136_STATUS},
+};
+
+static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
+ uint32_t addr)
+{
+ int i;
+
+ for (i = 0; i < aic->irq_table_count; i++) {
+ if (aic->irq_table[i].enable_addr == addr ||
+ aic->irq_table[i].status_addr == addr) {
+ return &aic->irq_table[i];
+ }
+ }
+
+ /*
+ * Invalid addr.
+ */
+ g_assert_not_reached();
+}
-static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
+/*
+ * Update the state of an interrupt controller pin by setting
+ * the specified output pin to the given level.
+ * The input pin index should be between 0 and the number of input pins.
+ * The output pin index should be between 0 and the number of output pins.
+ */
+static void aspeed_intc_update(AspeedINTCState *s, int inpin_idx,
+ int outpin_idx, int level)
{
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
- if (irq >= aic->num_ints) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
- __func__, irq);
+ if (inpin_idx >= aic->num_inpins) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid input pin index: %d\n",
+ __func__, inpin_idx);
+ return;
+ }
+
+ if (outpin_idx >= aic->num_outpins) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid output pin index: %d\n",
+ __func__, outpin_idx);
return;
}
- trace_aspeed_intc_update_irq(irq, level);
- qemu_set_irq(s->output_pins[irq], level);
+ trace_aspeed_intc_update_irq(inpin_idx, outpin_idx, level);
+ qemu_set_irq(s->output_pins[outpin_idx], level);
}
/*
@@ -56,30 +97,33 @@ static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
* The value of irq should be 0 to num_ints.
* The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on.
*/
-static void aspeed_intc_set_irq(void *opaque, int irq, int level)
+static void aspeed_intc_set_irq(void *opaque, int irq_idx, int level)
{
AspeedINTCState *s = (AspeedINTCState *)opaque;
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
- uint32_t status_addr = GICINT_STATUS_BASE + ((0x100 * irq) >> 2);
+ const AspeedINTCIRQ *irq;
uint32_t select = 0;
uint32_t enable;
int i;
- if (irq >= aic->num_ints) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
- __func__, irq);
+ if (irq_idx >= aic->num_inpins) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid input interrupt number: %d\n",
+ __func__, irq_idx);
return;
}
- trace_aspeed_intc_set_irq(irq, level);
- enable = s->enable[irq];
+ irq = &aic->irq_table[irq_idx];
+
+ trace_aspeed_intc_set_irq(irq->inpin_idx, level);
+ enable = s->enable[irq->inpin_idx];
if (!level) {
return;
}
for (i = 0; i < aic->num_lines; i++) {
- if (s->orgates[irq].levels[i]) {
+ if (s->orgates[irq->inpin_idx].levels[i]) {
if (enable & BIT(i)) {
select |= BIT(i);
}
@@ -92,7 +136,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
trace_aspeed_intc_select(select);
- if (s->mask[irq] || s->regs[status_addr]) {
+ if (s->mask[irq->inpin_idx] || s->regs[irq->status_addr]) {
/*
* a. mask is not 0 means in ISR mode
* sources interrupt routine are executing.
@@ -101,16 +145,18 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
*
* save source interrupt to pending variable.
*/
- s->pending[irq] |= select;
- trace_aspeed_intc_pending_irq(irq, s->pending[irq]);
+ s->pending[irq->inpin_idx] |= select;
+ trace_aspeed_intc_pending_irq(irq->inpin_idx,
+ s->pending[irq->inpin_idx]);
} else {
/*
* notify firmware which source interrupt are coming
* by setting status register
*/
- s->regs[status_addr] = select;
- trace_aspeed_intc_trigger_irq(irq, s->regs[status_addr]);
- aspeed_intc_update(s, irq, 1);
+ s->regs[irq->status_addr] = select;
+ trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
+ s->regs[irq->status_addr]);
+ aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
}
}
@@ -118,16 +164,16 @@ static void aspeed_2700_intc_enable_handler(AspeedINTCState *s, uint32_t addr,
uint64_t data)
{
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
- uint32_t offset = addr << 2;
+ const AspeedINTCIRQ *irq;
uint32_t old_enable;
uint32_t change;
- uint32_t irq;
- irq = (offset & 0x0f00) >> 8;
+ irq = aspeed_intc_get_irq(aic, addr);
- if (irq >= aic->num_ints) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
- __func__, irq);
+ if (irq->inpin_idx >= aic->num_inpins) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid input pin index number: %d\n",
+ __func__, irq->inpin_idx);
return;
}
@@ -138,17 +184,17 @@ static void aspeed_2700_intc_enable_handler(AspeedINTCState *s, uint32_t addr,
*/
/* disable all source interrupt */
- if (!data && !s->enable[irq]) {
+ if (!data && !s->enable[irq->inpin_idx]) {
s->regs[addr] = data;
return;
}
- old_enable = s->enable[irq];
- s->enable[irq] |= data;
+ old_enable = s->enable[irq->inpin_idx];
+ s->enable[irq->inpin_idx] |= data;
/* enable new source interrupt */
- if (old_enable != s->enable[irq]) {
- trace_aspeed_intc_enable(s->enable[irq]);
+ if (old_enable != s->enable[irq->inpin_idx]) {
+ trace_aspeed_intc_enable(s->enable[irq->inpin_idx]);
s->regs[addr] = data;
return;
}
@@ -156,11 +202,11 @@ static void aspeed_2700_intc_enable_handler(AspeedINTCState *s, uint32_t addr,
/* mask and unmask source interrupt */
change = s->regs[addr] ^ data;
if (change & data) {
- s->mask[irq] &= ~change;
- trace_aspeed_intc_unmask(change, s->mask[irq]);
+ s->mask[irq->inpin_idx] &= ~change;
+ trace_aspeed_intc_unmask(change, s->mask[irq->inpin_idx]);
} else {
- s->mask[irq] |= change;
- trace_aspeed_intc_mask(change, s->mask[irq]);
+ s->mask[irq->inpin_idx] |= change;
+ trace_aspeed_intc_mask(change, s->mask[irq->inpin_idx]);
}
s->regs[addr] = data;
}
@@ -169,19 +215,19 @@ static void aspeed_2700_intc_status_handler(AspeedINTCState *s, uint32_t addr,
uint64_t data)
{
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
- uint32_t offset = addr << 2;
- uint32_t irq;
-
- irq = (offset & 0x0f00) >> 8;
+ const AspeedINTCIRQ *irq;
if (!data) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__);
return;
}
- if (irq >= aic->num_ints) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
- __func__, irq);
+ irq = aspeed_intc_get_irq(aic, addr);
+
+ if (irq->inpin_idx >= aic->num_inpins) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid input pin index number: %d\n",
+ __func__, irq->inpin_idx);
return;
}
@@ -200,21 +246,22 @@ static void aspeed_2700_intc_status_handler(AspeedINTCState *s, uint32_t addr,
/* All source ISR execution are done */
if (!s->regs[addr]) {
- trace_aspeed_intc_all_isr_done(irq);
- if (s->pending[irq]) {
+ trace_aspeed_intc_all_isr_done(irq->inpin_idx);
+ if (s->pending[irq->inpin_idx]) {
/*
* handle pending source interrupt
* notify firmware which source interrupt are pending
* by setting status register
*/
- s->regs[addr] = s->pending[irq];
- s->pending[irq] = 0;
- trace_aspeed_intc_trigger_irq(irq, s->regs[addr]);
- aspeed_intc_update(s, irq, 1);
+ s->regs[addr] = s->pending[irq->inpin_idx];
+ s->pending[irq->inpin_idx] = 0;
+ trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
+ s->regs[addr]);
+ aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
} else {
/* clear irq */
- trace_aspeed_intc_clear_irq(irq, 0);
- aspeed_intc_update(s, irq, 0);
+ trace_aspeed_intc_clear_irq(irq->inpin_idx, irq->outpin_idx, 0);
+ aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 0);
}
}
}
@@ -301,8 +348,8 @@ static void aspeed_intc_instance_init(Object *obj)
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
int i;
- assert(aic->num_ints <= ASPEED_INTC_NR_INTS);
- for (i = 0; i < aic->num_ints; i++) {
+ assert(aic->num_inpins <= ASPEED_INTC_MAX_INPINS);
+ for (i = 0; i < aic->num_inpins; i++) {
object_initialize_child(obj, "intc-orgates[*]", &s->orgates[i],
TYPE_OR_IRQ);
object_property_set_int(OBJECT(&s->orgates[i]), "num-lines",
@@ -337,12 +384,15 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem);
- qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints);
+ qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_inpins);
- for (i = 0; i < aic->num_ints; i++) {
+ for (i = 0; i < aic->num_inpins; i++) {
if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) {
return;
}
+ }
+
+ for (i = 0; i < aic->num_outpins; i++) {
sysbus_init_irq(sbd, &s->output_pins[i]);
}
}
@@ -387,10 +437,13 @@ static void aspeed_2700_intc0_class_init(ObjectClass *klass, void *data)
dc->desc = "ASPEED 2700 INTC 0 Controller";
aic->num_lines = 32;
- aic->num_ints = 9;
+ aic->num_inpins = 9;
+ aic->num_outpins = 9;
aic->reg_ops = &aspeed_2700_intc0_ops;
aic->mem_size = 0x4000;
aic->reg_size = 0x2000;
+ aic->irq_table = aspeed_2700_intc0_irqs;
+ aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intc0_irqs);
}
static const TypeInfo aspeed_2700_intc0_info = {
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 3dcf147198..af9703e1b5 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -82,12 +82,12 @@ aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64
# aspeed_intc.c
aspeed_intc_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32
aspeed_intc_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
-aspeed_intc_set_irq(int irq, int level) "Set IRQ %d: %d"
-aspeed_intc_clear_irq(int irq, int level) "Clear IRQ %d: %d"
-aspeed_intc_update_irq(int irq, int level) "Update IRQ: %d: %d"
-aspeed_intc_pending_irq(int irq, uint32_t value) "Pending IRQ: %d: 0x%x"
-aspeed_intc_trigger_irq(int irq, uint32_t value) "Trigger IRQ: %d: 0x%x"
-aspeed_intc_all_isr_done(int irq) "All source ISR execution are done: %d"
+aspeed_intc_set_irq(int inpin_idx, int level) "Set IRQ %d: %d"
+aspeed_intc_clear_irq(int inpin_idx, int outpin_idx, int level) "Clear IRQ %d-%d: %d"
+aspeed_intc_update_irq(int inpin_idx, int outpin_idx, int level) "Update IRQ: %d-%d: %d"
+aspeed_intc_pending_irq(int inpin_idx, uint32_t value) "Pending IRQ: %d: 0x%x"
+aspeed_intc_trigger_irq(int inpin_idx, int outpin_idx, uint32_t value) "Trigger IRQ: %d-%d: 0x%x"
+aspeed_intc_all_isr_done(int inpin_idx) "All source ISR execution are done: %d"
aspeed_intc_enable(uint32_t value) "Enable: 0x%x"
aspeed_intc_select(uint32_t value) "Select: 0x%x"
aspeed_intc_mask(uint32_t change, uint32_t value) "Mask: 0x%x: 0x%x"
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index d881cb7088..73261037ea 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -17,7 +17,16 @@
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
#define ASPEED_INTC_NR_REGS (0x2000 >> 2)
-#define ASPEED_INTC_NR_INTS 9
+#define ASPEED_INTC_MAX_INPINS 9
+#define ASPEED_INTC_MAX_OUTPINS 9
+
+typedef struct AspeedINTCIRQ {
+ int inpin_idx;
+ int outpin_idx;
+ int num_outpins;
+ uint32_t enable_addr;
+ uint32_t status_addr;
+} AspeedINTCIRQ;
struct AspeedINTCState {
/*< private >*/
@@ -28,22 +37,25 @@ struct AspeedINTCState {
MemoryRegion iomem_container;
uint32_t regs[ASPEED_INTC_NR_REGS];
- OrIRQState orgates[ASPEED_INTC_NR_INTS];
- qemu_irq output_pins[ASPEED_INTC_NR_INTS];
+ OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
+ qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS];
- uint32_t enable[ASPEED_INTC_NR_INTS];
- uint32_t mask[ASPEED_INTC_NR_INTS];
- uint32_t pending[ASPEED_INTC_NR_INTS];
+ uint32_t enable[ASPEED_INTC_MAX_INPINS];
+ uint32_t mask[ASPEED_INTC_MAX_INPINS];
+ uint32_t pending[ASPEED_INTC_MAX_INPINS];
};
struct AspeedINTCClass {
SysBusDeviceClass parent_class;
uint32_t num_lines;
- uint32_t num_ints;
+ uint32_t num_inpins;
+ uint32_t num_outpins;
const MemoryRegionOps *reg_ops;
uint64_t mem_size;
uint64_t reg_size;
+ const AspeedINTCIRQ *irq_table;
+ int irq_table_count;
};
#endif /* ASPEED_INTC_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address
2025-01-21 7:04 ` [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
@ 2025-01-30 3:55 ` Andrew Jeffery
2025-02-04 9:45 ` Jamin Lin
0 siblings, 1 reply; 54+ messages in thread
From: Andrew Jeffery @ 2025-01-30 3:55 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The INTC0 controller supports GICINT128 to GICINT136, mapping 1:1 to
> input and
> output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was
> used to
> derive the IRQ index numbers.
>
> However, the INTC0 controller also supports GICINT192_201, mapping 1
> input IRQ
> pin to 10 output IRQ pins. The pin numbers for input and output are
> different.
> Additionally, the INTC0 controller supports routing to GIC, SSP, TSP,
> and
> BOOTMCU, making it difficult to use a formula to determine the index
> number of
> INTC0 model supported input and output IRQs.
It's also a bit difficult to follow, even having looked at the
datasheet. Do you mind adding some documentation with discussion and a
diagram of the components involved and the potential interrupt paths?
Further, it would be great if the documentation also described the
motivation for the interrupt chaining involving involving INT128-159,
INTM*, and GICINT192_201, GICINT208 and GICINT224. Clearly it's a
thing, but, why?
Andrew
^ permalink raw reply [flat|nested] 54+ messages in thread
* RE: [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address
2025-01-30 3:55 ` Andrew Jeffery
@ 2025-02-04 9:45 ` Jamin Lin
0 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin @ 2025-02-04 9:45 UTC (permalink / raw)
To: Andrew Jeffery, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hi Andrew,
> From: Andrew Jeffery <andrew@codeconstruct.com.au>
> Sent: Thursday, January 30, 2025 11:55 AM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
> Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel Stanley
> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ
> structure to save the irq index and register address
>
> On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> > The INTC0 controller supports GICINT128 to GICINT136, mapping 1:1 to
> > input and output IRQs 0 to 8. Previously, the formula "address &
> > 0x0f00" was used to derive the IRQ index numbers.
> >
> > However, the INTC0 controller also supports GICINT192_201, mapping 1
> > input IRQ pin to 10 output IRQ pins. The pin numbers for input and
> > output are different.
> > Additionally, the INTC0 controller supports routing to GIC, SSP, TSP,
> > and BOOTMCU, making it difficult to use a formula to determine the
> > index number of
> > INTC0 model supported input and output IRQs.
>
> It's also a bit difficult to follow, even having looked at the datasheet. Do you
> mind adding some documentation with discussion and a diagram of the
> components involved and the potential interrupt paths?
> Further, it would be great if the documentation also described the motivation
> for the interrupt chaining involving involving INT128-159, INTM*, and
> GICINT192_201, GICINT208 and GICINT224. Clearly it's a thing, but, why?
>
>
Please see my comments in patch 12.
Thanks for your review and suggestion.
Jamin
> Andrew
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (5 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Jamin Lin via
` (11 subsequent siblings)
18 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
The behavior of the INTC set IRQ is almost identical between INTC0 and INTC1.
To reduce duplicated code, introduce the `aspeed_intc_set_irq_handler` function
to handle both INTC0 and INTC1 IRQ behavior.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 56 +++++++++++++++++++++++--------------------
1 file changed, 30 insertions(+), 26 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 45f1c59a4b..8684d41ef6 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -91,11 +91,36 @@ static void aspeed_intc_update(AspeedINTCState *s, int inpin_idx,
qemu_set_irq(s->output_pins[outpin_idx], level);
}
+static void aspeed_intc_set_irq_handler(AspeedINTCState *s,
+ const AspeedINTCIRQ *irq, uint32_t select)
+{
+ if (s->mask[irq->inpin_idx] || s->regs[irq->status_addr]) {
+ /*
+ * a. mask is not 0 means in ISR mode
+ * sources interrupt routine are executing.
+ * b. status register value is not 0 means previous
+ * source interrupt does not be executed, yet.
+ *
+ * save source interrupt to pending variable.
+ */
+ s->pending[irq->inpin_idx] |= select;
+ trace_aspeed_intc_pending_irq(irq->inpin_idx,
+ s->pending[irq->inpin_idx]);
+ } else {
+ /*
+ * notify firmware which source interrupt are coming
+ * by setting status register
+ */
+ s->regs[irq->status_addr] = select;
+ trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
+ s->regs[irq->status_addr]);
+ aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
+ }
+}
+
/*
- * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804.
- * Utilize "address & 0x0f00" to get the irq and irq output pin index
- * The value of irq should be 0 to num_ints.
- * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on.
+ * GICINT128 to GICINT136 map 1:1 to input and output IRQs 0 to 8.
+ * The value of input IRQ should be between 0 and the number of inputs.
*/
static void aspeed_intc_set_irq(void *opaque, int irq_idx, int level)
{
@@ -136,28 +161,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq_idx, int level)
trace_aspeed_intc_select(select);
- if (s->mask[irq->inpin_idx] || s->regs[irq->status_addr]) {
- /*
- * a. mask is not 0 means in ISR mode
- * sources interrupt routine are executing.
- * b. status register value is not 0 means previous
- * source interrupt does not be executed, yet.
- *
- * save source interrupt to pending variable.
- */
- s->pending[irq->inpin_idx] |= select;
- trace_aspeed_intc_pending_irq(irq->inpin_idx,
- s->pending[irq->inpin_idx]);
- } else {
- /*
- * notify firmware which source interrupt are coming
- * by setting status register
- */
- s->regs[irq->status_addr] = select;
- trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
- s->regs[irq->status_addr]);
- aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
- }
+ aspeed_intc_set_irq_handler(s, irq, select);
}
static void aspeed_2700_intc_enable_handler(AspeedINTCState *s, uint32_t addr,
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (6 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 09/18] hw/intc/aspeed: Add ID to trace events for better debugging Jamin Lin via
` (10 subsequent siblings)
18 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
This update introduces support for handling multi-output IRQs in the AST2700
interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps
1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a
specific IRQ.
Implemented "aspeed_intc_set_irq_handler_multi_outpins" to handle IRQs with
multiple output pins. Introduced "aspeed_2700_intc_status_handler_multi_outpins"
for managing status registers associated with multi-output IRQs.
Added new IRQ definitions for GICINT192_201 in INTC0.
Adjusted the IRQ array to accommodate 10 input pins and 19 output pins,
aligning with the new GICINT192_201 mappings.
+------------------------------+
| INTC0 |
|inpin[0:0]--------->outpin[0] |
|inpin[0:1]|-------->outpin[1] |
|inpin[0:2]|-------->outpin[2] |
|inpin[0:3]|-------->outpin[3] |
orgates[0]+------> |inpin[0:4]|-------->outpin[4] |
|inpin[0:5]|-------->outpin[5] |
|inpin[0:6]|-------->outpin[6] |
|inpin[0:7]|-------->outpin[7] |
|inpin[0:8]|-------->outpin[8] |
|inpin[0:9]--------->outpin[9] |
| |
orgates[1]------> |inpin[1]+---------->outpin[10]|
orgates[2]|-----> |inpin[2]|---------->outpin[11]|
orgates[3]|-----> |inpin[3]|---------->outpin[12]|
orgates[4]|-----> |inpin[4]|---------->outpin[13]|
orgates[5]|-----> |inpin[5]|---------->outpin[14]|
orgates[6]|-----> |inpin[6]|---------->outpin[15]|
orgates[7]|-----> |inpin[7]|---------->outpin[16]|
orgates[8]|-----> |inpin[8]|---------->outpin[17]|
orgates[9]+-----> |inpin[9]|---------->outpin[18]|
+------------------------------+
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 137 ++++++++++++++++++++++++++++++----
hw/intc/trace-events | 1 +
include/hw/intc/aspeed_intc.h | 4 +-
3 files changed, 126 insertions(+), 16 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 8684d41ef6..2f704d6cd2 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -33,17 +33,20 @@ REG32(INTC0_GICINT135_EN, 0x1700)
REG32(INTC0_GICINT135_STATUS, 0x1704)
REG32(INTC0_GICINT136_EN, 0x1800)
REG32(INTC0_GICINT136_STATUS, 0x1804)
+REG32(INTC0_GICINT192_201_EN, 0x1B00)
+REG32(INTC0_GICINT192_201_STATUS, 0x1B04)
static AspeedINTCIRQ aspeed_2700_intc0_irqs[ASPEED_INTC_MAX_INPINS] = {
- {0, 0, 1, R_INTC0_GICINT128_EN, R_INTC0_GICINT128_STATUS},
- {1, 1, 1, R_INTC0_GICINT129_EN, R_INTC0_GICINT129_STATUS},
- {2, 2, 1, R_INTC0_GICINT130_EN, R_INTC0_GICINT130_STATUS},
- {3, 3, 1, R_INTC0_GICINT131_EN, R_INTC0_GICINT131_STATUS},
- {4, 4, 1, R_INTC0_GICINT132_EN, R_INTC0_GICINT132_STATUS},
- {5, 5, 1, R_INTC0_GICINT133_EN, R_INTC0_GICINT133_STATUS},
- {6, 6, 1, R_INTC0_GICINT134_EN, R_INTC0_GICINT134_STATUS},
- {7, 7, 1, R_INTC0_GICINT135_EN, R_INTC0_GICINT135_STATUS},
- {8, 8, 1, R_INTC0_GICINT136_EN, R_INTC0_GICINT136_STATUS},
+ {0, 0, 10, R_INTC0_GICINT192_201_EN, R_INTC0_GICINT192_201_STATUS},
+ {1, 10, 1, R_INTC0_GICINT128_EN, R_INTC0_GICINT128_STATUS},
+ {2, 11, 1, R_INTC0_GICINT129_EN, R_INTC0_GICINT129_STATUS},
+ {3, 12, 1, R_INTC0_GICINT130_EN, R_INTC0_GICINT130_STATUS},
+ {4, 13, 1, R_INTC0_GICINT131_EN, R_INTC0_GICINT131_STATUS},
+ {5, 14, 1, R_INTC0_GICINT132_EN, R_INTC0_GICINT132_STATUS},
+ {6, 15, 1, R_INTC0_GICINT133_EN, R_INTC0_GICINT133_STATUS},
+ {7, 16, 1, R_INTC0_GICINT134_EN, R_INTC0_GICINT134_STATUS},
+ {8, 17, 1, R_INTC0_GICINT135_EN, R_INTC0_GICINT135_STATUS},
+ {9, 18, 1, R_INTC0_GICINT136_EN, R_INTC0_GICINT136_STATUS},
};
static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
@@ -118,9 +121,46 @@ static void aspeed_intc_set_irq_handler(AspeedINTCState *s,
}
}
+static void aspeed_intc_set_irq_handler_multi_outpins(AspeedINTCState *s,
+ const AspeedINTCIRQ *irq, uint32_t select)
+{
+ int i;
+
+ for (i = 0; i < irq->num_outpins; i++) {
+ if (select & BIT(i)) {
+ if (s->mask[irq->inpin_idx] & BIT(i) ||
+ s->regs[irq->status_addr] & BIT(i)) {
+ /*
+ * a. mask bit is not 0 means in ISR mode sources interrupt
+ * routine are executing.
+ * b. status bit is not 0 means previous source interrupt
+ * does not be executed, yet.
+ *
+ * save source interrupt to pending bit.
+ */
+ s->pending[irq->inpin_idx] |= BIT(i);
+ trace_aspeed_intc_pending_irq(irq->inpin_idx,
+ s->pending[irq->inpin_idx]);
+ } else {
+ /*
+ * notify firmware which source interrupt are coming
+ * by setting status bit
+ */
+ s->regs[irq->status_addr] |= BIT(i);
+ trace_aspeed_intc_trigger_irq(irq->inpin_idx,
+ irq->outpin_idx + i,
+ s->regs[irq->status_addr]);
+ aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx + i, 1);
+ }
+ }
+ }
+}
+
/*
- * GICINT128 to GICINT136 map 1:1 to input and output IRQs 0 to 8.
- * The value of input IRQ should be between 0 and the number of inputs.
+ * GICINT192_201 maps 1:10 to input IRQ 0 and output IRQs 0 to 9.
+ * GICINT128 to GICINT136 map 1:1 to input IRQs 1 to 9 and output
+ * IRQs 10 to 18. The value of input IRQ should be between 0 and
+ * the number of input pins.
*/
static void aspeed_intc_set_irq(void *opaque, int irq_idx, int level)
{
@@ -161,7 +201,11 @@ static void aspeed_intc_set_irq(void *opaque, int irq_idx, int level)
trace_aspeed_intc_select(select);
- aspeed_intc_set_irq_handler(s, irq, select);
+ if (irq->num_outpins > 1) {
+ aspeed_intc_set_irq_handler_multi_outpins(s, irq, select);
+ } else {
+ aspeed_intc_set_irq_handler(s, irq, select);
+ }
}
static void aspeed_2700_intc_enable_handler(AspeedINTCState *s, uint32_t addr,
@@ -270,6 +314,67 @@ static void aspeed_2700_intc_status_handler(AspeedINTCState *s, uint32_t addr,
}
}
+static void aspeed_2700_intc_status_handler_multi_outpins(AspeedINTCState *s,
+ uint32_t addr, uint64_t data)
+{
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
+ const AspeedINTCIRQ *irq;
+ int i;
+
+ if (!data) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__);
+ return;
+ }
+
+ irq = aspeed_intc_get_irq(aic, addr);
+
+ if (irq->inpin_idx >= aic->num_inpins) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid input pin index number: %d\n",
+ __func__, irq->inpin_idx);
+ return;
+ }
+
+ /* clear status */
+ s->regs[addr] &= ~data;
+
+ /*
+ * The status registers are used for notify sources ISR are executed.
+ * If one source ISR is executed, it will clear one bit.
+ * If it clear all bits, it means to initialize this register status
+ * rather than sources ISR are executed.
+ */
+ if (data == 0xffffffff) {
+ return;
+ }
+
+ for (i = 0; i < irq->num_outpins; i++) {
+ /* All source ISR executions are done from a specific bit */
+ if (data & BIT(i)) {
+ trace_aspeed_intc_all_isr_done_bit(irq->inpin_idx, i);
+ if (s->pending[irq->inpin_idx] & BIT(i)) {
+ /*
+ * Handle pending source interrupt.
+ * Notify firmware which source interrupt is pending
+ * by setting the status bit.
+ */
+ s->regs[addr] |= BIT(i);
+ s->pending[irq->inpin_idx] &= ~BIT(i);
+ trace_aspeed_intc_trigger_irq(irq->inpin_idx,
+ irq->outpin_idx + i,
+ s->regs[addr]);
+ aspeed_intc_update(s, irq->inpin_idx,
+ irq->outpin_idx + i, 1);
+ } else {
+ /* clear irq for the specific bit */
+ trace_aspeed_intc_clear_irq(irq->inpin_idx,
+ irq->outpin_idx + i, 0);
+ aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx + i, 0);
+ }
+ }
+ }
+}
+
static uint64_t aspeed_2700_intc0_read(void *opaque, hwaddr offset,
unsigned int size)
{
@@ -317,6 +422,7 @@ static void aspeed_2700_intc0_write(void *opaque, hwaddr offset, uint64_t data,
case R_INTC0_GICINT134_EN:
case R_INTC0_GICINT135_EN:
case R_INTC0_GICINT136_EN:
+ case R_INTC0_GICINT192_201_EN:
aspeed_2700_intc_enable_handler(s, addr, data);
break;
case R_INTC0_GICINT128_STATUS:
@@ -330,6 +436,9 @@ static void aspeed_2700_intc0_write(void *opaque, hwaddr offset, uint64_t data,
case R_INTC0_GICINT136_STATUS:
aspeed_2700_intc_status_handler(s, addr, data);
break;
+ case R_INTC0_GICINT192_201_STATUS:
+ aspeed_2700_intc_status_handler_multi_outpins(s, addr, data);
+ break;
default:
s->regs[addr] = data;
break;
@@ -441,8 +550,8 @@ static void aspeed_2700_intc0_class_init(ObjectClass *klass, void *data)
dc->desc = "ASPEED 2700 INTC 0 Controller";
aic->num_lines = 32;
- aic->num_inpins = 9;
- aic->num_outpins = 9;
+ aic->num_inpins = 10;
+ aic->num_outpins = 19;
aic->reg_ops = &aspeed_2700_intc0_ops;
aic->mem_size = 0x4000;
aic->reg_size = 0x2000;
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index af9703e1b5..bcea3bf1d3 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -92,6 +92,7 @@ aspeed_intc_enable(uint32_t value) "Enable: 0x%x"
aspeed_intc_select(uint32_t value) "Select: 0x%x"
aspeed_intc_mask(uint32_t change, uint32_t value) "Mask: 0x%x: 0x%x"
aspeed_intc_unmask(uint32_t change, uint32_t value) "UnMask: 0x%x: 0x%x"
+aspeed_intc_all_isr_done_bit(int inpin_idx, int bit) "All source ISR execution are done from specific bit: %d-%d"
# arm_gic.c
gic_enable_irq(int irq) "irq %d enabled"
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 73261037ea..9280dc49d0 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -17,8 +17,8 @@
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
#define ASPEED_INTC_NR_REGS (0x2000 >> 2)
-#define ASPEED_INTC_MAX_INPINS 9
-#define ASPEED_INTC_MAX_OUTPINS 9
+#define ASPEED_INTC_MAX_INPINS 10
+#define ASPEED_INTC_MAX_OUTPINS 19
typedef struct AspeedINTCIRQ {
int inpin_idx;
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v1 09/18] hw/intc/aspeed: Add ID to trace events for better debugging
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (7 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 10/18] hw/intc/aspeed: Add Support for AST2700 INTC1 Controller Jamin Lin via
` (9 subsequent siblings)
18 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
Currently, it is difficult to recognize whether these trace events are from
INTC0 or INTC1. To make these trace events more readable, add an ID to the
INTC trace events.
Updated trace events to include the "id" field for better identification.
Updated the "AspeedINTCClass" structure to include an "id" field.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 45 ++++++++++++++++++++---------------
hw/intc/trace-events | 26 ++++++++++----------
include/hw/intc/aspeed_intc.h | 1 +
3 files changed, 40 insertions(+), 32 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 2f704d6cd2..c3b51cec6d 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -90,13 +90,15 @@ static void aspeed_intc_update(AspeedINTCState *s, int inpin_idx,
return;
}
- trace_aspeed_intc_update_irq(inpin_idx, outpin_idx, level);
+ trace_aspeed_intc_update_irq(aic->id, inpin_idx, outpin_idx, level);
qemu_set_irq(s->output_pins[outpin_idx], level);
}
static void aspeed_intc_set_irq_handler(AspeedINTCState *s,
const AspeedINTCIRQ *irq, uint32_t select)
{
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
+
if (s->mask[irq->inpin_idx] || s->regs[irq->status_addr]) {
/*
* a. mask is not 0 means in ISR mode
@@ -107,7 +109,7 @@ static void aspeed_intc_set_irq_handler(AspeedINTCState *s,
* save source interrupt to pending variable.
*/
s->pending[irq->inpin_idx] |= select;
- trace_aspeed_intc_pending_irq(irq->inpin_idx,
+ trace_aspeed_intc_pending_irq(aic->id, irq->inpin_idx,
s->pending[irq->inpin_idx]);
} else {
/*
@@ -115,7 +117,8 @@ static void aspeed_intc_set_irq_handler(AspeedINTCState *s,
* by setting status register
*/
s->regs[irq->status_addr] = select;
- trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
+ trace_aspeed_intc_trigger_irq(aic->id, irq->inpin_idx,
+ irq->outpin_idx,
s->regs[irq->status_addr]);
aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
}
@@ -124,6 +127,7 @@ static void aspeed_intc_set_irq_handler(AspeedINTCState *s,
static void aspeed_intc_set_irq_handler_multi_outpins(AspeedINTCState *s,
const AspeedINTCIRQ *irq, uint32_t select)
{
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
int i;
for (i = 0; i < irq->num_outpins; i++) {
@@ -139,7 +143,7 @@ static void aspeed_intc_set_irq_handler_multi_outpins(AspeedINTCState *s,
* save source interrupt to pending bit.
*/
s->pending[irq->inpin_idx] |= BIT(i);
- trace_aspeed_intc_pending_irq(irq->inpin_idx,
+ trace_aspeed_intc_pending_irq(aic->id, irq->inpin_idx,
s->pending[irq->inpin_idx]);
} else {
/*
@@ -147,7 +151,7 @@ static void aspeed_intc_set_irq_handler_multi_outpins(AspeedINTCState *s,
* by setting status bit
*/
s->regs[irq->status_addr] |= BIT(i);
- trace_aspeed_intc_trigger_irq(irq->inpin_idx,
+ trace_aspeed_intc_trigger_irq(aic->id, irq->inpin_idx,
irq->outpin_idx + i,
s->regs[irq->status_addr]);
aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx + i, 1);
@@ -180,7 +184,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq_idx, int level)
irq = &aic->irq_table[irq_idx];
- trace_aspeed_intc_set_irq(irq->inpin_idx, level);
+ trace_aspeed_intc_set_irq(aic->id, irq->inpin_idx, level);
enable = s->enable[irq->inpin_idx];
if (!level) {
@@ -199,7 +203,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq_idx, int level)
return;
}
- trace_aspeed_intc_select(select);
+ trace_aspeed_intc_select(aic->id, select);
if (irq->num_outpins > 1) {
aspeed_intc_set_irq_handler_multi_outpins(s, irq, select);
@@ -242,7 +246,7 @@ static void aspeed_2700_intc_enable_handler(AspeedINTCState *s, uint32_t addr,
/* enable new source interrupt */
if (old_enable != s->enable[irq->inpin_idx]) {
- trace_aspeed_intc_enable(s->enable[irq->inpin_idx]);
+ trace_aspeed_intc_enable(aic->id, s->enable[irq->inpin_idx]);
s->regs[addr] = data;
return;
}
@@ -251,10 +255,10 @@ static void aspeed_2700_intc_enable_handler(AspeedINTCState *s, uint32_t addr,
change = s->regs[addr] ^ data;
if (change & data) {
s->mask[irq->inpin_idx] &= ~change;
- trace_aspeed_intc_unmask(change, s->mask[irq->inpin_idx]);
+ trace_aspeed_intc_unmask(aic->id, change, s->mask[irq->inpin_idx]);
} else {
s->mask[irq->inpin_idx] |= change;
- trace_aspeed_intc_mask(change, s->mask[irq->inpin_idx]);
+ trace_aspeed_intc_mask(aic->id, change, s->mask[irq->inpin_idx]);
}
s->regs[addr] = data;
}
@@ -294,7 +298,7 @@ static void aspeed_2700_intc_status_handler(AspeedINTCState *s, uint32_t addr,
/* All source ISR execution are done */
if (!s->regs[addr]) {
- trace_aspeed_intc_all_isr_done(irq->inpin_idx);
+ trace_aspeed_intc_all_isr_done(aic->id, irq->inpin_idx);
if (s->pending[irq->inpin_idx]) {
/*
* handle pending source interrupt
@@ -303,12 +307,13 @@ static void aspeed_2700_intc_status_handler(AspeedINTCState *s, uint32_t addr,
*/
s->regs[addr] = s->pending[irq->inpin_idx];
s->pending[irq->inpin_idx] = 0;
- trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
- s->regs[addr]);
+ trace_aspeed_intc_trigger_irq(aic->id, irq->inpin_idx,
+ irq->outpin_idx, s->regs[addr]);
aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
} else {
/* clear irq */
- trace_aspeed_intc_clear_irq(irq->inpin_idx, irq->outpin_idx, 0);
+ trace_aspeed_intc_clear_irq(aic->id, irq->inpin_idx,
+ irq->outpin_idx, 0);
aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 0);
}
}
@@ -351,7 +356,7 @@ static void aspeed_2700_intc_status_handler_multi_outpins(AspeedINTCState *s,
for (i = 0; i < irq->num_outpins; i++) {
/* All source ISR executions are done from a specific bit */
if (data & BIT(i)) {
- trace_aspeed_intc_all_isr_done_bit(irq->inpin_idx, i);
+ trace_aspeed_intc_all_isr_done_bit(aic->id, irq->inpin_idx, i);
if (s->pending[irq->inpin_idx] & BIT(i)) {
/*
* Handle pending source interrupt.
@@ -360,14 +365,15 @@ static void aspeed_2700_intc_status_handler_multi_outpins(AspeedINTCState *s,
*/
s->regs[addr] |= BIT(i);
s->pending[irq->inpin_idx] &= ~BIT(i);
- trace_aspeed_intc_trigger_irq(irq->inpin_idx,
+ trace_aspeed_intc_trigger_irq(aic->id,
+ irq->inpin_idx,
irq->outpin_idx + i,
s->regs[addr]);
aspeed_intc_update(s, irq->inpin_idx,
irq->outpin_idx + i, 1);
} else {
/* clear irq for the specific bit */
- trace_aspeed_intc_clear_irq(irq->inpin_idx,
+ trace_aspeed_intc_clear_irq(aic->id, irq->inpin_idx,
irq->outpin_idx + i, 0);
aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx + i, 0);
}
@@ -391,7 +397,7 @@ static uint64_t aspeed_2700_intc0_read(void *opaque, hwaddr offset,
}
value = s->regs[addr];
- trace_aspeed_intc_read(offset, size, value);
+ trace_aspeed_intc_read(aic->id, offset, size, value);
return value;
}
@@ -410,7 +416,7 @@ static void aspeed_2700_intc0_write(void *opaque, hwaddr offset, uint64_t data,
return;
}
- trace_aspeed_intc_write(offset, size, data);
+ trace_aspeed_intc_write(aic->id, offset, size, data);
switch (addr) {
case R_INTC0_GICINT128_EN:
@@ -557,6 +563,7 @@ static void aspeed_2700_intc0_class_init(ObjectClass *klass, void *data)
aic->reg_size = 0x2000;
aic->irq_table = aspeed_2700_intc0_irqs;
aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intc0_irqs);
+ aic->id = 0;
}
static const TypeInfo aspeed_2700_intc0_info = {
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index bcea3bf1d3..a320b542d3 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -80,19 +80,19 @@ aspeed_vic_update_irq(int flags) "Raising IRQ: %d"
aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32
aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
# aspeed_intc.c
-aspeed_intc_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32
-aspeed_intc_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
-aspeed_intc_set_irq(int inpin_idx, int level) "Set IRQ %d: %d"
-aspeed_intc_clear_irq(int inpin_idx, int outpin_idx, int level) "Clear IRQ %d-%d: %d"
-aspeed_intc_update_irq(int inpin_idx, int outpin_idx, int level) "Update IRQ: %d-%d: %d"
-aspeed_intc_pending_irq(int inpin_idx, uint32_t value) "Pending IRQ: %d: 0x%x"
-aspeed_intc_trigger_irq(int inpin_idx, int outpin_idx, uint32_t value) "Trigger IRQ: %d-%d: 0x%x"
-aspeed_intc_all_isr_done(int inpin_idx) "All source ISR execution are done: %d"
-aspeed_intc_enable(uint32_t value) "Enable: 0x%x"
-aspeed_intc_select(uint32_t value) "Select: 0x%x"
-aspeed_intc_mask(uint32_t change, uint32_t value) "Mask: 0x%x: 0x%x"
-aspeed_intc_unmask(uint32_t change, uint32_t value) "UnMask: 0x%x: 0x%x"
-aspeed_intc_all_isr_done_bit(int inpin_idx, int bit) "All source ISR execution are done from specific bit: %d-%d"
+aspeed_intc_read(int id, uint64_t offset, unsigned size, uint32_t value) "%d: From 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_intc_write(int id, uint64_t offset, unsigned size, uint32_t data) "%d: To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_intc_set_irq(int id, int inpin_idx, int level) "%d: Set IRQ %d: %d"
+aspeed_intc_clear_irq(int id, int inpin_idx, int outpin_idx, int level) "%d: Clear IRQ %d-%d: %d"
+aspeed_intc_update_irq(int id, int inpin_idx, int outpin_idx, int level) "%d: Update IRQ: %d-%d: %d"
+aspeed_intc_pending_irq(int id, int inpin_idx, uint32_t value) "%d: Pending IRQ: %d: 0x%x"
+aspeed_intc_trigger_irq(int id, int inpin_idx, int outpin_idx, uint32_t value) "%d: Trigger IRQ: %d-%d: 0x%x"
+aspeed_intc_all_isr_done(int id, int inpin_idx) "%d: All source ISR execution are done: %d"
+aspeed_intc_enable(int id, uint32_t value) "%d: Enable: 0x%x"
+aspeed_intc_select(int id, uint32_t value) "%d: Select: 0x%x"
+aspeed_intc_mask(int id, uint32_t change, uint32_t value) "%d: Mask: 0x%x: 0x%x"
+aspeed_intc_unmask(int id, uint32_t change, uint32_t value) "%d: UnMask: 0x%x: 0x%x"
+aspeed_intc_all_isr_done_bit(int id, int inpin_idx, int bit) "%d: All source ISR execution are done from specific bit: %d-%d"
# arm_gic.c
gic_enable_irq(int irq) "irq %d enabled"
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 9280dc49d0..c2e3906d99 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -56,6 +56,7 @@ struct AspeedINTCClass {
uint64_t reg_size;
const AspeedINTCIRQ *irq_table;
int irq_table_count;
+ int id;
};
#endif /* ASPEED_INTC_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v1 10/18] hw/intc/aspeed: Add Support for AST2700 INTC1 Controller
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (8 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 09/18] hw/intc/aspeed: Add ID to trace events for better debugging Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
` (8 subsequent siblings)
18 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
Introduce a new ast2700 INTC1 class to support AST2700 INTC1.
Added new register definitions for INTC1, including enable and status registers
for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTC1, supporting six input pins and six
output pins, aligning with the newly defined registers.
Implemented "aspeed_2700_intc1_read" and "aspeed_2700_intc1_write" to handle
INTC1-specific register access.
+--------------------------+
| INTC1 |
| |
orgates[0]+----> |inpin[0]+------->outpin[0]|
orgates[1]|----> |inpin[1]|------->outpin[1]|
orgates[2]|----> |inpin[2]|------->outpin[2]|
orgates[3]|----> |inpin[3]|------->outpin[3]|
orgates[4]|----> |inpin[4]|------->outpin[4]|
orgates[5]+----> |inpin[5]+------->outpin[5]|
| |
+--------------------------+
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 119 ++++++++++++++++++++++++++++++++++
include/hw/intc/aspeed_intc.h | 1 +
2 files changed, 120 insertions(+)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index c3b51cec6d..1db5e5a94d 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -36,6 +36,20 @@ REG32(INTC0_GICINT136_STATUS, 0x1804)
REG32(INTC0_GICINT192_201_EN, 0x1B00)
REG32(INTC0_GICINT192_201_STATUS, 0x1B04)
+/* AST2700 INTC1 Registers */
+REG32(INTC1_GICINT192_EN, 0x100)
+REG32(INTC1_GICINT192_STATUS, 0x104)
+REG32(INTC1_GICINT193_EN, 0x110)
+REG32(INTC1_GICINT193_STATUS, 0x114)
+REG32(INTC1_GICINT194_EN, 0x120)
+REG32(INTC1_GICINT194_STATUS, 0x124)
+REG32(INTC1_GICINT195_EN, 0x130)
+REG32(INTC1_GICINT195_STATUS, 0x134)
+REG32(INTC1_GICINT196_EN, 0x140)
+REG32(INTC1_GICINT196_STATUS, 0x144)
+REG32(INTC1_GICINT197_EN, 0x150)
+REG32(INTC1_GICINT197_STATUS, 0x154)
+
static AspeedINTCIRQ aspeed_2700_intc0_irqs[ASPEED_INTC_MAX_INPINS] = {
{0, 0, 10, R_INTC0_GICINT192_201_EN, R_INTC0_GICINT192_201_STATUS},
{1, 10, 1, R_INTC0_GICINT128_EN, R_INTC0_GICINT128_STATUS},
@@ -49,6 +63,15 @@ static AspeedINTCIRQ aspeed_2700_intc0_irqs[ASPEED_INTC_MAX_INPINS] = {
{9, 18, 1, R_INTC0_GICINT136_EN, R_INTC0_GICINT136_STATUS},
};
+static AspeedINTCIRQ aspeed_2700_intc1_irqs[ASPEED_INTC_MAX_INPINS] = {
+ {0, 0, 1, R_INTC1_GICINT192_EN, R_INTC1_GICINT192_STATUS},
+ {1, 1, 1, R_INTC1_GICINT193_EN, R_INTC1_GICINT193_STATUS},
+ {2, 2, 1, R_INTC1_GICINT194_EN, R_INTC1_GICINT194_STATUS},
+ {3, 3, 1, R_INTC1_GICINT195_EN, R_INTC1_GICINT195_STATUS},
+ {4, 4, 1, R_INTC1_GICINT196_EN, R_INTC1_GICINT196_STATUS},
+ {5, 5, 1, R_INTC1_GICINT197_EN, R_INTC1_GICINT197_STATUS},
+};
+
static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
uint32_t addr)
{
@@ -453,6 +476,68 @@ static void aspeed_2700_intc0_write(void *opaque, hwaddr offset, uint64_t data,
return;
}
+static uint64_t aspeed_2700_intc1_read(void *opaque, hwaddr offset,
+ unsigned int size)
+{
+ AspeedINTCState *s = ASPEED_INTC(opaque);
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
+ uint32_t addr = offset >> 2;
+ uint32_t value = 0;
+
+ if (offset >= aic->reg_size) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return 0;
+ }
+
+ value = s->regs[addr];
+ trace_aspeed_intc_read(aic->id, offset, size, value);
+
+ return value;
+}
+
+static void aspeed_2700_intc1_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size)
+{
+ AspeedINTCState *s = ASPEED_INTC(opaque);
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
+ uint32_t addr = offset >> 2;
+
+ if (offset >= aic->reg_size) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return;
+ }
+
+ trace_aspeed_intc_write(aic->id, offset, size, data);
+
+ switch (addr) {
+ case R_INTC1_GICINT192_EN:
+ case R_INTC1_GICINT193_EN:
+ case R_INTC1_GICINT194_EN:
+ case R_INTC1_GICINT195_EN:
+ case R_INTC1_GICINT196_EN:
+ case R_INTC1_GICINT197_EN:
+ aspeed_2700_intc_enable_handler(s, addr, data);
+ break;
+ case R_INTC1_GICINT192_STATUS:
+ case R_INTC1_GICINT193_STATUS:
+ case R_INTC1_GICINT194_STATUS:
+ case R_INTC1_GICINT195_STATUS:
+ case R_INTC1_GICINT196_STATUS:
+ case R_INTC1_GICINT197_STATUS:
+ aspeed_2700_intc_status_handler(s, addr, data);
+ break;
+ default:
+ s->regs[addr] = data;
+ break;
+ }
+
+ return;
+}
+
static const MemoryRegionOps aspeed_intc_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
@@ -572,10 +657,44 @@ static const TypeInfo aspeed_2700_intc0_info = {
.class_init = aspeed_2700_intc0_class_init,
};
+static const MemoryRegionOps aspeed_2700_intc1_ops = {
+ .read = aspeed_2700_intc1_read,
+ .write = aspeed_2700_intc1_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
+static void aspeed_2700_intc1_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 INTC 1 Controller";
+ aic->num_lines = 32;
+ aic->num_inpins = 6;
+ aic->num_outpins = 6;
+ aic->mem_size = 0x400;
+ aic->reg_size = 0x3d8;
+ aic->reg_ops = &aspeed_2700_intc1_ops;
+ aic->irq_table = aspeed_2700_intc1_irqs;
+ aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intc1_irqs);
+ aic->id = 1;
+}
+
+static const TypeInfo aspeed_2700_intc1_info = {
+ .name = TYPE_ASPEED_2700_INTC1,
+ .parent = TYPE_ASPEED_INTC,
+ .class_init = aspeed_2700_intc1_class_init,
+};
+
static void aspeed_intc_register_types(void)
{
type_register_static(&aspeed_intc_info);
type_register_static(&aspeed_2700_intc0_info);
+ type_register_static(&aspeed_2700_intc1_info);
}
type_init(aspeed_intc_register_types);
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index c2e3906d99..7f500927a1 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -14,6 +14,7 @@
#define TYPE_ASPEED_INTC "aspeed.intc"
#define TYPE_ASPEED_2700_INTC0 TYPE_ASPEED_INTC "0" "-ast2700"
+#define TYPE_ASPEED_2700_INTC1 TYPE_ASPEED_INTC "1" "-ast2700"
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
#define ASPEED_INTC_NR_REGS (0x2000 >> 2)
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (9 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 10/18] hw/intc/aspeed: Add Support for AST2700 INTC1 Controller Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-30 4:05 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
` (7 subsequent siblings)
18 siblings, 1 reply; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV to
identify the A1 silicon revisions.
Update "aspeed_ast2700_scu_reset" to set the silicon_rev field in the SCU
registers.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 3 +++
include/hw/misc/aspeed_scu.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index bac1441b06..f049a9fd96 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -559,6 +559,8 @@ static uint32_t aspeed_silicon_revs[] = {
AST2700_A0_SILICON_REV,
AST2720_A0_SILICON_REV,
AST2750_A0_SILICON_REV,
+ AST2700_A1_SILICON_REV,
+ AST2750_A1_SILICON_REV,
};
bool is_supported_silicon_rev(uint32_t silicon_rev)
@@ -938,6 +940,7 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
memcpy(s->regs, asc->resets, asc->nr_regs * 4);
+ s->regs[AST2700_SILICON_REV] = s->silicon_rev;
}
static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 356be95e45..684b48b722 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -54,6 +54,8 @@ struct AspeedSCUState {
#define AST2700_A0_SILICON_REV 0x06000103U
#define AST2720_A0_SILICON_REV 0x06000203U
#define AST2750_A0_SILICON_REV 0x06000003U
+#define AST2700_A1_SILICON_REV 0x06010103U
+#define AST2750_A1_SILICON_REV 0x06010003U
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions
2025-01-21 7:04 ` [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
@ 2025-01-30 4:05 ` Andrew Jeffery
2025-02-04 7:23 ` Jamin Lin
0 siblings, 1 reply; 54+ messages in thread
From: Andrew Jeffery @ 2025-01-30 4:05 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> Added new definitions for AST2700_A1_SILICON_REV and
> AST2750_A1_SILICON_REV to
> identify the A1 silicon revisions.
>
> Update "aspeed_ast2700_scu_reset" to set the silicon_rev field in the
> SCU
> registers.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> hw/misc/aspeed_scu.c | 3 +++
> include/hw/misc/aspeed_scu.h | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> index bac1441b06..f049a9fd96 100644
> --- a/hw/misc/aspeed_scu.c
> +++ b/hw/misc/aspeed_scu.c
> @@ -559,6 +559,8 @@ static uint32_t aspeed_silicon_revs[] = {
> AST2700_A0_SILICON_REV,
> AST2720_A0_SILICON_REV,
> AST2750_A0_SILICON_REV,
> + AST2700_A1_SILICON_REV,
> + AST2750_A1_SILICON_REV,
> };
>
> bool is_supported_silicon_rev(uint32_t silicon_rev)
> @@ -938,6 +940,7 @@ static void aspeed_ast2700_scu_reset(DeviceState
> *dev)
> AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
>
> memcpy(s->regs, asc->resets, asc->nr_regs * 4);
> + s->regs[AST2700_SILICON_REV] = s->silicon_rev;
Has s->silicon_rev been set?
Should we now remove the AST2700_SILICON_REV entry from asc->resets?
This seems like a fix regardless. Perhaps separate it from the addition
of the new silicon IDs?
> }
>
> static void aspeed_2700_scu_class_init(ObjectClass *klass, void
> *data)
> diff --git a/include/hw/misc/aspeed_scu.h
> b/include/hw/misc/aspeed_scu.h
> index 356be95e45..684b48b722 100644
> --- a/include/hw/misc/aspeed_scu.h
> +++ b/include/hw/misc/aspeed_scu.h
> @@ -54,6 +54,8 @@ struct AspeedSCUState {
> #define AST2700_A0_SILICON_REV 0x06000103U
> #define AST2720_A0_SILICON_REV 0x06000203U
> #define AST2750_A0_SILICON_REV 0x06000003U
> +#define AST2700_A1_SILICON_REV 0x06010103U
> +#define AST2750_A1_SILICON_REV 0x06010003U
These look fine.
Andrew
>
> #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) ==
> 0x04)
>
^ permalink raw reply [flat|nested] 54+ messages in thread* RE: [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions
2025-01-30 4:05 ` Andrew Jeffery
@ 2025-02-04 7:23 ` Jamin Lin
2025-02-04 7:29 ` Cédric Le Goater
0 siblings, 1 reply; 54+ messages in thread
From: Jamin Lin @ 2025-02-04 7:23 UTC (permalink / raw)
To: Andrew Jeffery, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hi Andrew,
> From: Andrew Jeffery <andrew@codeconstruct.com.au>
> Sent: Thursday, January 30, 2025 12:05 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
> Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel Stanley
> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for
> AST2700/AST2750 A1 Silicon Revisions
>
> On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> > Added new definitions for AST2700_A1_SILICON_REV and
> > AST2750_A1_SILICON_REV to identify the A1 silicon revisions.
> >
> > Update "aspeed_ast2700_scu_reset" to set the silicon_rev field in the
> > SCU registers.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> > hw/misc/aspeed_scu.c | 3 +++
> > include/hw/misc/aspeed_scu.h | 2 ++
> > 2 files changed, 5 insertions(+)
> >
> > diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index
> > bac1441b06..f049a9fd96 100644
> > --- a/hw/misc/aspeed_scu.c
> > +++ b/hw/misc/aspeed_scu.c
> > @@ -559,6 +559,8 @@ static uint32_t aspeed_silicon_revs[] = {
> > AST2700_A0_SILICON_REV,
> > AST2720_A0_SILICON_REV,
> > AST2750_A0_SILICON_REV,
> > + AST2700_A1_SILICON_REV,
> > + AST2750_A1_SILICON_REV,
> > };
> >
> > bool is_supported_silicon_rev(uint32_t silicon_rev) @@ -938,6 +940,7
> > @@ static void aspeed_ast2700_scu_reset(DeviceState
> > *dev)
> > AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
> >
> > memcpy(s->regs, asc->resets, asc->nr_regs * 4);
> > + s->regs[AST2700_SILICON_REV] = s->silicon_rev;
>
> Has s->silicon_rev been set?
>
> Should we now remove the AST2700_SILICON_REV entry from asc->resets?
>
The value of s->silicon_rev is set at the SoC layer.
If we remove this line, the system will display " UnKnow-SOC".
> This seems like a fix regardless. Perhaps separate it from the addition of the
> new silicon IDs?
>
Yes, I noticed that s->silicon_rev cannot be set at the SOC layer.
For example: I am unable to set silicon_rev for AST2700 A0 and A1 in hw/arm/aspeed_ast27x0.c.
I will split this into two separate patches.
One patch to fix silicon_rev and another patch for A1 silicon revision definition.
Thanks-Jamin
> > }
> >
> > static void aspeed_2700_scu_class_init(ObjectClass *klass, void
> > *data)
> > diff --git a/include/hw/misc/aspeed_scu.h
> > b/include/hw/misc/aspeed_scu.h index 356be95e45..684b48b722 100644
> > --- a/include/hw/misc/aspeed_scu.h
> > +++ b/include/hw/misc/aspeed_scu.h
> > @@ -54,6 +54,8 @@ struct AspeedSCUState {
> > #define AST2700_A0_SILICON_REV 0x06000103U
> > #define AST2720_A0_SILICON_REV 0x06000203U
> > #define AST2750_A0_SILICON_REV 0x06000003U
> > +#define AST2700_A1_SILICON_REV 0x06010103U #define
> > +AST2750_A1_SILICON_REV 0x06010003U
>
> These look fine.
>
> Andrew
>
> >
> > #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) ==
> > 0x04)
> >
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions
2025-02-04 7:23 ` Jamin Lin
@ 2025-02-04 7:29 ` Cédric Le Goater
0 siblings, 0 replies; 54+ messages in thread
From: Cédric Le Goater @ 2025-02-04 7:29 UTC (permalink / raw)
To: Jamin Lin, Andrew Jeffery, Peter Maydell, Steven Lee, Troy Lee,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hello Jamin,
>>> --- a/hw/misc/aspeed_scu.c
>>> +++ b/hw/misc/aspeed_scu.c
>>> @@ -559,6 +559,8 @@ static uint32_t aspeed_silicon_revs[] = {
>>> AST2700_A0_SILICON_REV,
>>> AST2720_A0_SILICON_REV,
>>> AST2750_A0_SILICON_REV,
>>> + AST2700_A1_SILICON_REV,
>>> + AST2750_A1_SILICON_REV,
>>> };
>>>
>>> bool is_supported_silicon_rev(uint32_t silicon_rev) @@ -938,6 +940,7
>>> @@ static void aspeed_ast2700_scu_reset(DeviceState
>>> *dev)
>>> AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
>>>
>>> memcpy(s->regs, asc->resets, asc->nr_regs * 4);
>>> + s->regs[AST2700_SILICON_REV] = s->silicon_rev;
>>
>> Has s->silicon_rev been set?
>>
>> Should we now remove the AST2700_SILICON_REV entry from asc->resets?
>>
> The value of s->silicon_rev is set at the SoC layer.
> If we remove this line, the system will display " UnKnow-SOC".
>
>> This seems like a fix regardless. Perhaps separate it from the addition of the
>> new silicon IDs?
>>
> Yes, I noticed that s->silicon_rev cannot be set at the SOC layer.
> For example: I am unable to set silicon_rev for AST2700 A0 and A1 in hw/arm/aspeed_ast27x0.c.
> I will split this into two separate patches.
> One patch to fix silicon_rev and another patch for A1 silicon revision definition.
Is the AST2700 SoC different from the other SoCs AST 2[456]00 ?
If not please check the _scu_reset routines.
Thanks,
C.
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (10 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-30 4:19 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 13/18] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin Lin via
` (6 subsequent siblings)
18 siblings, 1 reply; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
The design of INTC controllers has significantly changed in AST2700 A1.
There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged every
32 sources for interrupt numbers greater than 127.
There are two levels of interrupt controllers, INTC0 and INTC1. The interrupt
sources of INTC0 are the interrupt numbers from INTC_0 to INTC_127 and
interrupts from INTC1. The interrupt sources of INTC1 are the interrupt numbers
greater than INTC_127. INTC1 controls the interrupts INTC_128 to INTC_319 only.
Currently, only GIC 192 to 201 are supported, and their source interrupts are
from INTC1 and connected to INTC0 at input pin 0 and output pins 0 to 9 for
GIC 192-201.
To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and output pins
10 to 18 remain to support GIC 128-136, which source interrupts from INTC0.
These will be removed if we decide not to support AST2700 A0 in the future.
+---------------------------------------------------------------------------------------+
| AST2700 A1 Design |
| |
| +--------------------------+ |
| | INTC1 | +---------------+ |
| | | | orgates[0] | |
| orgates[0]+----> |inpin[0]+------->outpin[0]+------> | 0 | |
| orgates[1]|----> |inpin[1]|------->outpin[1]|------> | 1 0-31 bits +--+ |
| orgates[2]|----> |inpin[2]|------->outpin[2]|------> | 2 | | |
| orgates[3]|----> |inpin[3]|------->outpin[3]|------> | 3 | | |
| orgates[4]|----> |inpin[4]|------->outpin[4]|------> | 4 | | |
| orgates[5]+----> |inpin[5]+------->outpin[5]+------> | 5 | | |
| | | |---------------| | |
| +--------------------------+ | |
| +-----------------------------------------------------------------------| |
| | |
| | |
| | +------------------------------+ +-----------------+ |
| | | INTC0 | | GIC | |
| | |inpin[0:0]--------->outpin[0] +---------> |192 | |
| | |inpin[0:1]|-------->outpin[1] |---------> |193 | |
| | |inpin[0:2]|-------->outpin[2] |---------> |194 | |
| | |inpin[0:3]|-------->outpin[3] |---------> |195 | |
| >--------------> |inpin[0:4]|-------->outpin[4] |---------> |196 | |
| |inpin[0:5]|-------->outpin[5] |---------> |197 | |
| |inpin[0:6]|-------->outpin[6] |---------> |198 | |
| |inpin[0:7]|-------->outpin[7] |---------> |199 | |
| |inpin[0:8]|-------->outpin[8] |---------> |200 | |
| |inpin[0:9]|-------->outpin[9] |---------> |201 | |
+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------+
| orgates[1]|-----> |inpin[1]|---------->outpin[10]|---------> |128 | |
| orgates[2]|-----> |inpin[2]|---------->outpin[11]|---------> |129 | |
| orgates[3]|-----> |inpin[3]|---------->outpin[12]|---------> |130 | |
| orgates[4]|-----> |inpin[4]|---------->outpin[13]|---------> |131 | |
| orgates[5]|-----> |inpin[5]|---------->outpin[14]|---------> |132 | |
| orgates[6]|-----> |inpin[6]|---------->outpin[15]|---------> |133 | |
| orgates[7]|-----> |inpin[7]|---------->outpin[16]|---------> |134 | |
| orgates[8]|-----> |inpin[8]|---------->outpin[17]|---------> |135 | |
| orgates[9]+-----> |inpin[9]|---------->outpin[18]+---------> |136 | |
| +------------------------------+ +-----------------+ |
| |
| AST2700 A0 Design |
| |
+---------------------------------------------------------------------------------------+
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 126 +++++++++++++++++++++++++-----------
include/hw/arm/aspeed_soc.h | 3 +-
2 files changed, 92 insertions(+), 37 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index d5e521cd38..a95fed30cf 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -67,6 +67,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_RTC] = 0x12C0F000,
[ASPEED_DEV_SDHCI] = 0x14080000,
[ASPEED_DEV_TIMER1] = 0x12C10000,
+ [ASPEED_DEV_INTC1] = 0x14C18000,
};
#define AST2700_MAX_IRQ 256
@@ -119,21 +120,27 @@ static const int aspeed_soc_ast2700_irqmap[] = {
};
/* GICINT 128 */
-static const int aspeed_soc_ast2700_gic128_intcmap[] = {
+/* GICINT 192 */
+static const int ast2700_gic128_gic192_intcmap[] = {
[ASPEED_DEV_LPC] = 0,
[ASPEED_DEV_IBT] = 2,
[ASPEED_DEV_KCS] = 4,
};
+/* GICINT 129 */
+/* GICINT 193 */
+
/* GICINT 130 */
-static const int aspeed_soc_ast2700_gic130_intcmap[] = {
+/* GICINT 194 */
+static const int ast2700_gic130_gic194_intcmap[] = {
[ASPEED_DEV_I2C] = 0,
[ASPEED_DEV_ADC] = 16,
[ASPEED_DEV_GPIO] = 18,
};
/* GICINT 131 */
-static const int aspeed_soc_ast2700_gic131_intcmap[] = {
+/* GICINT 195 */
+static const int ast2700_gic131_gic195_intcmap[] = {
[ASPEED_DEV_I3C] = 0,
[ASPEED_DEV_WDT] = 16,
[ASPEED_DEV_FMC] = 25,
@@ -141,7 +148,8 @@ static const int aspeed_soc_ast2700_gic131_intcmap[] = {
};
/* GICINT 132 */
-static const int aspeed_soc_ast2700_gic132_intcmap[] = {
+/* GICINT 196 */
+static const int ast2700_gic132_gic196_intcmap[] = {
[ASPEED_DEV_ETH1] = 0,
[ASPEED_DEV_ETH2] = 1,
[ASPEED_DEV_ETH3] = 2,
@@ -160,40 +168,58 @@ static const int aspeed_soc_ast2700_gic132_intcmap[] = {
};
/* GICINT 133 */
-static const int aspeed_soc_ast2700_gic133_intcmap[] = {
+/* GICINT 197 */
+static const int ast2700_gic133_gic197_intcmap[] = {
[ASPEED_DEV_SDHCI] = 1,
[ASPEED_DEV_PECI] = 4,
};
/* GICINT 128 ~ 136 */
+/* GICINT 192 ~ 201 */
struct gic_intc_irq_info {
int irq;
+ int intc_idx;
+ int orgate_idx;
const int *ptr;
};
-static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = {
- {128, aspeed_soc_ast2700_gic128_intcmap},
- {129, NULL},
- {130, aspeed_soc_ast2700_gic130_intcmap},
- {131, aspeed_soc_ast2700_gic131_intcmap},
- {132, aspeed_soc_ast2700_gic132_intcmap},
- {133, aspeed_soc_ast2700_gic133_intcmap},
- {134, NULL},
- {135, NULL},
- {136, NULL},
+static struct gic_intc_irq_info ast2700_gic_intcmap[] = {
+ {192, 1, 0, ast2700_gic128_gic192_intcmap},
+ {193, 1, 1, NULL},
+ {194, 1, 2, ast2700_gic130_gic194_intcmap},
+ {195, 1, 3, ast2700_gic131_gic195_intcmap},
+ {196, 1, 4, ast2700_gic132_gic196_intcmap},
+ {197, 1, 5, ast2700_gic133_gic197_intcmap},
+ {198, 1, 6, NULL},
+ {199, 1, 7, NULL},
+ {200, 1, 8, NULL},
+ {201, 1, 9, NULL},
+ {128, 0, 1, ast2700_gic128_gic192_intcmap},
+ {129, 0, 2, NULL},
+ {130, 0, 3, ast2700_gic130_gic194_intcmap},
+ {131, 0, 4, ast2700_gic131_gic195_intcmap},
+ {132, 0, 5, ast2700_gic132_gic196_intcmap},
+ {133, 0, 6, ast2700_gic133_gic197_intcmap},
+ {134, 0, 7, NULL},
+ {135, 0, 8, NULL},
+ {136, 0, 9, NULL},
};
static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
{
Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int or_idx;
+ int idx;
int i;
- for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
- if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
- assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
- return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
- aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]);
+ for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
+ if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
+ assert(ast2700_gic_intcmap[i].ptr);
+ or_idx = ast2700_gic_intcmap[i].orgate_idx;
+ idx = ast2700_gic_intcmap[i].intc_idx;
+ return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
+ ast2700_gic_intcmap[i].ptr[dev]);
}
}
@@ -205,13 +231,17 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
{
Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int or_idx;
+ int idx;
int i;
- for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
- if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
- assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
- return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
- aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index);
+ for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
+ if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
+ assert(ast2700_gic_intcmap[i].ptr);
+ or_idx = ast2700_gic_intcmap[i].orgate_idx;
+ idx = ast2700_gic_intcmap[i].intc_idx;
+ return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
+ ast2700_gic_intcmap[i].ptr[dev] + index);
}
}
@@ -372,7 +402,8 @@ static void aspeed_soc_ast2700_init(Object *obj)
object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO);
- object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC0);
+ object_initialize_child(obj, "intc0", &a->intc[0], TYPE_ASPEED_2700_INTC0);
+ object_initialize_child(obj, "intc1", &a->intc[1], TYPE_ASPEED_2700_INTC1);
snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
object_initialize_child(obj, "adc", &s->adc, typename);
@@ -481,7 +512,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc);
g_autofree char *sram_name = NULL;
qemu_irq irq;
@@ -511,21 +541,45 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
return;
}
- /* INTC */
- if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) {
+ /* INTC0 */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
sc->memmap[ASPEED_DEV_INTC0]);
- /* GICINT orgates -> INTC -> GIC */
- for (i = 0; i < ic->num_inpins; i++) {
- qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
- qdev_get_gpio_in(DEVICE(&a->intc), i));
- sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
+ /* INTC1 */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
+ return;
+ }
+
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
+ sc->memmap[ASPEED_DEV_INTC1]);
+
+ /* irq source orgates -> INTC0 */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) {
+ qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
+ qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
+ }
+ /* INTC0 -> GIC192 - GIC201 */
+ /* INTC0 -> GIC128 - GIC136 */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++) {
+ assert(i < ARRAY_SIZE(ast2700_gic_intcmap));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
qdev_get_gpio_in(DEVICE(&a->gic),
- aspeed_soc_ast2700_gic_intcmap[i].irq));
+ ast2700_gic_intcmap[i].irq));
+ }
+
+ /* irq source orgates -> INTC1 */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++) {
+ qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
+ qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
+ }
+ /* INTC1 -> INTC0 */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
+ qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
/* SRAM */
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 51e585e3e4..c079225775 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -128,7 +128,7 @@ struct Aspeed27x0SoCState {
AspeedSoCState parent;
ARMCPU cpu[ASPEED_CPUS_NUM];
- AspeedINTCState intc;
+ AspeedINTCState intc[2];
GICv3State gic;
MemoryRegion dram_empty;
};
@@ -195,6 +195,7 @@ enum {
ASPEED_DEV_EHCI2,
ASPEED_DEV_VIC,
ASPEED_DEV_INTC0,
+ ASPEED_DEV_INTC1,
ASPEED_DEV_SDMC,
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
2025-01-21 7:04 ` [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
@ 2025-01-30 4:19 ` Andrew Jeffery
2025-02-04 9:43 ` Jamin Lin
0 siblings, 1 reply; 54+ messages in thread
From: Andrew Jeffery @ 2025-01-30 4:19 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The design of INTC controllers has significantly changed in AST2700 A1.
>
> There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
> from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
> limitation of interrupt numbers of processors, the interrupts are merged every
> 32 sources for interrupt numbers greater than 127.
>
> There are two levels of interrupt controllers, INTC0 and INTC1. The interrupt
> sources of INTC0 are the interrupt numbers from INTC_0 to INTC_127 and
> interrupts from INTC1. The interrupt sources of INTC1 are the interrupt numbers
> greater than INTC_127. INTC1 controls the interrupts INTC_128 to INTC_319 only.
>
> Currently, only GIC 192 to 201 are supported, and their source interrupts are
> from INTC1 and connected to INTC0 at input pin 0 and output pins 0 to 9 for
> GIC 192-201.
>
> To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and output pins
> 10 to 18 remain to support GIC 128-136, which source interrupts from INTC0.
> These will be removed if we decide not to support AST2700 A0 in the future.
>
> +---------------------------------------------------------------------------------------+
> > AST2700 A1 Design |
> > |
> > +--------------------------+ |
> > | INTC1 | +---------------+ |
> > | | | orgates[0] | |
> > orgates[0]+----> |inpin[0]+------->outpin[0]+------> | 0 | |
> > orgates[1]|----> |inpin[1]|------->outpin[1]|------> | 1 0-31 bits +--+ |
> > orgates[2]|----> |inpin[2]|------->outpin[2]|------> | 2 | | |
> > orgates[3]|----> |inpin[3]|------->outpin[3]|------> | 3 | | |
> > orgates[4]|----> |inpin[4]|------->outpin[4]|------> | 4 | | |
> > orgates[5]+----> |inpin[5]+------->outpin[5]+------> | 5 | | |
> > | | |---------------| | |
> > +--------------------------+ | |
> > +-----------------------------------------------------------------------| |
> > | |
> > | |
> > | +------------------------------+ +-----------------+ |
> > | | INTC0 | | GIC | |
> > | |inpin[0:0]--------->outpin[0] +---------> |192 | |
> > | |inpin[0:1]|-------->outpin[1] |---------> |193 | |
> > | |inpin[0:2]|-------->outpin[2] |---------> |194 | |
> > | |inpin[0:3]|-------->outpin[3] |---------> |195 | |
> > >--------------> |inpin[0:4]|-------->outpin[4] |---------> |196 | |
> > |inpin[0:5]|-------->outpin[5] |---------> |197 | |
> > |inpin[0:6]|-------->outpin[6] |---------> |198 | |
> > |inpin[0:7]|-------->outpin[7] |---------> |199 | |
> > |inpin[0:8]|-------->outpin[8] |---------> |200 | |
> > |inpin[0:9]|-------->outpin[9] |---------> |201 | |
> +---------------------------------------------------------------------------------------+
> +---------------------------------------------------------------------------------------+
> > orgates[1]|-----> |inpin[1]|---------->outpin[10]|---------> |128 | |
> > orgates[2]|-----> |inpin[2]|---------->outpin[11]|---------> |129 | |
> > orgates[3]|-----> |inpin[3]|---------->outpin[12]|---------> |130 | |
> > orgates[4]|-----> |inpin[4]|---------->outpin[13]|---------> |131 | |
> > orgates[5]|-----> |inpin[5]|---------->outpin[14]|---------> |132 | |
> > orgates[6]|-----> |inpin[6]|---------->outpin[15]|---------> |133 | |
> > orgates[7]|-----> |inpin[7]|---------->outpin[16]|---------> |134 | |
> > orgates[8]|-----> |inpin[8]|---------->outpin[17]|---------> |135 | |
> > orgates[9]+-----> |inpin[9]|---------->outpin[18]+---------> |136 | |
> > +------------------------------+ +-----------------+ |
> > |
> > AST2700 A0 Design |
> > |
> +---------------------------------------------------------------------------------------+
>
Okay, so I think this is the diagram and discussion I asked for as
documentation earlier. I still prefer it doesn't just live in a commit
message, that you pull it out to a separate document that we can easily
point to and evolve.
I'm a little hazy on some of your notation in diagram though. Can you
explain your use of pipes ("|"), plusses ("+"), the "orgates" to the
left of INTC1 (what are they ORing?), and the choice of 5 lines into
the "orgates[0]" box? Also why does the "orgates[0]" arrow point where
it does on INTC0?
Andrew
^ permalink raw reply [flat|nested] 54+ messages in thread* RE: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
2025-01-30 4:19 ` Andrew Jeffery
@ 2025-02-04 9:43 ` Jamin Lin
2025-02-05 3:50 ` Andrew Jeffery
0 siblings, 1 reply; 54+ messages in thread
From: Jamin Lin @ 2025-02-04 9:43 UTC (permalink / raw)
To: Andrew Jeffery, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hi Andrew,
> -----Original Message-----
> From: Andrew Jeffery <andrew@codeconstruct.com.au>
> Sent: Thursday, January 30, 2025 12:20 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
> Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel Stanley
> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of
> INTC controllers for AST2700 A1
>
> On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> > The design of INTC controllers has significantly changed in AST2700 A1.
> >
> > There are a total of 480 interrupt sources in AST2700 A1. For
> > interrupt numbers from 0 to 127, they can route directly to PSP, SSP,
> > and TSP. Due to the limitation of interrupt numbers of processors, the
> > interrupts are merged every
> > 32 sources for interrupt numbers greater than 127.
> >
> > There are two levels of interrupt controllers, INTC0 and INTC1. The
> > interrupt sources of INTC0 are the interrupt numbers from INTC_0 to
> > INTC_127 and interrupts from INTC1. The interrupt sources of INTC1 are
> > the interrupt numbers greater than INTC_127. INTC1 controls the interrupts
> INTC_128 to INTC_319 only.
> >
> > Currently, only GIC 192 to 201 are supported, and their source
> > interrupts are from INTC1 and connected to INTC0 at input pin 0 and
> > output pins 0 to 9 for GIC 192-201.
> >
> > To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and output
> > pins
> > 10 to 18 remain to support GIC 128-136, which source interrupts from INTC0.
> > These will be removed if we decide not to support AST2700 A0 in the future.
> >
> > +---------------------------------------------------------------------------------------+
> > > AST2700 A1
> Design
> > > |
> >
> >
>
> > > |
> >
> > +--------------------------+
>
> > > |
> >
> > | INTC1 |
>
> > > +---------------+ |
> >
> > | |
> |
> > > orgates[0] | |
> > > orgates[0]+----> |inpin[0]+------->outpin[0]+------> |
> 0
> > > | |
> > > orgates[1]|----> |inpin[1]|------->outpin[1]|------> | 1 0-31
> > > bits +--+ |
> > > orgates[2]|----> |inpin[2]|------->outpin[2]|------> |
> 2
> > > | | |
> > > orgates[3]|----> |inpin[3]|------->outpin[3]|------> |
> 3
> > > | | |
> > > orgates[4]|----> |inpin[4]|------->outpin[4]|------> |
> 4
> > > | | |
> > > orgates[5]+----> |inpin[5]+------->outpin[5]+------> |
> 5
> > > | | |
> >
> > | |
>
> > > |---------------| | |
> >
> > +--------------------------+
>
> > > | |
> > >
> > > +-------------------------------------------------------------------
> > > ----| |
> >
> > |
>
> > > |
> >
> > |
>
> > > |
> > > | +------------------------------+
> > > +-----------------+ |
> >
> > | | INTC0 |
> |
> > > GIC | |
> > > | |inpin[0:0]--------->outpin[0] +--------->
> |192
> > > | |
> > > | |inpin[0:1]|-------->outpin[1] |--------->
> |193
> > > | |
> > > | |inpin[0:2]|-------->outpin[2] |--------->
> |194
> > > | |
> > > | |inpin[0:3]|-------->outpin[3] |--------->
> |195
> > > | |
> > > >--------------> |inpin[0:4]|-------->outpin[4] |--------->
> |196
> > > | |
> > > |inpin[0:5]|-------->outpin[5] |--------->
> |197
> > > | |
> > > |inpin[0:6]|-------->outpin[6] |--------->
> |198
> > > | |
> > > |inpin[0:7]|-------->outpin[7] |--------->
> |199
> > > | |
> > > |inpin[0:8]|-------->outpin[8] |--------->
> |200
> > > | |
> > > |inpin[0:9]|-------->outpin[9] |--------->
> |201
> > > | |
> > +---------------------------------------------------------------------------------------+
> > +---------------------------------------------------------------------------------------+
> > > orgates[1]|-----> |inpin[1]|---------->outpin[10]|--------->
> |128
> > > | |
> > > orgates[2]|-----> |inpin[2]|---------->outpin[11]|--------->
> |129
> > > | |
> > > orgates[3]|-----> |inpin[3]|---------->outpin[12]|--------->
> |130
> > > | |
> > > orgates[4]|-----> |inpin[4]|---------->outpin[13]|--------->
> |131
> > > | |
> > > orgates[5]|-----> |inpin[5]|---------->outpin[14]|--------->
> |132
> > > | |
> > > orgates[6]|-----> |inpin[6]|---------->outpin[15]|--------->
> |133
> > > | |
> > > orgates[7]|-----> |inpin[7]|---------->outpin[16]|--------->
> |134
> > > | |
> > > orgates[8]|-----> |inpin[8]|---------->outpin[17]|--------->
> |135
> > > | |
> > > orgates[9]+-----> |inpin[9]|---------->outpin[18]+--------->
> |136
> > > | |
> > > +------------------------------+
> > > +-----------------+ |
> >
> >
>
> > > |
> > > AST2700 A0
> Design
>
> > > |
> >
> >
>
> > > |
> > +---------------------------------------------------------------------------------------+
> >
>
> Okay, so I think this is the diagram and discussion I asked for as documentation
> earlier. I still prefer it doesn't just live in a commit message, that you pull it out
> to a separate document that we can easily point to and evolve.
>
INTC drivers owners update DTS binding document here,
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20241016022410.1154574-2-kevin_chen@aspeedtech.com/
> I'm a little hazy on some of your notation in diagram though. Can you explain
> your use of pipes ("|"), plusses ("+"), the "orgates" to the left of INTC1 (what
> are they ORing?), and the choice of 5 lines into the "orgates[0]" box? Also why
> does the "orgates[0]" arrow point where it does on INTC0?
>
I created this block diagram using the asciiflow tool and both ("I") and "("+") symbols are identical.
I will update the diagram and replace ("+") with ("|").
Sorry to make you confuse.
The design of the OR gates for GICINT 196 is as follows:
It has interrupt sources ranging from 0 to 31, with its output pin connected to INTC_IO "T0 GICINTC_192".
The output pin is then connected to INTC_CPU "GIC_192_201" at bit 0, and its bit 0 output should be connected to GIC 192.
The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following:
Bit 0 --> GIC 192
BIT 1 -> GIC 193
BIT 2-> GIC 194
Our firmware only utilizes bits 0 to 5, so I have only illustrated bits 0 to 5 in the diagram. However, I have implemented bits 0 to 9 in the code.
Then, orgates[0] "or" the output pins of INTC_IO (To GIC192, To GIC193, To GIC194, To GIC195, To GIC196)
ETH1 +-----------+
+--------v+0 3+
ETH2 | 4|
+-------->+1 5|
ETH3 | 6|
+-------->+2 19|
UART0 | 20|
+-------->+7 21|
UART1 | 22|
+-------->+8 23|
UART2 | 24|
+-------->+9 25|
UART3 | 26|
+--------->10 27|
UART5 | 28|
+-------->+11 29|
UART6 | |
+-------->+12 30|
UART7 | 31|
+-------->+13 |
UART8 | OR[0:31] |
+--------->14 |
UART9 | |
+-------->+15 |
UART10 | |
+-------->+16 |
UART11 | |
+-------->+17 |
UART12 | |
+--------->18 |
| |
| |
| |
+-----------+
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi#L483
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi#L1610
Thanks-Jamin
> Andrew
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
2025-02-04 9:43 ` Jamin Lin
@ 2025-02-05 3:50 ` Andrew Jeffery
2025-02-05 7:12 ` Jamin Lin
0 siblings, 1 reply; 54+ messages in thread
From: Andrew Jeffery @ 2025-02-05 3:50 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
On Tue, 2025-02-04 at 09:43 +0000, Jamin Lin wrote:
> Hi Andrew,
>
> > -----Original Message-----
> > From: Andrew Jeffery <andrew@codeconstruct.com.au>
> > Sent: Thursday, January 30, 2025 12:20 PM
> > To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
> > Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> > <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel Stanley
> > <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> > list:All patches CC here <qemu-devel@nongnu.org>
> > Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> > <yunlin.tang@aspeedtech.com>
> > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of
> > INTC controllers for AST2700 A1
> >
> > On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> > > The design of INTC controllers has significantly changed in AST2700 A1.
> > >
> > > There are a total of 480 interrupt sources in AST2700 A1. For
> > > interrupt numbers from 0 to 127, they can route directly to PSP, SSP,
> > > and TSP. Due to the limitation of interrupt numbers of processors, the
> > > interrupts are merged every
> > > 32 sources for interrupt numbers greater than 127.
> > >
> > > There are two levels of interrupt controllers, INTC0 and INTC1. The
> > > interrupt sources of INTC0 are the interrupt numbers from INTC_0 to
> > > INTC_127 and interrupts from INTC1. The interrupt sources of INTC1 are
> > > the interrupt numbers greater than INTC_127. INTC1 controls the interrupts
> > INTC_128 to INTC_319 only.
> > >
> > > Currently, only GIC 192 to 201 are supported, and their source
> > > interrupts are from INTC1 and connected to INTC0 at input pin 0 and
> > > output pins 0 to 9 for GIC 192-201.
> > >
> > > To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and output
> > > pins
> > > 10 to 18 remain to support GIC 128-136, which source interrupts from INTC0.
> > > These will be removed if we decide not to support AST2700 A0 in the future.
> > >
> > > +---------------------------------------------------------------------------------------+
> > > > AST2700 A1
> > Design
> > > > >
> > >
> > >
> >
> > > > >
> > >
> > > +--------------------------+
> >
> > > > >
> > >
> > > | INTC1 |
> >
> > > > +---------------+ |
> > >
> > > | |
> > |
> > > > orgates[0] | |
> > > > orgates[0]+----> |inpin[0]+------->outpin[0]+------> |
> > 0
> > > > > |
> > > > orgates[1]|----> |inpin[1]|------->outpin[1]|------> | 1 0-31
> > > > bits +--+ |
> > > > orgates[2]|----> |inpin[2]|------->outpin[2]|------> |
> > 2
> > > > > | |
> > > > orgates[3]|----> |inpin[3]|------->outpin[3]|------> |
> > 3
> > > > > | |
> > > > orgates[4]|----> |inpin[4]|------->outpin[4]|------> |
> > 4
> > > > > | |
> > > > orgates[5]+----> |inpin[5]+------->outpin[5]+------> |
> > 5
> > > > > | |
> > >
> > > | |
> >
> > > > > ---------------| | |
> > >
> > > +--------------------------+
> >
> > > > > |
> > > >
> > > > +-------------------------------------------------------------------
> > > > ----| |
> > >
> > > |
> >
> > > > >
> > >
> > > |
> >
> > > > >
> > > > | +------------------------------+
> > > > +-----------------+ |
> > >
> > > | | INTC0 |
> > |
> > > > GIC | |
> > > > | |inpin[0:0]--------->outpin[0] +--------->
> > > 192
> > > > > |
> > > > | |inpin[0:1]|-------->outpin[1] |--------->
> > > 193
> > > > > |
> > > > | |inpin[0:2]|-------->outpin[2] |--------->
> > > 194
> > > > > |
> > > > | |inpin[0:3]|-------->outpin[3] |--------->
> > > 195
> > > > > |
> > > > >--------------> |inpin[0:4]|-------->outpin[4] |--------->
> > > 196
> > > > > |
> > > > |inpin[0:5]|-------->outpin[5] |--------->
> > > 197
> > > > > |
> > > > |inpin[0:6]|-------->outpin[6] |--------->
> > > 198
> > > > > |
> > > > |inpin[0:7]|-------->outpin[7] |--------->
> > > 199
> > > > > |
> > > > |inpin[0:8]|-------->outpin[8] |--------->
> > > 200
> > > > > |
> > > > |inpin[0:9]|-------->outpin[9] |--------->
> > > 201
> > > > > |
> > > +---------------------------------------------------------------------------------------+
> > > +---------------------------------------------------------------------------------------+
> > > > orgates[1]|-----> |inpin[1]|---------->outpin[10]|--------->
> > > 128
> > > > > |
> > > > orgates[2]|-----> |inpin[2]|---------->outpin[11]|--------->
> > > 129
> > > > > |
> > > > orgates[3]|-----> |inpin[3]|---------->outpin[12]|--------->
> > > 130
> > > > > |
> > > > orgates[4]|-----> |inpin[4]|---------->outpin[13]|--------->
> > > 131
> > > > > |
> > > > orgates[5]|-----> |inpin[5]|---------->outpin[14]|--------->
> > > 132
> > > > > |
> > > > orgates[6]|-----> |inpin[6]|---------->outpin[15]|--------->
> > > 133
> > > > > |
> > > > orgates[7]|-----> |inpin[7]|---------->outpin[16]|--------->
> > > 134
> > > > > |
> > > > orgates[8]|-----> |inpin[8]|---------->outpin[17]|--------->
> > > 135
> > > > > |
> > > > orgates[9]+-----> |inpin[9]|---------->outpin[18]+--------->
> > > 136
> > > > > |
> > > > +------------------------------+
> > > > +-----------------+ |
> > >
> > >
> >
> > > > >
> > > > AST2700 A0
> > Design
> >
> > > > >
> > >
> > >
> >
> > > > >
> > > +---------------------------------------------------------------------------------------+
> > >
> >
> > Okay, so I think this is the diagram and discussion I asked for as documentation
> > earlier. I still prefer it doesn't just live in a commit message, that you pull it out
> > to a separate document that we can easily point to and evolve.
> >
> INTC drivers owners update DTS binding document here,
> https://patchwork.kernel.org/project/linux-arm-kernel/patch/20241016022410.1154574-2-kevin_chen@aspeedtech.com/
The diagram there is relatively straight-forward, but I suspect the
devil is in the details.
>
>
> > I'm a little hazy on some of your notation in diagram though. Can you explain
> > your use of pipes ("|"), plusses ("+"), the "orgates" to the left of INTC1 (what
> > are they ORing?), and the choice of 5 lines into the "orgates[0]" box? Also why
> > does the "orgates[0]" arrow point where it does on INTC0?
> >
> I created this block diagram using the asciiflow tool and both ("I") and "("+") symbols are identical.
> I will update the diagram and replace ("+") with ("|").
> Sorry to make you confuse.
Ah, right.
>
> The design of the OR gates for GICINT 196 is as follows:
196? You discuss 192 below.
> It has interrupt sources ranging from 0 to 31, with its output pin connected to INTC_IO "T0 GICINTC_192".
> The output pin is then connected to INTC_CPU "GIC_192_201" at bit 0, and its bit 0 output should be connected to GIC 192.
>
> The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following:
> Bit 0 --> GIC 192
> BIT 1 -> GIC 193
> BIT 2-> GIC 194
>
> Our firmware only utilizes bits 0 to 5, so I have only illustrated bits 0 to 5 in the diagram. However, I have implemented bits 0 to 9 in the code.
Ah, okay, this is helpful context.
>
> Then, orgates[0] "or" the output pins of INTC_IO (To GIC192, To GIC193, To GIC194, To GIC195, To GIC196)
>
> ETH1 +-----------+
> +--------v+0 3+
> ETH2 | 4|
> +-------->+1 5|
> ETH3 | 6|
> +-------->+2 19|
> UART0 | 20|
> +-------->+7 21|
> UART1 | 22|
> +-------->+8 23|
> UART2 | 24|
> +-------->+9 25|
> UART3 | 26|
> +--------->10 27|
> UART5 | 28|
> +-------->+11 29|
> UART6 | |
> +-------->+12 30|
> UART7 | 31|
> +-------->+13 |
> UART8 | OR[0:31] |
> +--------->14 |
> UART9 | |
> +-------->+15 |
> UART10 | |
> +-------->+16 |
> UART11 | |
> +-------->+17 |
> UART12 | |
> +--------->18 |
> | |
> | |
> | |
> +-----------+
>
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi#L483
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi#L1610
Let me absorb this and develop my own understanding in conjunction with
the datasheet. It may take a few days.
Andrew
^ permalink raw reply [flat|nested] 54+ messages in thread* RE: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
2025-02-05 3:50 ` Andrew Jeffery
@ 2025-02-05 7:12 ` Jamin Lin
2025-02-05 23:39 ` Andrew Jeffery
2025-02-06 7:22 ` Cédric Le Goater
0 siblings, 2 replies; 54+ messages in thread
From: Jamin Lin @ 2025-02-05 7:12 UTC (permalink / raw)
To: Andrew Jeffery, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hi Andrew,
> From: Andrew Jeffery <andrew@codeconstruct.com.au>
> Sent: Wednesday, February 5, 2025 11:51 AM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
> Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel Stanley
> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of
> INTC controllers for AST2700 A1
>
> On Tue, 2025-02-04 at 09:43 +0000, Jamin Lin wrote:
> > Hi Andrew,
> >
> > > -----Original Message-----
> > > From: Andrew Jeffery <andrew@codeconstruct.com.au>
> > > Sent: Thursday, January 30, 2025 12:20 PM
> > > To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater
> > > <clg@kaod.org>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> > > <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel
> > > Stanley <joel@jms.id.au>; open list:ASPEED BMCs
> > > <qemu-arm@nongnu.org>; open list:All patches CC here
> > > <qemu-devel@nongnu.org>
> > > Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> > > <yunlin.tang@aspeedtech.com>
> > > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two
> > > levels of INTC controllers for AST2700 A1
> > >
> > > On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> > > > The design of INTC controllers has significantly changed in AST2700 A1.
> > > >
> > > > There are a total of 480 interrupt sources in AST2700 A1. For
> > > > interrupt numbers from 0 to 127, they can route directly to PSP,
> > > > SSP, and TSP. Due to the limitation of interrupt numbers of
> > > > processors, the interrupts are merged every
> > > > 32 sources for interrupt numbers greater than 127.
> > > >
> > > > There are two levels of interrupt controllers, INTC0 and INTC1.
> > > > The interrupt sources of INTC0 are the interrupt numbers from
> > > > INTC_0 to
> > > > INTC_127 and interrupts from INTC1. The interrupt sources of INTC1
> > > > are the interrupt numbers greater than INTC_127. INTC1 controls
> > > > the interrupts
> > > INTC_128 to INTC_319 only.
> > > >
> > > > Currently, only GIC 192 to 201 are supported, and their source
> > > > interrupts are from INTC1 and connected to INTC0 at input pin 0
> > > > and output pins 0 to 9 for GIC 192-201.
> > > >
> > > > To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and
> > > > output pins
> > > > 10 to 18 remain to support GIC 128-136, which source interrupts from
> INTC0.
> > > > These will be removed if we decide not to support AST2700 A0 in the
> future.
> > > >
> > > > +---------------------------------------------------------------------------------------+
> > > > > AST2700 A1
> > > Design
> > > > > >
> > > >
> > > >
> > >
> > > > > >
> > > >
> > > > +--------------------------+
> > >
> > > > > >
> > > >
> > > > | INTC1 |
> > >
> > > > > +---------------+ |
> > > >
> > > > | |
> > > |
> > > > > orgates[0] | |
> > > > > orgates[0]+----> |inpin[0]+------->outpin[0]+------> |
> > > 0
> > > > > > |
> > > > > orgates[1]|----> |inpin[1]|------->outpin[1]|------> | 1
> > > > > 0-31 bits +--+ |
> > > > > orgates[2]|----> |inpin[2]|------->outpin[2]|------> |
> > > 2
> > > > > > | |
> > > > > orgates[3]|----> |inpin[3]|------->outpin[3]|------> |
> > > 3
> > > > > > | |
> > > > > orgates[4]|----> |inpin[4]|------->outpin[4]|------> |
> > > 4
> > > > > > | |
> > > > > orgates[5]+----> |inpin[5]+------->outpin[5]+------> |
> > > 5
> > > > > > | |
> > > >
> > > > | |
> > >
> > > > > > ---------------| | |
> > > >
> > > > +--------------------------+
> > >
> > > > > > |
> > > > >
> > > > > +---------------------------------------------------------------
> > > > > +----
> > > > > ----| |
> > > >
> > > > |
> > >
> > > > > >
> > > >
> > > > |
> > >
> > > > > >
> > > > > | +------------------------------+
> > > > > +-----------------+ |
> > > >
> > >
> > | | INTC0 |
> > > |
> > > > > GIC | |
> > > > > | |inpin[0:0]--------->outpin[0] +--------->
> > > > 192
> > > > > > |
> > > > > | |inpin[0:1]|-------->outpin[1] |--------->
> > > > 193
> > > > > > |
> > > > > | |inpin[0:2]|-------->outpin[2] |--------->
> > > > 194
> > > > > > |
> > > > > | |inpin[0:3]|-------->outpin[3] |--------->
> > > > 195
> > > > > > |
> > > > > >--------------> |inpin[0:4]|-------->outpin[4] |--------->
> > > > 196
> > > > > > |
> > > > > |inpin[0:5]|-------->outpin[5] |--------->
> > > > 197
> > > > > > |
> > > > > |inpin[0:6]|-------->outpin[6] |--------->
> > > > 198
> > > > > > |
> > > > > |inpin[0:7]|-------->outpin[7] |--------->
> > > > 199
> > > > > > |
> > > > > |inpin[0:8]|-------->outpin[8] |--------->
> > > > 200
> > > > > > |
> > > > > |inpin[0:9]|-------->outpin[9] |--------->
> > > > 201
> > > > > > |
> > > > +---------------------------------------------------------------------------------------+
> > > > +---------------------------------------------------------------------------------------+
> > > > > orgates[1]|-----> |inpin[1]|---------->outpin[10]|--------->
> > > > 128
> > > > > > |
> > > > > orgates[2]|-----> |inpin[2]|---------->outpin[11]|--------->
> > > > 129
> > > > > > |
> > > > > orgates[3]|-----> |inpin[3]|---------->outpin[12]|--------->
> > > > 130
> > > > > > |
> > > > > orgates[4]|-----> |inpin[4]|---------->outpin[13]|--------->
> > > > 131
> > > > > > |
> > > > > orgates[5]|-----> |inpin[5]|---------->outpin[14]|--------->
> > > > 132
> > > > > > |
> > > > > orgates[6]|-----> |inpin[6]|---------->outpin[15]|--------->
> > > > 133
> > > > > > |
> > > > > orgates[7]|-----> |inpin[7]|---------->outpin[16]|--------->
> > > > 134
> > > > > > |
> > > > > orgates[8]|-----> |inpin[8]|---------->outpin[17]|--------->
> > > > 135
> > > > > > |
> > > > > orgates[9]+-----> |inpin[9]|---------->outpin[18]+--------->
> > > > 136
> > > > > > |
> > > > > +------------------------------+
> > > > > +-----------------+ |
> > > >
> > > >
> > >
> > > > > >
> > > > > AST2700 A0
> > > Design
> > >
> > > > > >
> > > >
> > > >
> > >
> > > > > >
> > > > +---------------------------------------------------------------------------------------+
> > > >
> > >
> > > Okay, so I think this is the diagram and discussion I asked for as
> > > documentation earlier. I still prefer it doesn't just live in a
> > > commit message, that you pull it out to a separate document that we can
> easily point to and evolve.
> > >
> > INTC drivers owners update DTS binding document here,
> > https://patchwork.kernel.org/project/linux-arm-kernel/patch/2024101602
> > 2410.1154574-2-kevin_chen@aspeedtech.com/
>
> The diagram there is relatively straight-forward, but I suspect the devil is in the
> details.
>
> >
> >
> > > I'm a little hazy on some of your notation in diagram though. Can
> > > you explain your use of pipes ("|"), plusses ("+"), the "orgates" to
> > > the left of INTC1 (what are they ORing?), and the choice of 5 lines
> > > into the "orgates[0]" box? Also why does the "orgates[0]" arrow point where
> it does on INTC0?
> > >
> > I created this block diagram using the asciiflow tool and both ("I") and "("+")
> symbols are identical.
> > I will update the diagram and replace ("+") with ("|").
> > Sorry to make you confuse.
>
> Ah, right.
>
> >
> > The design of the OR gates for GICINT 196 is as follows:
>
> 196? You discuss 192 below.
>
Sorry typo. I update my comments.
The design of the OR gates for GICINT 196 is as follows:
It has interrupt sources ranging from 0 to 31, with its output pin connected to
INTC_IO "T0 GICINT_196".
The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4, and
its bit 4 output should be connected to GIC 196.
The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
Jamin
|-------------------------------------------------------------------------------------------------------|
| AST2700 A1 Design |
| To GICINT196 |
| |
| ETH1 |-----------| |--------------------------| |--------------| |
| -------->|0 | | INTC_IO | | orgates[0] | |
| ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | |
| -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | |
| ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | |
| -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| |
| UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | |
| -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | |
| UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | |
| -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | |
| UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | |
| -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | |
| UART3 | 26| |--------------------------| |--------------| | |
| ---------|10 27| | |
| UART5 | 28| | |
| -------->|11 29| | |
| UART6 | | | |
| -------->|12 30| |-----------------------------------------------------------------------| |
| UART7 | 31| | |
| -------->|13 | | |
| UART8 | OR[0:31] | | |------------------------------| |----------| |
| -------->|14 | | | INTC | | GIC | |
| UART9 | | | |inpin[0:0]--------->outpin[0] |---------->|192 | |
| -------->|15 | | |inpin[0:1]--------->outpin[1] |---------->|193 | |
| UART10 | | | |inpin[0:2]--------->outpin[2] |---------->|194 | |
| -------->|16 | | |inpin[0:3]--------->outpin[3] |---------->|195 | |
| UART11 | | |--------------> |inpin[0:4]--------->outpin[4] |---------->|196 | |
| -------->|17 | |inpin[0:5]--------->outpin[5] |---------->|197 | |
| UART12 | | |inpin[0:6]--------->outpin[6] |---------->|198 | |
| -------->|18 | |inpin[0:7]--------->outpin[7] |---------->|199 | |
| |-----------| |inpin[0:8]--------->outpin[8] |---------->|200 | |
| |inpin[0:9]--------->outpin[9] |---------->|201 | |
|-------------------------------------------------------------------------------------------------------|
|-------------------------------------------------------------------------------------------------------|
| ETH1 |-----------| orgates[1]------->|inpin[1]|---------->outpin[10]|---------->|128 | |
| -------->|0 | orgates[2]------->|inpin[2]|---------->outpin[11]|---------->|129 | |
| ETH2 | 4| orgates[3]------->|inpin[3]|---------->outpin[12]|---------->|130 | |
| -------->|1 5| orgates[4]------->|inpin[4]|---------->outpin[13]|---------->|131 | |
| ETH3 | 6|---->orgates[5]------->|inpin[5]|---------->outpin[14]|---------->|132 | |
| -------->|2 19| orgates[6]------->|inpin[6]|---------->outpin[15]|---------->|133 | |
| UART0 | 20| orgates[7]------->|inpin[7]|---------->outpin[16]|---------->|134 | |
| -------->|7 21| orgates[8]------->|inpin[8]|---------->outpin[17]|---------->|135 | |
| UART1 | 22| orgates[9]------->|inpin[9]|---------->outpin[18]|---------->|136 | |
| -------->|8 23| |------------------------------| |----------| |
| UART2 | 24| |
| -------->|9 25| AST2700 A0 Design |
| UART3 | 26| |
| -------->|10 27| |
| UART5 | 28| |
| -------->|11 29| GICINT132 |
| UART6 | | |
| -------->|12 30| |
| UART7 | 31| |
| -------->|13 | |
| UART8 | OR[0:31] | |
| -------->|14 | |
| UART9 | | |
| -------->|15 | |
| UART10 | | |
| -------->|16 | |
| UART11 | | |
| -------->|17 | |
| UART12 | | |
| -------->|18 | |
| |-----------| |
| |
|-------------------------------------------------------------------------------------------------------|
> >
> > Our firmware only utilizes bits 0 to 5, so I have only illustrated bits 0 to 5 in
> the diagram. However, I have implemented bits 0 to 9 in the code.
> > It has interrupt sources ranging from 0 to 31, with its output pin connected to
> INTC_IO "T0 GICINTC_192".
> > The output pin is then connected to INTC_CPU "GIC_192_201" at bit 0, and
> its bit 0 output should be connected to GIC 192.
> >
> > The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as
> following:
> > Bit 0 --> GIC 192
> > BIT 1 -> GIC 193
> > BIT 2-> GIC 194
> >
> > Our firmware only utilizes bits 0 to 5, so I have only illustrated bits 0 to 5 in
> the diagram. However, I have implemented bits 0 to 9 in the code.
>
> Ah, okay, this is helpful context.
>
> >
> > Then, orgates[0] "or" the output pins of INTC_IO (To GIC192, To
> > GIC193, To GIC194, To GIC195, To GIC196)
> >
> > ETH1 +-----------+
> > +--------v+0 3+
> > ETH2 | 4|
> > +-------->+1 5|
> > ETH3 | 6|
> > +-------->+2 19|
> > UART0 | 20|
> > +-------->+7 21|
> > UART1 | 22|
> > +-------->+8 23|
> > UART2 | 24|
> > +-------->+9 25|
> > UART3 | 26|
> > +--------->10 27|
> > UART5 | 28|
> > +-------->+11 29|
> > UART6 | |
> > +-------->+12 30|
> > UART7 | 31|
> > +-------->+13 |
> > UART8 | OR[0:31] |
> > +--------->14 |
> > UART9 | |
> > +-------->+15 |
> > UART10 | |
> > +-------->+16 |
> > UART11 | |
> > +-------->+17 |
> > UART12 | |
> > +--------->18 |
> > | |
> > | |
> > | |
> > +-----------+
> >
> > https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/a
> > rm64/boot/dts/aspeed/aspeed-g7.dtsi#L483
> > https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/a
> > rm64/boot/dts/aspeed/aspeed-g7.dtsi#L1610
>
> Let me absorb this and develop my own understanding in conjunction with the
> datasheet. It may take a few days.
>
> Andrew
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
2025-02-05 7:12 ` Jamin Lin
@ 2025-02-05 23:39 ` Andrew Jeffery
2025-02-06 4:55 ` Joel Stanley
2025-02-06 7:22 ` Cédric Le Goater
1 sibling, 1 reply; 54+ messages in thread
From: Andrew Jeffery @ 2025-02-05 23:39 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hi Jamin,
> > >
> > > The design of the OR gates for GICINT 196 is as follows:
> >
> > 196? You discuss 192 below.
> >
> Sorry typo. I update my comments.
>
> The design of the OR gates for GICINT 196 is as follows:
> It has interrupt sources ranging from 0 to 31, with its output pin connected to
> INTC_IO "T0 GICINT_196".
> The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4, and
> its bit 4 output should be connected to GIC 196.
> The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following:
> Bit 0 -> GIC 192
> Bit 1 -> GIC 193
> Bit 2 -> GIC 194
> Bit 3 -> GIC 195
> Bit 4 -> GIC 196
>
> Jamin
> |-------------------------------------------------------------------------------------------------------|
> | AST2700 A1 Design |
> | To GICINT196 |
> | |
> | ETH1 |-----------| |--------------------------| |--------------| |
> | -------->|0 | | INTC_IO | | orgates[0] | |
> | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | |
> | -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | |
> | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | |
> | -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| |
> | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | |
> | -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | |
> | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | |
> | -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | |
> | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | |
> | -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | |
> | UART3 | 26| |--------------------------| |--------------| | |
> | ---------|10 27| | |
> | UART5 | 28| | |
> | -------->|11 29| | |
> | UART6 | | | |
> | -------->|12 30| |-----------------------------------------------------------------------| |
> | UART7 | 31| | |
> | -------->|13 | | |
> | UART8 | OR[0:31] | | |------------------------------| |----------| |
> | -------->|14 | | | INTC | | GIC | |
> | UART9 | | | |inpin[0:0]--------->outpin[0] |---------->|192 | |
> | -------->|15 | | |inpin[0:1]--------->outpin[1] |---------->|193 | |
> | UART10 | | | |inpin[0:2]--------->outpin[2] |---------->|194 | |
> | -------->|16 | | |inpin[0:3]--------->outpin[3] |---------->|195 | |
> | UART11 | | |--------------> |inpin[0:4]--------->outpin[4] |---------->|196 | |
> | -------->|17 | |inpin[0:5]--------->outpin[5] |---------->|197 | |
> | UART12 | | |inpin[0:6]--------->outpin[6] |---------->|198 | |
> | -------->|18 | |inpin[0:7]--------->outpin[7] |---------->|199 | |
> | |-----------| |inpin[0:8]--------->outpin[8] |---------->|200 | |
> | |inpin[0:9]--------->outpin[9] |---------->|201 | |
> |-------------------------------------------------------------------------------------------------------|
> |-------------------------------------------------------------------------------------------------------|
> | ETH1 |-----------| orgates[1]------->|inpin[1]|---------->outpin[10]|---------->|128 | |
> | -------->|0 | orgates[2]------->|inpin[2]|---------->outpin[11]|---------->|129 | |
> | ETH2 | 4| orgates[3]------->|inpin[3]|---------->outpin[12]|---------->|130 | |
> | -------->|1 5| orgates[4]------->|inpin[4]|---------->outpin[13]|---------->|131 | |
> | ETH3 | 6|---->orgates[5]------->|inpin[5]|---------->outpin[14]|---------->|132 | |
> | -------->|2 19| orgates[6]------->|inpin[6]|---------->outpin[15]|---------->|133 | |
> | UART0 | 20| orgates[7]------->|inpin[7]|---------->outpin[16]|---------->|134 | |
> | -------->|7 21| orgates[8]------->|inpin[8]|---------->outpin[17]|---------->|135 | |
> | UART1 | 22| orgates[9]------->|inpin[9]|---------->outpin[18]|---------->|136 | |
> | -------->|8 23| |------------------------------| |----------| |
> | UART2 | 24| |
> | -------->|9 25| AST2700 A0 Design |
> | UART3 | 26| |
> | -------->|10 27| |
> | UART5 | 28| |
> | -------->|11 29| GICINT132 |
> | UART6 | | |
> | -------->|12 30| |
> | UART7 | 31| |
> | -------->|13 | |
> | UART8 | OR[0:31] | |
> | -------->|14 | |
> | UART9 | | |
> | -------->|15 | |
> | UART10 | | |
> | -------->|16 | |
> | UART11 | | |
> | -------->|17 | |
> | UART12 | | |
> | -------->|18 | |
> | |-----------| |
> | |
> |-------------------------------------------------------------------------------------------------------|
> >
Thanks, I'll consider this updated diagram as well while I put my own
together from the other pieces of info you've provided.
Andrew
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
2025-02-05 23:39 ` Andrew Jeffery
@ 2025-02-06 4:55 ` Joel Stanley
2025-02-06 5:15 ` Jamin Lin
0 siblings, 1 reply; 54+ messages in thread
From: Joel Stanley @ 2025-02-06 4:55 UTC (permalink / raw)
To: Jamin Lin
Cc: Andrew Jeffery, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, open list:ASPEED BMCs, open list:All patches CC here,
Troy Lee, Yunlin Tang
Hi Jamin,
On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery <andrew@codeconstruct.com.au> wrote:
> Thanks, I'll consider this updated diagram as well while I put my own
> together from the other pieces of info you've provided.
When you send the next version, please try to separate your code
cleanups and minor renames into a different patch. It makes it easier
to see what you're adding.
Thanks,
Joel
^ permalink raw reply [flat|nested] 54+ messages in thread
* RE: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
2025-02-06 4:55 ` Joel Stanley
@ 2025-02-06 5:15 ` Jamin Lin
2025-02-06 7:17 ` Cédric Le Goater
0 siblings, 1 reply; 54+ messages in thread
From: Jamin Lin @ 2025-02-06 5:15 UTC (permalink / raw)
To: Joel Stanley
Cc: Andrew Jeffery, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, open list:ASPEED BMCs, open list:All patches CC here,
Troy Lee, Yunlin Tang
Hi Joel,
> From: Joel Stanley <joel@jms.id.au>
> Sent: Thursday, February 6, 2025 12:55 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>
> Cc: Andrew Jeffery <andrew@codeconstruct.com.au>; Cédric Le Goater
> <clg@kaod.org>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; open
> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>; Yunlin
> Tang <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of
> INTC controllers for AST2700 A1
>
> Hi Jamin,
>
> On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery <andrew@codeconstruct.com.au>
> wrote:
> > Thanks, I'll consider this updated diagram as well while I put my own
> > together from the other pieces of info you've provided.
>
> When you send the next version, please try to separate your code cleanups and
> minor renames into a different patch. It makes it easier to see what you're
> adding.
>
> Thanks,
>
> Joel
Thanks for suggestion. Cedric, also made the same suggestion in patch 0,
https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jamin_lin@aspeedtech.com/
I think I will re-send this first.
1. INTC rename/prereqs/cleanups
hw/intc/aspeed: Rename INTC to INTC0
hw/intc/aspeed: Support different memory region ops
hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0
hw/intc/aspeed: Support setting different memory and register size
hw/intc/aspeed: Introduce helper functions for enable and status registers
hw/intc/aspeed: Add ID to trace events for better debugging
hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0
Jamin
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
2025-02-06 5:15 ` Jamin Lin
@ 2025-02-06 7:17 ` Cédric Le Goater
2025-02-06 7:22 ` Jamin Lin
0 siblings, 1 reply; 54+ messages in thread
From: Cédric Le Goater @ 2025-02-06 7:17 UTC (permalink / raw)
To: Jamin Lin, Joel Stanley
Cc: Andrew Jeffery, Peter Maydell, Steven Lee, Troy Lee,
open list:ASPEED BMCs, open list:All patches CC here, Troy Lee,
Yunlin Tang
On 2/6/25 06:15, Jamin Lin wrote:
> Hi Joel,
>
>> From: Joel Stanley <joel@jms.id.au>
>> Sent: Thursday, February 6, 2025 12:55 PM
>> To: Jamin Lin <jamin_lin@aspeedtech.com>
>> Cc: Andrew Jeffery <andrew@codeconstruct.com.au>; Cédric Le Goater
>> <clg@kaod.org>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee
>> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; open
>> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
>> <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>; Yunlin
>> Tang <yunlin.tang@aspeedtech.com>
>> Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of
>> INTC controllers for AST2700 A1
>>
>> Hi Jamin,
>>
>> On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery <andrew@codeconstruct.com.au>
>> wrote:
>>> Thanks, I'll consider this updated diagram as well while I put my own
>>> together from the other pieces of info you've provided.
>>
>> When you send the next version, please try to separate your code cleanups and
>> minor renames into a different patch. It makes it easier to see what you're
>> adding.
>>
>> Thanks,
>>
>> Joel
>
> Thanks for suggestion. Cedric, also made the same suggestion in patch 0,
> https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jamin_lin@aspeedtech.com/
>
> I think I will re-send this first.
>
> 1. INTC rename/prereqs/cleanups
> hw/intc/aspeed: Rename INTC to INTC0
I thought we were keeping INTC and introducing INTC_IO ? As
you wish.
If we choose to rename INTC to INTC0, I prefer that you send
the series below first.
> hw/intc/aspeed: Support different memory region ops
> hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0
> hw/intc/aspeed: Support setting different memory and register size
> hw/intc/aspeed: Introduce helper functions for enable and status registers
> hw/intc/aspeed: Add ID to trace events for better debugging
> hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0
Thanks,
C.
^ permalink raw reply [flat|nested] 54+ messages in thread
* RE: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
2025-02-06 7:17 ` Cédric Le Goater
@ 2025-02-06 7:22 ` Jamin Lin
0 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin @ 2025-02-06 7:22 UTC (permalink / raw)
To: Cédric Le Goater, Joel Stanley
Cc: Andrew Jeffery, Peter Maydell, Steven Lee, Troy Lee,
open list:ASPEED BMCs, open list:All patches CC here, Troy Lee,
Yunlin Tang
Hi Cedric,
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Thursday, February 6, 2025 3:17 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Joel Stanley <joel@jms.id.au>
> Cc: Andrew Jeffery <andrew@codeconstruct.com.au>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; open list:ASPEED BMCs <qemu-arm@nongnu.org>;
> open list:All patches CC here <qemu-devel@nongnu.org>; Troy Lee
> <troy_lee@aspeedtech.com>; Yunlin Tang <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of
> INTC controllers for AST2700 A1
>
> On 2/6/25 06:15, Jamin Lin wrote:
> > Hi Joel,
> >
> >> From: Joel Stanley <joel@jms.id.au>
> >> Sent: Thursday, February 6, 2025 12:55 PM
> >> To: Jamin Lin <jamin_lin@aspeedtech.com>
> >> Cc: Andrew Jeffery <andrew@codeconstruct.com.au>; Cédric Le Goater
> >> <clg@kaod.org>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> >> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; open
> >> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
> >> <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>; Yunlin
> >> Tang <yunlin.tang@aspeedtech.com>
> >> Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two
> >> levels of INTC controllers for AST2700 A1
> >>
> >> Hi Jamin,
> >>
> >> On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery
> >> <andrew@codeconstruct.com.au>
> >> wrote:
> >>> Thanks, I'll consider this updated diagram as well while I put my
> >>> own together from the other pieces of info you've provided.
> >>
> >> When you send the next version, please try to separate your code
> >> cleanups and minor renames into a different patch. It makes it easier
> >> to see what you're adding.
> >>
> >> Thanks,
> >>
> >> Joel
> >
> > Thanks for suggestion. Cedric, also made the same suggestion in patch
> > 0,
> > https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2
> > 465942-1-jamin_lin@aspeedtech.com/
> >
> > I think I will re-send this first.
>
> >
> > 1. INTC rename/prereqs/cleanups
> > hw/intc/aspeed: Rename INTC to INTC0
>
> I thought we were keeping INTC and introducing INTC_IO ? As you wish.
>
Yes, I am working keeping INTC (CPU Die) and introducing INTC_IO(IO Die).
I understand that INTC0 and INTC1 are very difficult to interpret or distinguish their meanings.
Thanks-Jamin
> If we choose to rename INTC to INTC0, I prefer that you send the series below
> first.
>
>
> > hw/intc/aspeed: Support different memory region ops
> > hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0
> > hw/intc/aspeed: Support setting different memory and register size
> > hw/intc/aspeed: Introduce helper functions for enable and status
> registers
> > hw/intc/aspeed: Add ID to trace events for better debugging
> > hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0
>
> Thanks,
>
> C.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
2025-02-05 7:12 ` Jamin Lin
2025-02-05 23:39 ` Andrew Jeffery
@ 2025-02-06 7:22 ` Cédric Le Goater
2025-02-06 7:24 ` Jamin Lin
1 sibling, 1 reply; 54+ messages in thread
From: Cédric Le Goater @ 2025-02-06 7:22 UTC (permalink / raw)
To: Jamin Lin, Andrew Jeffery, Peter Maydell, Steven Lee, Troy Lee,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
> The design of the OR gates for GICINT 196 is as follows:
> It has interrupt sources ranging from 0 to 31, with its output pin connected to
> INTC_IO "T0 GICINT_196".
> The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4, and
> its bit 4 output should be connected to GIC 196.
> The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following:
> Bit 0 -> GIC 192
> Bit 1 -> GIC 193
> Bit 2 -> GIC 194
> Bit 3 -> GIC 195
> Bit 4 -> GIC 196
>
> Jamin
> |-------------------------------------------------------------------------------------------------------|
> | AST2700 A1 Design |
> | To GICINT196 |
> | |
> | ETH1 |-----------| |--------------------------| |--------------| |
> | -------->|0 | | INTC_IO | | orgates[0] | |
> | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | |
> | -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | |
> | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | |
> | -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| |
> | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | |
> | -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | |
> | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | |
> | -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | |
> | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | |
> | -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | |
> | UART3 | 26| |--------------------------| |--------------| | |
> | ---------|10 27| | |
> | UART5 | 28| | |
> | -------->|11 29| | |
> | UART6 | | | |
> | -------->|12 30| |-----------------------------------------------------------------------| |
> | UART7 | 31| | |
> | -------->|13 | | |
> | UART8 | OR[0:31] | | |------------------------------| |----------| |
> | -------->|14 | | | INTC | | GIC | |
> | UART9 | | | |inpin[0:0]--------->outpin[0] |---------->|192 | |
> | -------->|15 | | |inpin[0:1]--------->outpin[1] |---------->|193 | |
> | UART10 | | | |inpin[0:2]--------->outpin[2] |---------->|194 | |
> | -------->|16 | | |inpin[0:3]--------->outpin[3] |---------->|195 | |
> | UART11 | | |--------------> |inpin[0:4]--------->outpin[4] |---------->|196 | |
> | -------->|17 | |inpin[0:5]--------->outpin[5] |---------->|197 | |
> | UART12 | | |inpin[0:6]--------->outpin[6] |---------->|198 | |
> | -------->|18 | |inpin[0:7]--------->outpin[7] |---------->|199 | |
> | |-----------| |inpin[0:8]--------->outpin[8] |---------->|200 | |
> | |inpin[0:9]--------->outpin[9] |---------->|201 | |
> |-------------------------------------------------------------------------------------------------------|
> |-------------------------------------------------------------------------------------------------------|
> | ETH1 |-----------| orgates[1]------->|inpin[1]|---------->outpin[10]|---------->|128 | |
> | -------->|0 | orgates[2]------->|inpin[2]|---------->outpin[11]|---------->|129 | |
> | ETH2 | 4| orgates[3]------->|inpin[3]|---------->outpin[12]|---------->|130 | |
> | -------->|1 5| orgates[4]------->|inpin[4]|---------->outpin[13]|---------->|131 | |
> | ETH3 | 6|---->orgates[5]------->|inpin[5]|---------->outpin[14]|---------->|132 | |
> | -------->|2 19| orgates[6]------->|inpin[6]|---------->outpin[15]|---------->|133 | |
> | UART0 | 20| orgates[7]------->|inpin[7]|---------->outpin[16]|---------->|134 | |
> | -------->|7 21| orgates[8]------->|inpin[8]|---------->outpin[17]|---------->|135 | |
> | UART1 | 22| orgates[9]------->|inpin[9]|---------->outpin[18]|---------->|136 | |
> | -------->|8 23| |------------------------------| |----------| |
> | UART2 | 24| |
> | -------->|9 25| AST2700 A0 Design |
> | UART3 | 26| |
> | -------->|10 27| |
> | UART5 | 28| |
> | -------->|11 29| GICINT132 |
> | UART6 | | |
> | -------->|12 30| |
> | UART7 | 31| |
> | -------->|13 | |
> | UART8 | OR[0:31] | |
> | -------->|14 | |
> | UART9 | | |
> | -------->|15 | |
> | UART10 | | |
> | -------->|16 | |
> | UART11 | | |
> | -------->|17 | |
> | UART12 | | |
> | -------->|18 | |
> | |-----------| |
> | |
> |-------------------------------------------------------------------------------------------------------|
Nice ! When you send the intc series for ast2700a1 support, could you
please include this diagram in file docs/specs/aspeed-intc.rst with
some description ? The text could be the same as the cover letter.
Thanks,
C.
^ permalink raw reply [flat|nested] 54+ messages in thread
* RE: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
2025-02-06 7:22 ` Cédric Le Goater
@ 2025-02-06 7:24 ` Jamin Lin
0 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin @ 2025-02-06 7:24 UTC (permalink / raw)
To: Cédric Le Goater, Andrew Jeffery, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hi Cedric,
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Thursday, February 6, 2025 3:23 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Andrew Jeffery
> <andrew@codeconstruct.com.au>; Peter Maydell <peter.maydell@linaro.org>;
> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>;
> Joel Stanley <joel@jms.id.au>; open list:ASPEED BMCs
> <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of
> INTC controllers for AST2700 A1
>
> > The design of the OR gates for GICINT 196 is as follows:
> > It has interrupt sources ranging from 0 to 31, with its output pin
> > connected to INTC_IO "T0 GICINT_196".
> > The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4,
> > and its bit 4 output should be connected to GIC 196.
> > The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as
> following:
> > Bit 0 -> GIC 192
> > Bit 1 -> GIC 193
> > Bit 2 -> GIC 194
> > Bit 3 -> GIC 195
> > Bit 4 -> GIC 196
> >
> > Jamin
> >
> |-----------------------------------------------------------------------------------------------------
> --|
> > |
> AST2700 A1 Design |
> > | To GICINT196
> |
> > |
> |
> > | ETH1 |-----------|
> |--------------------------| |--------------| |
> > | -------->|0 | |
> INTC_IO | | orgates[0] | |
> > | ETH2 | 4|
> orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | |
> > | -------->|1 5|
> orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | |
> > | ETH3 | 6|
> orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | |
> > | -------->|2 19|
> orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| |
> > | UART0 |
> 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 |
> | |
> > | -------->|7 21|
> orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | |
> > | UART1 | 22|
> orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | |
> > | -------->|8 23|
> orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | |
> > | UART2 | 24|
> orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | |
> > | -------->|9 25|
> orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | |
> > | UART3 | 26|
> |--------------------------| |--------------| | |
> > | ---------|10 27|
> | |
> > | UART5 | 28|
> | |
> > | -------->|11 29|
> | |
> > | UART6 | |
> | |
> > | -------->|12 30|
> |-----------------------------------------------------------------------| |
> > | UART7 | 31| |
> |
> > | -------->|13 | |
> |
> > | UART8 | OR[0:31] | |
> |------------------------------| |----------| |
> > | -------->|14 | | |
> INTC | | GIC | |
> > | UART9 | | |
> |inpin[0:0]--------->outpin[0] |---------->|192 | |
> > | -------->|15 | |
> |inpin[0:1]--------->outpin[1] |---------->|193 | |
> > | UART10 | | |
> |inpin[0:2]--------->outpin[2] |---------->|194 | |
> > | -------->|16 | |
> |inpin[0:3]--------->outpin[3] |---------->|195 | |
> > | UART11 | | |-------------->
> |inpin[0:4]--------->outpin[4] |---------->|196 | |
> > | -------->|17 |
> |inpin[0:5]--------->outpin[5] |---------->|197 | |
> > | UART12 | |
> |inpin[0:6]--------->outpin[6] |---------->|198 | |
> > | -------->|18 |
> |inpin[0:7]--------->outpin[7] |---------->|199 | |
> > | |-----------|
> |inpin[0:8]--------->outpin[8] |---------->|200 | |
> > |
> |inpin[0:9]--------->outpin[9] |---------->|201 | |
> >
> |-----------------------------------------------------------------------------------------------------
> --|
> >
> |-----------------------------------------------------------------------------------------------------
> --|
> > | ETH1 |-----------|
> orgates[1]------->|inpin[1]|---------->outpin[10]|---------->|128 | |
> > | -------->|0 |
> orgates[2]------->|inpin[2]|---------->outpin[11]|---------->|129 | |
> > | ETH2 | 4|
> orgates[3]------->|inpin[3]|---------->outpin[12]|---------->|130 | |
> > | -------->|1 5|
> orgates[4]------->|inpin[4]|---------->outpin[13]|---------->|131 | |
> > | ETH3 |
> 6|---->orgates[5]------->|inpin[5]|---------->outpin[14]|---------->|132 |
> |
> > | -------->|2 19|
> orgates[6]------->|inpin[6]|---------->outpin[15]|---------->|133 | |
> > | UART0 | 20|
> orgates[7]------->|inpin[7]|---------->outpin[16]|---------->|134 | |
> > | -------->|7 21|
> orgates[8]------->|inpin[8]|---------->outpin[17]|---------->|135 | |
> > | UART1 | 22|
> orgates[9]------->|inpin[9]|---------->outpin[18]|---------->|136 | |
> > | -------->|8 23|
> |------------------------------| |----------| |
> > | UART2 | 24|
> |
> > | -------->|9 25| AST2700 A0
> Design |
> > | UART3 | 26|
> |
> > | -------->|10 27|
> |
> > | UART5 | 28|
> |
> > | -------->|11 29| GICINT132
> |
> > | UART6 | |
> |
> > | -------->|12 30|
> |
> > | UART7 | 31|
> |
> > | -------->|13 |
> |
> > | UART8 | OR[0:31] |
> |
> > | -------->|14 |
> |
> > | UART9 | |
> |
> > | -------->|15 |
> |
> > | UART10 | |
> |
> > | -------->|16 |
> |
> > | UART11 | |
> |
> > | -------->|17 |
> |
> > | UART12 | |
> |
> > | -------->|18 |
> |
> > | |-----------|
> |
> > |
> |
> >
> > |---------------------------------------------------------------------
> > ----------------------------------|
>
>
> Nice ! When you send the intc series for ast2700a1 support, could you please
> include this diagram in file docs/specs/aspeed-intc.rst with some description ?
> The text could be the same as the cover letter.
>
Will add
Thanks for suggestion
Jamin
>
> Thanks,
>
> C.
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v1 13/18] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (11 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1 Jamin Lin via
` (5 subsequent siblings)
18 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 8 ++++----
hw/arm/aspeed_ast27x0.c | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index ae0405c654..402d55c556 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1654,12 +1654,12 @@ static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
TYPE_TMP105, 0x4d);
}
-static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data)
+static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
- mc->desc = "Aspeed AST2700 EVB (Cortex-A35)";
+ mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)";
amc->soc_name = "ast2700-a0";
amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
@@ -1795,9 +1795,9 @@ static const TypeInfo aspeed_machine_types[] = {
.class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
#ifdef TARGET_AARCH64
}, {
- .name = MACHINE_TYPE_NAME("ast2700-evb"),
+ .name = MACHINE_TYPE_NAME("ast2700a0-evb"),
.parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_ast2700_evb_class_init,
+ .class_init = aspeed_machine_ast2700a0_evb_class_init,
#endif
}, {
.name = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index a95fed30cf..b32c4fcc35 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -73,7 +73,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
#define AST2700_MAX_IRQ 256
/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
-static const int aspeed_soc_ast2700_irqmap[] = {
+static const int aspeed_soc_ast2700a0_irqmap[] = {
[ASPEED_DEV_UART0] = 132,
[ASPEED_DEV_UART1] = 132,
[ASPEED_DEV_UART2] = 132,
@@ -794,7 +794,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("ast2700.io", 0x0, 0x4000000);
}
-static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data)
+static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a35"),
@@ -817,7 +817,7 @@ static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data)
sc->uarts_num = 13;
sc->num_cpus = 4;
sc->uarts_base = ASPEED_DEV_UART0;
- sc->irqmap = aspeed_soc_ast2700_irqmap;
+ sc->irqmap = aspeed_soc_ast2700a0_irqmap;
sc->memmap = aspeed_soc_ast2700_memmap;
sc->get_irq = aspeed_soc_ast2700_get_irq;
}
@@ -832,7 +832,7 @@ static const TypeInfo aspeed_soc_ast27x0_types[] = {
.name = "ast2700-a0",
.parent = TYPE_ASPEED27X0_SOC,
.instance_init = aspeed_soc_ast2700_init,
- .class_init = aspeed_soc_ast2700_class_init,
+ .class_init = aspeed_soc_ast2700a0_class_init,
},
};
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (12 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 13/18] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-30 4:22 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 15/18] hw/misc/aspeed_hace: Fix coding style Jamin Lin via
` (4 subsequent siblings)
18 siblings, 1 reply; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
The memory map for AST2700 A1 remains compatible with AST2700 A0.
However, the IRQ mapping has been updated for AST2700 A1, with GIC interrupts
now ranging from 192 to 201. Add a new IRQ map table for AST2700 A1.
Introduce "aspeed_machine_ast2700_evb_class_init" to initialize the AST2700 EVB
machine. Add "aspeed_soc_ast2700_class_init" to initialize the AST2700 A1 SoC.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 24 +++++++++++++
hw/arm/aspeed_ast27x0.c | 80 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 104 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 402d55c556..254fa5316d 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1672,6 +1672,26 @@ static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, void *data)
mc->default_ram_size = 1 * GiB;
aspeed_machine_class_init_cpus_defaults(mc);
}
+
+static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Aspeed AST2700 EVB (Cortex-A35)";
+ amc->soc_name = "ast2700-a1";
+ amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
+ amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
+ amc->fmc_model = "w25q01jvq";
+ amc->spi_model = "w25q512jv";
+ amc->num_cs = 2;
+ amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
+ amc->uart_default = ASPEED_DEV_UART12;
+ amc->i2c_init = ast2700_evb_i2c_init;
+ mc->default_ram_size = 1 * GiB;
+ aspeed_machine_class_init_cpus_defaults(mc);
+}
+
#endif
static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
@@ -1798,6 +1818,10 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("ast2700a0-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2700a0_evb_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("ast2700-evb"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_ast2700_evb_class_init,
#endif
}, {
.name = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index b32c4fcc35..e0a29c9053 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -119,6 +119,52 @@ static const int aspeed_soc_ast2700a0_irqmap[] = {
[ASPEED_DEV_SDHCI] = 133,
};
+static const int aspeed_soc_ast2700_irqmap[] = {
+ [ASPEED_DEV_UART0] = 196,
+ [ASPEED_DEV_UART1] = 196,
+ [ASPEED_DEV_UART2] = 196,
+ [ASPEED_DEV_UART3] = 196,
+ [ASPEED_DEV_UART4] = 8,
+ [ASPEED_DEV_UART5] = 196,
+ [ASPEED_DEV_UART6] = 196,
+ [ASPEED_DEV_UART7] = 196,
+ [ASPEED_DEV_UART8] = 196,
+ [ASPEED_DEV_UART9] = 196,
+ [ASPEED_DEV_UART10] = 196,
+ [ASPEED_DEV_UART11] = 196,
+ [ASPEED_DEV_UART12] = 196,
+ [ASPEED_DEV_FMC] = 195,
+ [ASPEED_DEV_SDMC] = 0,
+ [ASPEED_DEV_SCU] = 12,
+ [ASPEED_DEV_ADC] = 194,
+ [ASPEED_DEV_XDMA] = 5,
+ [ASPEED_DEV_EMMC] = 15,
+ [ASPEED_DEV_GPIO] = 194,
+ [ASPEED_DEV_RTC] = 13,
+ [ASPEED_DEV_TIMER1] = 16,
+ [ASPEED_DEV_TIMER2] = 17,
+ [ASPEED_DEV_TIMER3] = 18,
+ [ASPEED_DEV_TIMER4] = 19,
+ [ASPEED_DEV_TIMER5] = 20,
+ [ASPEED_DEV_TIMER6] = 21,
+ [ASPEED_DEV_TIMER7] = 22,
+ [ASPEED_DEV_TIMER8] = 23,
+ [ASPEED_DEV_WDT] = 195,
+ [ASPEED_DEV_PWM] = 195,
+ [ASPEED_DEV_LPC] = 192,
+ [ASPEED_DEV_IBT] = 192,
+ [ASPEED_DEV_I2C] = 194,
+ [ASPEED_DEV_PECI] = 197,
+ [ASPEED_DEV_ETH1] = 196,
+ [ASPEED_DEV_ETH2] = 196,
+ [ASPEED_DEV_ETH3] = 196,
+ [ASPEED_DEV_HACE] = 4,
+ [ASPEED_DEV_KCS] = 192,
+ [ASPEED_DEV_DP] = 28,
+ [ASPEED_DEV_I3C] = 195,
+ [ASPEED_DEV_SDHCI] = 197,
+};
+
/* GICINT 128 */
/* GICINT 192 */
static const int ast2700_gic128_gic192_intcmap[] = {
@@ -822,6 +868,34 @@ static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data)
sc->get_irq = aspeed_soc_ast2700_get_irq;
}
+static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data)
+{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a35"),
+ NULL
+ };
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+
+ /* Reason: The Aspeed SoC can only be instantiated from a board */
+ dc->user_creatable = false;
+ dc->realize = aspeed_soc_ast2700_realize;
+
+ sc->name = "ast2700-a1";
+ sc->valid_cpu_types = valid_cpu_types;
+ sc->silicon_rev = AST2700_A1_SILICON_REV;
+ sc->sram_size = 0x20000;
+ sc->spis_num = 3;
+ sc->wdts_num = 8;
+ sc->macs_num = 1;
+ sc->uarts_num = 13;
+ sc->num_cpus = 4;
+ sc->uarts_base = ASPEED_DEV_UART0;
+ sc->irqmap = aspeed_soc_ast2700_irqmap;
+ sc->memmap = aspeed_soc_ast2700_memmap;
+ sc->get_irq = aspeed_soc_ast2700_get_irq;
+}
+
static const TypeInfo aspeed_soc_ast27x0_types[] = {
{
.name = TYPE_ASPEED27X0_SOC,
@@ -834,6 +908,12 @@ static const TypeInfo aspeed_soc_ast27x0_types[] = {
.instance_init = aspeed_soc_ast2700_init,
.class_init = aspeed_soc_ast2700a0_class_init,
},
+ {
+ .name = "ast2700-a1",
+ .parent = TYPE_ASPEED27X0_SOC,
+ .instance_init = aspeed_soc_ast2700_init,
+ .class_init = aspeed_soc_ast2700_class_init,
+ },
};
DEFINE_TYPES(aspeed_soc_ast27x0_types)
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1
2025-01-21 7:04 ` [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1 Jamin Lin via
@ 2025-01-30 4:22 ` Andrew Jeffery
2025-02-03 8:55 ` Jamin Lin
0 siblings, 1 reply; 54+ messages in thread
From: Andrew Jeffery @ 2025-01-30 4:22 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The memory map for AST2700 A1 remains compatible with AST2700 A0.
> However, the IRQ mapping has been updated for AST2700 A1, with GIC
> interrupts
> now ranging from 192 to 201. Add a new IRQ map table for AST2700 A1.
>
> Introduce "aspeed_machine_ast2700_evb_class_init" to initialize the
> AST2700 EVB
> machine. Add "aspeed_soc_ast2700_class_init" to initialize the
> AST2700 A1 SoC.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> hw/arm/aspeed.c | 24 +++++++++++++
> hw/arm/aspeed_ast27x0.c | 80
> +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 104 insertions(+)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 402d55c556..254fa5316d 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1672,6 +1672,26 @@ static void
> aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, void *data)
> mc->default_ram_size = 1 * GiB;
> aspeed_machine_class_init_cpus_defaults(mc);
> }
> +
> +static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc,
> void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
> +
> + mc->desc = "Aspeed AST2700 EVB (Cortex-A35)";
> + amc->soc_name = "ast2700-a1";
> + amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
> + amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
> + amc->fmc_model = "w25q01jvq";
> + amc->spi_model = "w25q512jv";
> + amc->num_cs = 2;
> + amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON |
> ASPEED_MAC2_ON;
> + amc->uart_default = ASPEED_DEV_UART12;
> + amc->i2c_init = ast2700_evb_i2c_init;
> + mc->default_ram_size = 1 * GiB;
> + aspeed_machine_class_init_cpus_defaults(mc);
> +}
> +
> #endif
>
> static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass
> *oc,
> @@ -1798,6 +1818,10 @@ static const TypeInfo aspeed_machine_types[] =
> {
> .name = MACHINE_TYPE_NAME("ast2700a0-evb"),
> .parent = TYPE_ASPEED_MACHINE,
> .class_init = aspeed_machine_ast2700a0_evb_class_init,
> + }, {
> + .name = MACHINE_TYPE_NAME("ast2700-evb"),
> + .parent = TYPE_ASPEED_MACHINE,
> + .class_init = aspeed_machine_ast2700_evb_class_init,
> #endif
> }, {
> .name = TYPE_ASPEED_MACHINE,
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index b32c4fcc35..e0a29c9053 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -119,6 +119,52 @@ static const int aspeed_soc_ast2700a0_irqmap[] =
> {
> [ASPEED_DEV_SDHCI] = 133,
> };
>
> +static const int aspeed_soc_ast2700_irqmap[] = {
> + [ASPEED_DEV_UART0] = 196,
> + [ASPEED_DEV_UART1] = 196,
> + [ASPEED_DEV_UART2] = 196,
> + [ASPEED_DEV_UART3] = 196,
> + [ASPEED_DEV_UART4] = 8,
> + [ASPEED_DEV_UART5] = 196,
> + [ASPEED_DEV_UART6] = 196,
> + [ASPEED_DEV_UART7] = 196,
> + [ASPEED_DEV_UART8] = 196,
> + [ASPEED_DEV_UART9] = 196,
> + [ASPEED_DEV_UART10] = 196,
> + [ASPEED_DEV_UART11] = 196,
> + [ASPEED_DEV_UART12] = 196,
> + [ASPEED_DEV_FMC] = 195,
> + [ASPEED_DEV_SDMC] = 0,
> + [ASPEED_DEV_SCU] = 12,
> + [ASPEED_DEV_ADC] = 194,
> + [ASPEED_DEV_XDMA] = 5,
> + [ASPEED_DEV_EMMC] = 15,
> + [ASPEED_DEV_GPIO] = 194,
> + [ASPEED_DEV_RTC] = 13,
> + [ASPEED_DEV_TIMER1] = 16,
> + [ASPEED_DEV_TIMER2] = 17,
> + [ASPEED_DEV_TIMER3] = 18,
> + [ASPEED_DEV_TIMER4] = 19,
> + [ASPEED_DEV_TIMER5] = 20,
> + [ASPEED_DEV_TIMER6] = 21,
> + [ASPEED_DEV_TIMER7] = 22,
> + [ASPEED_DEV_TIMER8] = 23,
> + [ASPEED_DEV_WDT] = 195,
> + [ASPEED_DEV_PWM] = 195,
> + [ASPEED_DEV_LPC] = 192,
> + [ASPEED_DEV_IBT] = 192,
> + [ASPEED_DEV_I2C] = 194,
> + [ASPEED_DEV_PECI] = 197,
> + [ASPEED_DEV_ETH1] = 196,
> + [ASPEED_DEV_ETH2] = 196,
> + [ASPEED_DEV_ETH3] = 196,
> + [ASPEED_DEV_HACE] = 4,
> + [ASPEED_DEV_KCS] = 192,
> + [ASPEED_DEV_DP] = 28,
> + [ASPEED_DEV_I3C] = 195,
> + [ASPEED_DEV_SDHCI] = 197,
> +};
Bit of a nit, but can we sort this table? Perhaps by interrupt value?
Andrew
^ permalink raw reply [flat|nested] 54+ messages in thread* RE: [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1
2025-01-30 4:22 ` Andrew Jeffery
@ 2025-02-03 8:55 ` Jamin Lin
0 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin @ 2025-02-03 8:55 UTC (permalink / raw)
To: Andrew Jeffery, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hi Andrew,
> From: Andrew Jeffery <andrew@codeconstruct.com.au>
> Sent: Thursday, January 30, 2025 12:22 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
> Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Joel Stanley
> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support
> for AST2700 A1
>
> On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> > The memory map for AST2700 A1 remains compatible with AST2700 A0.
> > However, the IRQ mapping has been updated for AST2700 A1, with GIC
> > interrupts now ranging from 192 to 201. Add a new IRQ map table for
> > AST2700 A1.
> >
> > Introduce "aspeed_machine_ast2700_evb_class_init" to initialize the
> > AST2700 EVB
> > machine. Add "aspeed_soc_ast2700_class_init" to initialize the
> > AST2700 A1 SoC.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> > hw/arm/aspeed.c | 24 +++++++++++++
> > hw/arm/aspeed_ast27x0.c | 80
> > +++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 104 insertions(+)
> >
> > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index
> > 402d55c556..254fa5316d 100644
> > --- a/hw/arm/aspeed.c
> > +++ b/hw/arm/aspeed.c
> > @@ -1672,6 +1672,26 @@ static void
> > aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, void *data)
> > mc->default_ram_size = 1 * GiB;
> > aspeed_machine_class_init_cpus_defaults(mc);
> > }
> > +
> > +static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc,
> > void *data)
> > +{
> > + MachineClass *mc = MACHINE_CLASS(oc);
> > + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
> > +
> > + mc->desc = "Aspeed AST2700 EVB (Cortex-A35)";
> > + amc->soc_name = "ast2700-a1";
> > + amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
> > + amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
> > + amc->fmc_model = "w25q01jvq";
> > + amc->spi_model = "w25q512jv";
> > + amc->num_cs = 2;
> > + amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON |
> > ASPEED_MAC2_ON;
> > + amc->uart_default = ASPEED_DEV_UART12;
> > + amc->i2c_init = ast2700_evb_i2c_init;
> > + mc->default_ram_size = 1 * GiB;
> > + aspeed_machine_class_init_cpus_defaults(mc);
> > +}
> > +
> > #endif
> >
> > static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass
> > *oc,
> > @@ -1798,6 +1818,10 @@ static const TypeInfo aspeed_machine_types[] =
> > {
> > .name =
> MACHINE_TYPE_NAME("ast2700a0-evb"),
> > .parent = TYPE_ASPEED_MACHINE,
> > .class_init = aspeed_machine_ast2700a0_evb_class_init,
> > + }, {
> > + .name = MACHINE_TYPE_NAME("ast2700-evb"),
> > + .parent = TYPE_ASPEED_MACHINE,
> > + .class_init = aspeed_machine_ast2700_evb_class_init,
> > #endif
> > }, {
> > .name = TYPE_ASPEED_MACHINE, diff --git
> > a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index
> > b32c4fcc35..e0a29c9053 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -119,6 +119,52 @@ static const int aspeed_soc_ast2700a0_irqmap[] =
> > {
> > [ASPEED_DEV_SDHCI] = 133,
> > };
> >
> > +static const int aspeed_soc_ast2700_irqmap[] = {
> > + [ASPEED_DEV_UART0] = 196,
> > + [ASPEED_DEV_UART1] = 196,
> > + [ASPEED_DEV_UART2] = 196,
> > + [ASPEED_DEV_UART3] = 196,
> > + [ASPEED_DEV_UART4] = 8,
> > + [ASPEED_DEV_UART5] = 196,
> > + [ASPEED_DEV_UART6] = 196,
> > + [ASPEED_DEV_UART7] = 196,
> > + [ASPEED_DEV_UART8] = 196,
> > + [ASPEED_DEV_UART9] = 196,
> > + [ASPEED_DEV_UART10] = 196,
> > + [ASPEED_DEV_UART11] = 196,
> > + [ASPEED_DEV_UART12] = 196,
> > + [ASPEED_DEV_FMC] = 195,
> > + [ASPEED_DEV_SDMC] = 0,
> > + [ASPEED_DEV_SCU] = 12,
> > + [ASPEED_DEV_ADC] = 194,
> > + [ASPEED_DEV_XDMA] = 5,
> > + [ASPEED_DEV_EMMC] = 15,
> > + [ASPEED_DEV_GPIO] = 194,
> > + [ASPEED_DEV_RTC] = 13,
> > + [ASPEED_DEV_TIMER1] = 16,
> > + [ASPEED_DEV_TIMER2] = 17,
> > + [ASPEED_DEV_TIMER3] = 18,
> > + [ASPEED_DEV_TIMER4] = 19,
> > + [ASPEED_DEV_TIMER5] = 20,
> > + [ASPEED_DEV_TIMER6] = 21,
> > + [ASPEED_DEV_TIMER7] = 22,
> > + [ASPEED_DEV_TIMER8] = 23,
> > + [ASPEED_DEV_WDT] = 195,
> > + [ASPEED_DEV_PWM] = 195,
> > + [ASPEED_DEV_LPC] = 192,
> > + [ASPEED_DEV_IBT] = 192,
> > + [ASPEED_DEV_I2C] = 194,
> > + [ASPEED_DEV_PECI] = 197,
> > + [ASPEED_DEV_ETH1] = 196,
> > + [ASPEED_DEV_ETH2] = 196,
> > + [ASPEED_DEV_ETH3] = 196,
> > + [ASPEED_DEV_HACE] = 4,
> > + [ASPEED_DEV_KCS] = 192,
> > + [ASPEED_DEV_DP] = 28,
> > + [ASPEED_DEV_I3C] = 195,
> > + [ASPEED_DEV_SDHCI] = 197,
> > +};
>
> Bit of a nit, but can we sort this table? Perhaps by interrupt value?
Thanks for review and suggestion.
Will update this table
Jamin
>
> Andrew
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v1 15/18] hw/misc/aspeed_hace: Fix coding style
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (13 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1 Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support Jamin Lin via
` (3 subsequent siblings)
18 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_hace.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index e3f7df2e86..18b85081c7 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -75,9 +75,12 @@ static const struct {
{ HASH_ALGO_SHA1, QCRYPTO_HASH_ALGO_SHA1 },
{ HASH_ALGO_SHA224, QCRYPTO_HASH_ALGO_SHA224 },
{ HASH_ALGO_SHA256, QCRYPTO_HASH_ALGO_SHA256 },
- { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA512, QCRYPTO_HASH_ALGO_SHA512 },
- { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA384, QCRYPTO_HASH_ALGO_SHA384 },
- { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA256, QCRYPTO_HASH_ALGO_SHA256 },
+ { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA512,
+ QCRYPTO_HASH_ALGO_SHA512 },
+ { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA384,
+ QCRYPTO_HASH_ALGO_SHA384 },
+ { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA256,
+ QCRYPTO_HASH_ALGO_SHA256 },
};
static int hash_algo_lookup(uint32_t reg)
@@ -201,7 +204,8 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
haddr = address_space_map(&s->dram_as, addr, &plen, false,
MEMTXATTRS_UNSPECIFIED);
if (haddr == NULL) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: qcrypto failed\n", __func__);
return;
}
iov[i].iov_base = haddr;
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (14 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 15/18] hw/misc/aspeed_hace: Fix coding style Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-30 4:30 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700 Jamin Lin via
` (2 subsequent siblings)
18 siblings, 1 reply; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_hace.c | 20 ++++++++++++++++++++
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 18b85081c7..86422cb3be 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -552,12 +552,32 @@ static const TypeInfo aspeed_ast1030_hace_info = {
.class_init = aspeed_ast1030_hace_class_init,
};
+static void aspeed_ast2700_hace_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass);
+
+ dc->desc = "AST2700 Hash and Crypto Engine";
+
+ ahc->src_mask = 0x7FFFFFFF;
+ ahc->dest_mask = 0x7FFFFFF8;
+ ahc->key_mask = 0x7FFFFFF8;
+ ahc->hash_mask = 0x00147FFF;
+}
+
+static const TypeInfo aspeed_ast2700_hace_info = {
+ .name = TYPE_ASPEED_AST2700_HACE,
+ .parent = TYPE_ASPEED_HACE,
+ .class_init = aspeed_ast2700_hace_class_init,
+};
+
static void aspeed_hace_register_types(void)
{
type_register_static(&aspeed_ast2400_hace_info);
type_register_static(&aspeed_ast2500_hace_info);
type_register_static(&aspeed_ast2600_hace_info);
type_register_static(&aspeed_ast1030_hace_info);
+ type_register_static(&aspeed_ast2700_hace_info);
type_register_static(&aspeed_hace_info);
}
diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h
index 4af9919195..d13fd3da07 100644
--- a/include/hw/misc/aspeed_hace.h
+++ b/include/hw/misc/aspeed_hace.h
@@ -18,6 +18,7 @@
#define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500"
#define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600"
#define TYPE_ASPEED_AST1030_HACE TYPE_ASPEED_HACE "-ast1030"
+#define TYPE_ASPEED_AST2700_HACE TYPE_ASPEED_HACE "-ast2700"
OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE)
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support
2025-01-21 7:04 ` [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support Jamin Lin via
@ 2025-01-30 4:30 ` Andrew Jeffery
0 siblings, 0 replies; 54+ messages in thread
From: Andrew Jeffery @ 2025-01-30 4:30 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> Introduce a new ast2700 class to support AST2700.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (15 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-30 4:32 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 18/18] hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self Test(WORKAROUND) Jamin Lin via
2025-01-31 7:34 ` [PATCH v1 00/18] Support AST2700 A1 Cédric Le Goater
18 siblings, 1 reply; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
The HACE controller between AST2600 and AST2700 are almost identical.
The HACE controller registers base address starts at 0x1207_0000 and
its alarm interrupt is connected to GICINT4.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index e0a29c9053..0b82b2eab5 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -68,6 +68,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_SDHCI] = 0x14080000,
[ASPEED_DEV_TIMER1] = 0x12C10000,
[ASPEED_DEV_INTC1] = 0x14C18000,
+ [ASPEED_DEV_HACE] = 0x12070000,
};
#define AST2700_MAX_IRQ 256
@@ -478,6 +479,9 @@ static void aspeed_soc_ast2700_init(Object *obj)
snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
+
+ snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
+ object_initialize_child(obj, "hace", &s->hace, typename);
}
/*
@@ -833,6 +837,17 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
}
+ /* HACE */
+ object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
+ sc->memmap[ASPEED_DEV_HACE]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
+
create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700
2025-01-21 7:04 ` [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700 Jamin Lin via
@ 2025-01-30 4:32 ` Andrew Jeffery
0 siblings, 0 replies; 54+ messages in thread
From: Andrew Jeffery @ 2025-01-30 4:32 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The HACE controller between AST2600 and AST2700 are almost identical.
> The HACE controller registers base address starts at 0x1207_0000 and
> its alarm interrupt is connected to GICINT4.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v1 18/18] hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self Test(WORKAROUND)
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (16 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700 Jamin Lin via
@ 2025-01-21 7:04 ` Jamin Lin via
2025-01-31 7:34 ` [PATCH v1 00/18] Support AST2700 A1 Cédric Le Goater
18 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin via @ 2025-01-21 7:04 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
Currently, it does not support the CRYPT command.
Instead, it only sends an interrupt to notify the firmware
that the crypt command has completed.
It is a temporary workaround to resolve the boot issue in
the Crypto Manager Self Test.
Full support for the CRYPT command will be implemented in the future.
It only for reviewer testing and please drop this patch.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_hace.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 86422cb3be..c3ec6179b9 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -58,6 +58,7 @@
#define HASH_HASH_THEN_CRYPT (BIT(0) | BIT(1))
/* Other cmd bits */
#define HASH_IRQ_EN BIT(9)
+#define CRYPT_IRQ_EN BIT(12)
#define HASH_SG_EN BIT(18)
/* Scatter-gather data list */
#define SG_LIST_LEN_SIZE 4
@@ -343,6 +344,13 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
qemu_irq_lower(s->irq);
}
}
+ if (data & CRYPT_IRQ) {
+ data &= ~CRYPT_IRQ;
+
+ if (s->regs[addr] & CRYPT_IRQ) {
+ qemu_irq_lower(s->irq);
+ }
+ }
break;
case R_HASH_SRC:
data &= ahc->src_mask;
@@ -388,6 +396,10 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
case R_CRYPT_CMD:
qemu_log_mask(LOG_UNIMP, "%s: Crypt commands not implemented\n",
__func__);
+ s->regs[R_STATUS] |= CRYPT_IRQ;
+ if (data & CRYPT_IRQ_EN) {
+ qemu_irq_raise(s->irq);
+ }
break;
default:
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH v1 00/18] Support AST2700 A1
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
` (17 preceding siblings ...)
2025-01-21 7:04 ` [PATCH v1 18/18] hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self Test(WORKAROUND) Jamin Lin via
@ 2025-01-31 7:34 ` Cédric Le Goater
2025-02-04 8:05 ` Jamin Lin
2025-06-30 20:28 ` Cédric Le Goater
18 siblings, 2 replies; 54+ messages in thread
From: Cédric Le Goater @ 2025-01-31 7:34 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
Hello Jamin,
On 1/21/25 08:04, Jamin Lin wrote:
> v1:
> 1. Refactor INTC model to support both INTC0 and INTC1.
> 2. Support AST2700 A1.
> 3. Create ast2700a0-evb machine.
>
> With the patch applied, QEMU now supports two machines for running AST2700 SoCs:
> ast2700a0-evb: Designed for AST2700 A0
> ast2700-evb: Designed for AST2700 A1
Let's do that progressively, please add a new ast2700a1-evb machine too and
a machine alias on ast2700a0-evb. Then we will change the alias on the newer
SoC.
>
> Test information
> 1. QEMU version: https://github.com/qemu/qemu/commit/d6430c17d7113d3c38480dc34e59d00b0504e2f7
> 2. This patch series depends on the following patch series
> https://patchwork.kernel.org/project/qemu-devel/cover/20250113064455.1660564-1-jamin_lin@aspeedtech.com/
> https://patchwork.kernel.org/project/qemu-devel/cover/20241114094839.4128404-1-jamin_lin@aspeedtech.com/
> 3. ASPEED SDK v09.05 pre-built image
> https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.05
> ast2700-default-obmc.tar.gz (A1)
> https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.05/ast2700-default-obmc.tar.gz
We need a functional test case for the new A1 SoC please.
Also, could please split the patchset in 3 and resend :
1. INTC rename/prereqs/cleanups
hw/intc/aspeed: Rename INTC to INTC0
hw/intc/aspeed: Support different memory region ops
hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0
hw/intc/aspeed: Support setting different memory and register size
hw/intc/aspeed: Introduce helper functions for enable and status registers
hw/intc/aspeed: Add ID to trace events for better debugging
hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0
2. AST2700A1 support
hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions
hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address
hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication
hw/intc/aspeed: Add Support for Multi-Output IRQ Handling
hw/intc/aspeed: Add Support for AST2700 INTC1 Controller
hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1
3. HACE support
hw/misc/aspeed_hace: Fix coding style
hw/misc/aspeed_hace: Add AST2700 support
hw/arm/aspeed_ast27x0: Add HACE support for AST2700
hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self Test(WORKAROUND)
It seems that 1+3 could be reviewed and merged quickly. 2 is definitely
more complex.
> Known Issue:
> The HACE crypto and hash engine is enable by default since AST2700 A1.
> However, aspeed_hace.c(HACE model) currently does not support the CRYPTO command.
Do we need support from the QEMU crypto subsystem or do we only lack
an implementation for the model ?
> To boot AST2700 A1, I have created a Patch 18 which temporarily resolves the
> issue by sending an interrupt to notify the firmware that the cryptographic
> command has completed. It is a temporary workaround to resolve the boot issue
> in the Crypto Manager SelfTest.
could you test the silicon revision in the model for this workaround ?
Thanks,
C.
> As a result, you will encounter the following kernel warning due to the
> Crypto Manager test failure. If you don't want to see these kernel warning,
> please add the following settings in your kernel config.
>
> ```
> CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
> ```
>
> ```
> alg: skcipher: aspeed-ctr-tdes encryption test failed (wrong result) on test vector 0, cfg="in-place (one sglist)"
> [ 5.035966] alg: self-tests for ctr(des3_ede) using aspeed-ctr-tdes failed (rc=-22)
> [ 5.036139] ------------[ cut here ]------------
> [ 5.037188] alg: self-tests for ctr(des3_ede) using aspeed-ctr-tdes failed (rc=-22)
> [ 5.037312] WARNING: CPU: 2 PID: 109 at /crypto/testmgr.c:5936 alg_test+0x42c/0x548
> [ 5.038049] Modules linked in:
> [ 5.038302] CPU: 2 PID: 109 Comm: cryptomgr_test Tainted: G W 6.6.52-v00.06.04-gf52a0cf7c475 #1
> [ 5.038787] Hardware name: AST2700-EVB (DT)
> [ 5.038988] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [ 5.039315] pc : alg_test+0x42c/0x548
> [ 5.039505] lr : alg_test+0x42c/0x548
> [ 5.039697] sp : ffffffc0825e3d50
> [ 5.039862] x29: ffffffc0825e3df0 x28: 0000000000000004 x27: 0000000000000000
> [ 5.040226] x26: ffffffc080bcada0 x25: ffffffc081dac9d0 x24: 0000000000000004
> [ 5.040700] x23: 0000000000001285 x22: ffffff8003ded280 x21: ffffff8003ded200
> [ 5.041458] x20: 00000000ffffffff x19: 00000000ffffffea x18: ffffffffffffffff
> [ 5.041915] x17: 282064656c696166 x16: 20736564742d7274 x15: 00000000fffffffe
> [ 5.042287] x14: 0000000000000000 x13: ffffffc081ba555c x12: 65742d666c657320
> [ 5.042684] x11: 00000000fffeffff x10: ffffffc0818ff048 x9 : ffffffc0800a36e4
> [ 5.043077] x8 : 000000000017ffe8 x7 : c0000000fffeffff x6 : 000000000057ffa8
> [ 5.043461] x5 : 000000000000ffff x4 : 0000000000000000 x3 : 0000000000000000
> [ 5.043751] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffffff800415e740
> [ 5.045544] Call trace:
> [ 5.045693] alg_test+0x42c/0x548
> [ 5.045878] cryptomgr_test+0x28/0x48
> [ 5.046052] kthread+0x114/0x120
> [ 5.046226] ret_from_fork+0x10/0x20
> [ 5.046413] ---[ end trace 0000000000000000 ]---
> [ 5.071510] alg: skcipher: aspeed-ctr-des encryption test failed (wrong result) on test vector 0, cfg="in-place (one sglist)"
> [ 5.072145] alg: self-tests for ctr(des) using aspeed-ctr-des failed (rc=-22)
> ```
>
>
> Jamin Lin (18):
> hw/intc/aspeed: Rename INTC to INTC0
> hw/intc/aspeed: Support different memory region ops
> hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0
> hw/intc/aspeed: Support setting different memory and register size
> hw/intc/aspeed: Introduce helper functions for enable and status
> registers
> hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq
> index and register address
> hw/intc/aspeed: Introduce IRQ handler function to reduce code
> duplication
> hw/intc/aspeed: Add Support for Multi-Output IRQ Handling
> hw/intc/aspeed: Add ID to trace events for better debugging
> hw/intc/aspeed: Add Support for AST2700 INTC1 Controller
> hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon
> Revisions
> hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for
> AST2700 A1
> hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0
> hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1
> hw/misc/aspeed_hace: Fix coding style
> hw/misc/aspeed_hace: Add AST2700 support
> hw/arm/aspeed_ast27x0: Add HACE support for AST2700
> hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self
> Test(WORKAROUND)
>
> hw/arm/aspeed.c | 26 +-
> hw/arm/aspeed_ast27x0.c | 229 +++++++++--
> hw/intc/aspeed_intc.c | 689 +++++++++++++++++++++++++---------
> hw/intc/trace-events | 25 +-
> hw/misc/aspeed_hace.c | 44 ++-
> hw/misc/aspeed_scu.c | 3 +
> include/hw/arm/aspeed_soc.h | 5 +-
> include/hw/intc/aspeed_intc.h | 35 +-
> include/hw/misc/aspeed_hace.h | 1 +
> include/hw/misc/aspeed_scu.h | 2 +
> 10 files changed, 817 insertions(+), 242 deletions(-)
>
^ permalink raw reply [flat|nested] 54+ messages in thread* RE: [PATCH v1 00/18] Support AST2700 A1
2025-01-31 7:34 ` [PATCH v1 00/18] Support AST2700 A1 Cédric Le Goater
@ 2025-02-04 8:05 ` Jamin Lin
2025-06-30 20:28 ` Cédric Le Goater
1 sibling, 0 replies; 54+ messages in thread
From: Jamin Lin @ 2025-02-04 8:05 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hi Cedric,
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Friday, January 31, 2025 3:34 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Andrew Jeffery <andrew@codeconstruct.com.au>;
> Joel Stanley <joel@jms.id.au>; open list:ASPEED BMCs
> <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 00/18] Support AST2700 A1
>
> Hello Jamin,
>
> On 1/21/25 08:04, Jamin Lin wrote:
> > v1:
> > 1. Refactor INTC model to support both INTC0 and INTC1.
> > 2. Support AST2700 A1.
> > 3. Create ast2700a0-evb machine.
> >
> > With the patch applied, QEMU now supports two machines for running
> AST2700 SoCs:
> > ast2700a0-evb: Designed for AST2700 A0
> > ast2700-evb: Designed for AST2700 A1
>
> Let's do that progressively, please add a new ast2700a1-evb machine too and a
> machine alias on ast2700a0-evb. Then we will change the alias on the newer
> SoC.
>
Will add
>
> >
> > Test information
> > 1. QEMU version:
> >
> https://github.com/qemu/qemu/commit/d6430c17d7113d3c38480dc34e59d0
> 0b05
> > 04e2f7 2. This patch series depends on the following patch series
> >
> https://patchwork.kernel.org/project/qemu-devel/cover/20250113064455.166
> 0564-1-jamin_lin@aspeedtech.com/
> >
> > https://patchwork.kernel.org/project/qemu-devel/cover/20241114094839.4
> > 128404-1-jamin_lin@aspeedtech.com/
> > 3. ASPEED SDK v09.05 pre-built image
> > https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.05
> > ast2700-default-obmc.tar.gz (A1)
> >
> >
> https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.05/ast
> > 2700-default-obmc.tar.gz
>
> We need a functional test case for the new A1 SoC please.
>
Will add
>
>
> Also, could please split the patchset in 3 and resend :
>
> 1. INTC rename/prereqs/cleanups
>
> hw/intc/aspeed: Rename INTC to INTC0
> hw/intc/aspeed: Support different memory region ops
> hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0
> hw/intc/aspeed: Support setting different memory and register size
> hw/intc/aspeed: Introduce helper functions for enable and status registers
> hw/intc/aspeed: Add ID to trace events for better debugging
> hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0
>
> 2. AST2700A1 support
>
> hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon
> Revisions
> hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index
> and register address
> hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication
> hw/intc/aspeed: Add Support for Multi-Output IRQ Handling
> hw/intc/aspeed: Add Support for AST2700 INTC1 Controller
> hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for
> AST2700 A1
> hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1
>
> 3. HACE support
>
> hw/misc/aspeed_hace: Fix coding style
> hw/misc/aspeed_hace: Add AST2700 support
> hw/arm/aspeed_ast27x0: Add HACE support for AST2700
> hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self
> Test(WORKAROUND)
>
> It seems that 1+3 could be reviewed and merged quickly. 2 is definitely more
> complex.
>
Will re-send 3 patch series for v2
> > Known Issue:
> > The HACE crypto and hash engine is enable by default since AST2700 A1.
> > However, aspeed_hace.c(HACE model) currently does not support the
> CRYPTO command.
>
> Do we need support from the QEMU crypto subsystem or do we only lack an
> implementation for the model ?
>
We currently lack an implementation for the HACE model.
While it supports the HASH module, the CRYPT module is not yet implemented (aspeed_hace.c).
Additionally, I am investigating which "QCrypto common API" can be used to support AES (ECB, CBC, CFB, CTR, GCM, etc.) and DES.
https://github.com/qemu/qemu/tree/master/crypto
Do you have any suggestion?
> > To boot AST2700 A1, I have created a Patch 18 which temporarily
> > resolves the issue by sending an interrupt to notify the firmware that
> > the cryptographic command has completed. It is a temporary workaround
> > to resolve the boot issue in the Crypto Manager SelfTest.
>
> could you test the silicon revision in the model for this workaround ?
>
I have tested our pre-built image v09.05 and it worked well. You can download it from:
https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.05/ast2700-default-obmc.tar.gz
```
U-Boot 2023.10-v00.05.05 (Jan 22 2025 - 07:38:51 +0000)
SOC: AST2700-A1
```
Thanks for suggestion and review.
Jamin
>
> Thanks,
>
> C.
>
>
>
> > As a result, you will encounter the following kernel warning due to
> > the Crypto Manager test failure. If you don't want to see these kernel
> > warning, please add the following settings in your kernel config.
> >
> > ```
> > CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
> > ```
> >
> > ```
> > alg: skcipher: aspeed-ctr-tdes encryption test failed (wrong result) on test
> vector 0, cfg="in-place (one sglist)"
> > [ 5.035966] alg: self-tests for ctr(des3_ede) using aspeed-ctr-tdes failed
> (rc=-22)
> > [ 5.036139] ------------[ cut here ]------------
> > [ 5.037188] alg: self-tests for ctr(des3_ede) using aspeed-ctr-tdes failed
> (rc=-22)
> > [ 5.037312] WARNING: CPU: 2 PID: 109 at /crypto/testmgr.c:5936
> alg_test+0x42c/0x548
> > [ 5.038049] Modules linked in:
> > [ 5.038302] CPU: 2 PID: 109 Comm: cryptomgr_test Tainted: G
> W 6.6.52-v00.06.04-gf52a0cf7c475 #1
> > [ 5.038787] Hardware name: AST2700-EVB (DT)
> > [ 5.038988] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS
> BTYPE=--)
> > [ 5.039315] pc : alg_test+0x42c/0x548
> > [ 5.039505] lr : alg_test+0x42c/0x548
> > [ 5.039697] sp : ffffffc0825e3d50
> > [ 5.039862] x29: ffffffc0825e3df0 x28: 0000000000000004 x27:
> 0000000000000000
> > [ 5.040226] x26: ffffffc080bcada0 x25: ffffffc081dac9d0 x24:
> 0000000000000004
> > [ 5.040700] x23: 0000000000001285 x22: ffffff8003ded280 x21:
> ffffff8003ded200
> > [ 5.041458] x20: 00000000ffffffff x19: 00000000ffffffea x18: ffffffffffffffff
> > [ 5.041915] x17: 282064656c696166 x16: 20736564742d7274 x15:
> 00000000fffffffe
> > [ 5.042287] x14: 0000000000000000 x13: ffffffc081ba555c x12:
> 65742d666c657320
> > [ 5.042684] x11: 00000000fffeffff x10: ffffffc0818ff048 x9 :
> ffffffc0800a36e4
> > [ 5.043077] x8 : 000000000017ffe8 x7 : c0000000fffeffff x6 :
> 000000000057ffa8
> > [ 5.043461] x5 : 000000000000ffff x4 : 0000000000000000 x3 :
> 0000000000000000
> > [ 5.043751] x2 : 0000000000000000 x1 : 0000000000000000 x0 :
> ffffff800415e740
> > [ 5.045544] Call trace:
> > [ 5.045693] alg_test+0x42c/0x548
> > [ 5.045878] cryptomgr_test+0x28/0x48
> > [ 5.046052] kthread+0x114/0x120
> > [ 5.046226] ret_from_fork+0x10/0x20
> > [ 5.046413] ---[ end trace 0000000000000000 ]---
> > [ 5.071510] alg: skcipher: aspeed-ctr-des encryption test failed (wrong
> result) on test vector 0, cfg="in-place (one sglist)"
> > [ 5.072145] alg: self-tests for ctr(des) using aspeed-ctr-des failed
> (rc=-22)
> > ```
> >
> >
> > Jamin Lin (18):
> > hw/intc/aspeed: Rename INTC to INTC0
> > hw/intc/aspeed: Support different memory region ops
> > hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0
> > hw/intc/aspeed: Support setting different memory and register size
> > hw/intc/aspeed: Introduce helper functions for enable and status
> > registers
> > hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq
> > index and register address
> > hw/intc/aspeed: Introduce IRQ handler function to reduce code
> > duplication
> > hw/intc/aspeed: Add Support for Multi-Output IRQ Handling
> > hw/intc/aspeed: Add ID to trace events for better debugging
> > hw/intc/aspeed: Add Support for AST2700 INTC1 Controller
> > hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon
> > Revisions
> > hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for
> > AST2700 A1
> > hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0
> > hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1
> > hw/misc/aspeed_hace: Fix coding style
> > hw/misc/aspeed_hace: Add AST2700 support
> > hw/arm/aspeed_ast27x0: Add HACE support for AST2700
> > hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self
> > Test(WORKAROUND)
> >
> > hw/arm/aspeed.c | 26 +-
> > hw/arm/aspeed_ast27x0.c | 229 +++++++++--
> > hw/intc/aspeed_intc.c | 689
> +++++++++++++++++++++++++---------
> > hw/intc/trace-events | 25 +-
> > hw/misc/aspeed_hace.c | 44 ++-
> > hw/misc/aspeed_scu.c | 3 +
> > include/hw/arm/aspeed_soc.h | 5 +-
> > include/hw/intc/aspeed_intc.h | 35 +-
> > include/hw/misc/aspeed_hace.h | 1 +
> > include/hw/misc/aspeed_scu.h | 2 +
> > 10 files changed, 817 insertions(+), 242 deletions(-)
> >
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v1 00/18] Support AST2700 A1
2025-01-31 7:34 ` [PATCH v1 00/18] Support AST2700 A1 Cédric Le Goater
2025-02-04 8:05 ` Jamin Lin
@ 2025-06-30 20:28 ` Cédric Le Goater
2025-07-02 1:57 ` Jamin Lin
1 sibling, 1 reply; 54+ messages in thread
From: Cédric Le Goater @ 2025-06-30 20:28 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
Hi,
On 1/31/25 08:34, Cédric Le Goater wrote:
> Hello Jamin,
>
> On 1/21/25 08:04, Jamin Lin wrote:
>> v1:
>> 1. Refactor INTC model to support both INTC0 and INTC1.
>> 2. Support AST2700 A1.
>> 3. Create ast2700a0-evb machine.
>> With the patch applied, QEMU now supports two machines for running AST2700 SoCs:
>> ast2700a0-evb: Designed for AST2700 A0
>> ast2700-evb: Designed for AST2700 A1
>
> Let's do that progressively, please add a new ast2700a1-evb machine too and
> a machine alias on ast2700a0-evb. Then we will change the alias on the newer
> SoC.
So, machine 'ast2700a1-evb' was added in QEMU 10.0.0 :
498c519eb776 "hw/arm/aspeed: Add Machine Support for AST2700 A1"
and machine 'ast2700a0-evb' in QEMU 9.1.0:
92707992103e "aspeed: Add an AST2700 eval board"
and, currently, machine 'ast2700-evb' is an alias of 'ast2700a0-evb' :
$ ./build/qemu-system-aarch64 -M ? | grep AST2700
ast2700-evb Aspeed AST2700 A0 EVB (Cortex-A35) (alias of ast2700a0-evb)
ast2700a0-evb Aspeed AST2700 A0 EVB (Cortex-A35)
ast2700a1-evb Aspeed AST2700 A1 EVB (Cortex-A35)
Should we switch the alias to point to 'ast2700a1-evb' in QEMU 10.1.0 ?
and deprecate the A0 SoC and machine if it is no longer planned to
support them.
Thanks,
C.
^ permalink raw reply [flat|nested] 54+ messages in thread
* RE: [PATCH v1 00/18] Support AST2700 A1
2025-06-30 20:28 ` Cédric Le Goater
@ 2025-07-02 1:57 ` Jamin Lin
2025-07-02 6:43 ` Cédric Le Goater
0 siblings, 1 reply; 54+ messages in thread
From: Jamin Lin @ 2025-07-02 1:57 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hi Cédric
> Subject: Re: [PATCH v1 00/18] Support AST2700 A1
>
> Hi,
>
> On 1/31/25 08:34, Cédric Le Goater wrote:
> > Hello Jamin,
> >
> > On 1/21/25 08:04, Jamin Lin wrote:
> >> v1:
> >> 1. Refactor INTC model to support both INTC0 and INTC1.
> >> 2. Support AST2700 A1.
> >> 3. Create ast2700a0-evb machine.
> >> With the patch applied, QEMU now supports two machines for running
> AST2700 SoCs:
> >> ast2700a0-evb: Designed for AST2700 A0
> >> ast2700-evb: Designed for AST2700 A1
> >
> > Let's do that progressively, please add a new ast2700a1-evb machine
> > too and a machine alias on ast2700a0-evb. Then we will change the
> > alias on the newer SoC.
>
>
> So, machine 'ast2700a1-evb' was added in QEMU 10.0.0 :
>
> 498c519eb776 "hw/arm/aspeed: Add Machine Support for AST2700 A1"
>
> and machine 'ast2700a0-evb' in QEMU 9.1.0:
>
> 92707992103e "aspeed: Add an AST2700 eval board"
>
> and, currently, machine 'ast2700-evb' is an alias of 'ast2700a0-evb' :
>
> $ ./build/qemu-system-aarch64 -M ? | grep AST2700
> ast2700-evb Aspeed AST2700 A0 EVB (Cortex-A35) (alias of
> ast2700a0-evb)
> ast2700a0-evb Aspeed AST2700 A0 EVB (Cortex-A35)
> ast2700a1-evb Aspeed AST2700 A1 EVB (Cortex-A35)
>
> Should we switch the alias to point to 'ast2700a1-evb' in QEMU 10.1.0 ?
> and deprecate the A0 SoC and machine if it is no longer planned to support
> them.
>
Sorry for the late reply and delay in processing this task.
I’ve been postponing this because our customers do not have "AST2700 A1 EVB".
Since ASPEED SDK has dropped support for AST2700 A0 as of version "v09.07", I believe it's now appropriate to remove AST2700 A0 support in QEMU.
https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.07
In addition, I plan to make ast2700-evb an alias of ast2700a1-evb.
Currently, I’m not very familiar with the proper procedure to deprecate an existing machine in QEMU, but the following is my initial plan for handling this task:
PATCH 1: Update the ast2700-evb alias to point to ast2700a1-evb and remove AST2700 A0 functional tests.
PATCH 2: Remove the AST2700 A0 SoC and ast2700a0-evb machine implementation.
PATCH 3: (Question) Should I update the docs/about/deprecated.rst file as well?
Thanks-Jamin
> Thanks,
>
> C.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v1 00/18] Support AST2700 A1
2025-07-02 1:57 ` Jamin Lin
@ 2025-07-02 6:43 ` Cédric Le Goater
2025-07-03 7:43 ` Jamin Lin
0 siblings, 1 reply; 54+ messages in thread
From: Cédric Le Goater @ 2025-07-02 6:43 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hello,
>> Should we switch the alias to point to 'ast2700a1-evb' in QEMU 10.1.0 ?
>> and deprecate the A0 SoC and machine if it is no longer planned to support
>> them.
>>
>
> Sorry for the late reply and delay in processing this task.
> I’ve been postponing this because our customers do not have "AST2700 A1 EVB".
oh. There is no urgency to remove A0.
> Since ASPEED SDK has dropped support for AST2700 A0 as of version "v09.07", I believe it's now appropriate to remove AST2700 A0 support in QEMU.
> https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.07
> In addition, I plan to make ast2700-evb an alias of ast2700a1-evb.
>
> Currently, I’m not very familiar with the proper procedure to deprecate an existing machine in QEMU, but the following is my initial plan for handling this task:
> PATCH 1: Update the ast2700-evb alias to point to ast2700a1-evb and remove AST2700 A0 functional tests.
That's something we can do whenever we like now.
> PATCH 2: Remove the AST2700 A0 SoC and ast2700a0-evb machine implementation.
> PATCH 3: (Question) Should I update the docs/about/deprecated.rst file as well?
See https://www.qemu.org/docs/master/about/deprecated.html
First, we update the deprecated file, then remove the soc in
2 releases.
Thanks,
C.
^ permalink raw reply [flat|nested] 54+ messages in thread
* RE: [PATCH v1 00/18] Support AST2700 A1
2025-07-02 6:43 ` Cédric Le Goater
@ 2025-07-03 7:43 ` Jamin Lin
0 siblings, 0 replies; 54+ messages in thread
From: Jamin Lin @ 2025-07-03 7:43 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hi Cédric,
> Subject: Re: [PATCH v1 00/18] Support AST2700 A1
>
> Hello,
>
> >> Should we switch the alias to point to 'ast2700a1-evb' in QEMU 10.1.0 ?
> >> and deprecate the A0 SoC and machine if it is no longer planned to
> >> support them.
> >>
> >
> > Sorry for the late reply and delay in processing this task.
> > I’ve been postponing this because our customers do not have "AST2700 A1
> EVB".
>
> oh. There is no urgency to remove A0.
>
> > Since ASPEED SDK has dropped support for AST2700 A0 as of version "v09.07",
> I believe it's now appropriate to remove AST2700 A0 support in QEMU.
> > https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.07
> > In addition, I plan to make ast2700-evb an alias of ast2700a1-evb.
> >
> > Currently, I’m not very familiar with the proper procedure to deprecate an
> existing machine in QEMU, but the following is my initial plan for handling this
> task:
> > PATCH 1: Update the ast2700-evb alias to point to ast2700a1-evb and remove
> AST2700 A0 functional tests.
>
> That's something we can do whenever we like now.
>
> > PATCH 2: Remove the AST2700 A0 SoC and ast2700a0-evb machine
> implementation.
> > PATCH 3: (Question) Should I update the docs/about/deprecated.rst file as
> well?
>
> See https://www.qemu.org/docs/master/about/deprecated.html
>
> First, we update the deprecated file, then remove the soc in
> 2 releases.
Update deprecated.html patch here, https://patchwork.kernel.org/project/qemu-devel/patch/20250703052400.2927831-1-jamin_lin@aspeedtech.com/
Thanks-Jamin
>
> Thanks,
>
> C.
>
^ permalink raw reply [flat|nested] 54+ messages in thread