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Tue, 24 Mar 2026 20:59:15 -0700 (PDT) Received: from ZEVORN-PC.localdomain ([38.95.120.198]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c10b17d1ddsm16775894eec.11.2026.03.24.20.59.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 20:59:14 -0700 (PDT) Date: Wed, 25 Mar 2026 11:58:54 +0800 From: Chao Liu To: Djordje Todorovic Cc: "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" , "philmd@linaro.org" , "alistair23@gmail.com" , "thuth@redhat.com" Subject: Re: [PATCH v5 0/7] Add RISC-V big-endian target support Message-ID: References: <20260324164007.549397-1-djordje.todorovic@htecgroup.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260324164007.549397-1-djordje.todorovic@htecgroup.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1343; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-dy1-x1343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Djordje, On Tue, Mar 24, 2026 at 04:40:14PM +0000, Djordje Todorovic wrote: > Adding functional test case for riscv big-endian. > Thanks for the v5 and for adding the functional test that Philippe requested. The runtime big-endian approach is the right direction. However, it looks like the series was developed on top of Philippe's "[PATCH-for-11.1] target/riscv: Forbid to use legacy native endianness API" prep series, which hasn't been merged yet. This causes two build-breaking issues and apply failures on both master and riscv-to-apply.next. For v6, I'd suggest either: a) Explicitly declare "Based-on:" Philippe's prep series, or b) Include the prerequisite changes (MSTATUS defines, op_helper.c cleanup, MO_TE->MO_LE) in this series. Thanks, Chao > Djordje Todorovic (7): > target/riscv: Add big-endian CPU property > target/riscv: Set endianness MSTATUS bits at CPU reset > target/riscv: Implement runtime data endianness via MSTATUS bits > hw/riscv: Make boot code endianness-aware at runtime > target/riscv: Fix page table walk endianness for big-endian harts > target/riscv: Support runtime endianness in virtio via sysemu callback > target/riscv: Add test for RISC-V BE > > hw/riscv/boot.c | 82 ++++++++++++++++++---- > include/hw/riscv/boot.h | 2 + > target/riscv/cpu.c | 22 ++++-- > target/riscv/cpu.h | 28 ++++++++ > target/riscv/cpu_cfg_fields.h.inc | 1 + > target/riscv/cpu_helper.c | 28 ++++++-- > target/riscv/internals.h | 9 +-- > target/riscv/tcg/tcg-cpu.c | 9 ++- > target/riscv/translate.c | 12 ++-- > tests/functional/riscv64/meson.build | 1 + > tests/functional/riscv64/test_bigendian.py | 57 +++++++++++++++ > 11 files changed, 211 insertions(+), 40 deletions(-) > create mode 100644 tests/functional/riscv64/test_bigendian.py > > -- > 2.34.1