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[103.95.112.190]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b0bc917b5fsm18321605ad.84.2026.03.25.23.29.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2026 23:29:25 -0700 (PDT) Date: Thu, 26 Mar 2026 16:29:22 +1000 From: Nicholas Piggin To: Chao Liu Cc: Alistair Francis , qemu-riscv@nongnu.org, Laurent Vivier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-devel@nongnu.org, Joel Stanley , Nicholas Joaquin , Ganesh Valliappan Subject: Re: [PATCH v3 1/3] target/riscv: Fix IALIGN check in misa write Message-ID: References: <20260321144554.606417-1-npiggin@gmail.com> <20260321144554.606417-2-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Mar 25, 2026 at 11:40:18AM +0800, Chao Liu wrote: > On Wed, Mar 25, 2026 at 01:26:56PM +1000, Alistair Francis wrote: > > On Wed, Mar 25, 2026 at 1:09 PM Chao Liu wrote: > > > > > > On Sun, Mar 22, 2026 at 12:45:52AM +1000, Nicholas Piggin wrote: > > > > The instruction alignment check for the C extension was inverted. > > > > The new value should be checked for C bit clear (thus increasing > > > > IALIGN). If IALIGN is incompatible, then the write to misa should > > > > be suppressed, not just ignoring the update to the C bit. > > > > > > > > From the ISA: > > > > > > > > Writing misa may increase IALIGN, e.g., by disabling the "C" > > > > extension. If an instruction that would write misa increases IALIGN, > > > > and the subsequent instruction’s address is not IALIGN-bit aligned, > > > > the write to misa is suppressed, leaving misa unchanged. > > > > > > > > This was found with a verification test generator based on RiESCUE. > > > > > > > > Reported-by: Nicholas Joaquin > > > > Reported-by: Ganesh Valliappan > > > > Signed-off-by: Nicholas Piggin > > > > --- > > > > target/riscv/csr.c | 16 ++++- > > > > tests/tcg/riscv64/Makefile.softmmu-target | 5 ++ > > > > tests/tcg/riscv64/misa-ialign.S | 88 +++++++++++++++++++++++ > > > > 3 files changed, 106 insertions(+), 3 deletions(-) > > > > create mode 100644 tests/tcg/riscv64/misa-ialign.S > > > > > > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > > > index 5064483917..91421a2dd8 100644 > > > > --- a/target/riscv/csr.c > > > > +++ b/target/riscv/csr.c > > > > @@ -2129,9 +2129,19 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, > > > > /* Mask extensions that are not supported by this hart */ > > > > val &= env->misa_ext_mask; > > > > > > > > - /* Suppress 'C' if next instruction is not aligned. */ > > > > - if ((val & RVC) && (get_next_pc(env, ra) & 3) != 0) { > > > > - val &= ~RVC; > > > > + /* > > > > + * misa writes that increase IALIGN beyond alignment of the next > > > > + * instruction cause the write to misa to be suppressed. Clearing > > > > + * "C" extension increases IALIGN. > > > > + */ > > > > + if (!(val & RVC) && (get_next_pc(env, ra) & 3) != 0) { > > > > + /* > > > > + * If the next instruction is unaligned mod 4 then "C" must be > > > > + * set or this instruction could not be executing, so we know > > > > + * this is is clearing "C" (and not just keeping it clear). > > > "this is is clearing" — double "is" > > > > > > > + */ > > > > + g_assert(env->misa_ext & RVC); > > > > + return RISCV_EXCP_NONE; > > > write_misa() is also reachable via riscv_csrrw_debug() > > > with ra=0, where get_next_pc() falls back to env->pc. > > > > Ah good catch > > > > > A debugger can set PC to a 2-byte-aligned address while C is > > > already disabled, then write misa keeping C=0. This hits > > > the condition and fires the g_assert. > > > > I'm not convinced that that's necessarily bad, as that's an odd and > > invalid thing to be writing. But we probably shouldn't assert > > > > > > > > The ISA spec language: > > > > > > "if an instruction that would write misa..." > > > > > > does not cover debug writes, so the IALIGN suppression > > > arguably should not apply in that case at all. > > > > > > We can: > > > > > > if (ra && !(val & RVC) > > > && (get_next_pc(env, ra) & 3) != 0) { > > > g_assert(env->misa_ext & RVC); > > > return RISCV_EXCP_NONE; > > > } > > > > Maybe it's best to change the `g_assert()` to a log GUEST_ERROR > > instead. That way we flag that something fishy is going on, but don't > > exit QEMU > > > Agreed! > > Replacing the g_assert() with qemu_log_mask(LOG_GUEST_ERROR, ...) > sounds like the right balance — it still surfaces the anomaly for > anyone debugging, without taking down QEMU over what is ultimately > a debugger-induced corner case. > > The IALIGN suppression logic itself is still correct for the normal > execution path, so there's no reason to skip it entirely; just don't > crash on the weird one. Okay good feedback, thanks to you both. I agree, I'll make the changes and resend. Thanks, Nick