Re: [PATCH v3 3/3] tests/tcg: Add riscv test for interrupted vector ops

[Nicholas Piggin <npiggin@gmail.com>]

On Wed, Mar 25, 2026 at 11:19:26AM +0800, Chao Liu wrote:
> On Sun, Mar 22, 2026 at 12:45:54AM +1000, Nicholas Piggin wrote:
> > riscv vector instructions can be interrupted with a trap, and partial
> > completion is recorded in the vstart register. Some causes are
> > implementation dependent, for example an asynchronous interrupt (which I
> > don't think TCG allows). Others are architectural, typically memory
> > access faults on vector load/store instructions.
> > 
> > Add some TCG tests for interrupting vector load instructions and
> > resuming partially completed ones.
> > 
> > This would have caught a recent (now reverted) regression in vector
> > stride load implementation, commit 28c12c1f2f50d ("Generate strided
> > vector loads/stores with tcg nodes.")
> > 
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> > ---
> >  tests/tcg/riscv64/Makefile.target      |  11 +
> >  tests/tcg/riscv64/test-interrupted-v.c | 329 +++++++++++++++++++++++++
> >  2 files changed, 340 insertions(+)
> >  create mode 100644 tests/tcg/riscv64/test-interrupted-v.c
> > 
> > diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
> > index 19a49b6467..b2b2325843 100644
> > --- a/tests/tcg/riscv64/Makefile.target
> > +++ b/tests/tcg/riscv64/Makefile.target
> > @@ -1,6 +1,10 @@
> >  # -*- Mode: makefile -*-
> >  # RISC-V specific tweaks
> >  
> > +# Not all environments have compilers with vector intrinsics yet.
> > +HAVE_RISCV_VECTOR_INTRINSICS := $(shell echo '#ifndef __riscv_v_intrinsic\n#error\n#endif' |  \
> > +                                  $(CC) -march=rv64gcv -E -x c - >/dev/null 2>&1 && echo y)
> The feature probe relies on echo interpreting '\n'
> as newlines, but this is not portable.
> 
> POSIX leaves echo's handling of backslash sequences
> implementation-defined.
> 
> On bash (the default /bin/sh on many systems including
> Fedora, Arch, and some CI images), echo outputs literal
> '\n', so the preprocessor sees a malformed single-line input
> and always fails. This silently disables test-interrupted-v
> even when the compiler supports vector intrinsics.
> 
> I suggest using printf for portability:
> 
>     HAVE_RISCV_VECTOR_INTRINSICS := $(shell printf \
>         '#ifndef __riscv_v_intrinsic\n#error\n#endif\n' | \
>         $(CC) -march=rv64gcv -E -x c - \
>         >/dev/null 2>&1 && echo y)

Wow nice catch. My shell skills amount to pressing random buttons
until it works, so I appreciate the help :P

[...]

> > +static volatile int nr_segv;
> > +static volatile unsigned long fault_start, fault_end;
> > +static volatile bool fault_write;
> checkpatch errors:
> 
>   ERROR: Use of volatile is usually wrong, please add a comment
>   #84: FILE: tests/tcg/riscv64/test-interrupted-v.c:26:
>   +static volatile int nr_segv;
> 
>   ERROR: Use of volatile is usually wrong, please add a comment
>   #85: FILE: tests/tcg/riscv64/test-interrupted-v.c:27:
>   +static volatile unsigned long fault_start, fault_end;
> 
>   ERROR: Use of volatile is usually wrong, please add a comment
>   #86: FILE: tests/tcg/riscv64/test-interrupted-v.c:28:
>   +static volatile bool fault_write;
> 
> Please fix it.

Yeah I guess they were missed in the rest of the checkpatch
errors, you're right the volatiles should be commented.

Thanks,
Nick