From: Richard Henderson <richard.henderson@linaro.org>
To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Kito Cheng <kito.cheng@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Subject: Re: [RFC v3 16/16] target/riscv: rvb: support and turn on B-extension from command line
Date: Mon, 11 Jan 2021 19:47:47 -1000 [thread overview]
Message-ID: <acde5c9d-88ba-f4ae-5d05-e0266254b588@linaro.org> (raw)
In-Reply-To: <20210112022001.20521-17-frank.chang@sifive.com>
On 1/11/21 4:19 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> B-extension is default off, use cpu rv32 or rv64 with x-b=true to
> enable B-extension.
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 4 ++++
> target/riscv/cpu.h | 2 ++
> 2 files changed, 6 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
prev parent reply other threads:[~2021-01-12 5:53 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 2:19 [RFC v3 00/16] support subsets of bitmanip extension frank.chang
2021-01-12 2:19 ` [RFC v3 01/16] target/riscv: reformat @sh format encoding for B-extension frank.chang
2021-01-12 2:19 ` [RFC v3 02/16] target/riscv: rvb: count leading/trailing zeros frank.chang
2021-01-12 2:19 ` [RFC v3 03/16] target/riscv: rvb: count bits set frank.chang
2021-01-12 2:19 ` [RFC v3 04/16] target/riscv: rvb: logic-with-negate frank.chang
2021-01-12 5:46 ` Richard Henderson
2021-01-12 2:19 ` [RFC v3 05/16] target/riscv: rvb: pack two words into one register frank.chang
2021-01-12 2:19 ` [RFC v3 06/16] target/riscv: rvb: min/max instructions frank.chang
2021-01-12 2:19 ` [RFC v3 07/16] target/riscv: rvb: sign-extend instructions frank.chang
2021-01-12 2:19 ` [RFC v3 08/16] target/riscv: add gen_shifti() and gen_shiftiw() helper functions frank.chang
2021-01-12 4:54 ` Richard Henderson
2021-01-12 5:27 ` Frank Chang
2021-01-12 2:19 ` [RFC v3 09/16] target/riscv: rvb: single-bit instructions frank.chang
2021-01-12 4:56 ` Richard Henderson
2021-01-12 2:19 ` [RFC v3 10/16] target/riscv: rvb: shift ones frank.chang
2021-01-12 2:19 ` [RFC v3 11/16] target/riscv: rvb: rotate (left/right) frank.chang
2021-01-12 5:45 ` Richard Henderson
2021-01-12 2:19 ` [RFC v3 12/16] target/riscv: rvb: generalized reverse frank.chang
2021-01-12 2:19 ` [RFC v3 13/16] target/riscv: rvb: generalized or-combine frank.chang
2021-01-12 5:47 ` Richard Henderson
2021-01-12 2:19 ` [RFC v3 14/16] target/riscv: rvb: address calculation frank.chang
2021-01-12 2:19 ` [RFC v3 15/16] target/riscv: rvb: add/shift with prefix zero-extend frank.chang
2021-01-12 2:19 ` [RFC v3 16/16] target/riscv: rvb: support and turn on B-extension from command line frank.chang
2021-01-12 5:47 ` Richard Henderson [this message]
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