From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Alexey Baturo <baturo.alexey@gmail.com>
Cc: Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com
Subject: Re: [PATCH 09/13] target/riscv: Adjust vector address with ol
Date: Tue, 9 Nov 2021 10:25:50 +0100 [thread overview]
Message-ID: <ace70393-0a40-93c1-f30b-e45b0ba856ca@linaro.org> (raw)
In-Reply-To: <47b0a429-52ac-4d5e-ce0b-cea67b44c550@c-sky.com>
On 11/9/21 10:05 AM, LIU Zhiwei wrote:
>> Do you mean we should add this code to riscv_tr_init_disas_context
>>
>> if (ctx->pm_enabled) {
>> switch (priv) {
>> case PRV_M:
>> env->mask = env->mpmmask;
>> env->base = env->mpmbase;
>> break;
>> case PRV_S:
>> env->mask = env->spmmask;
>> env->base = env->spmbase;
>> break;
>> case PRV_U:
>> env->mask = env->upmmask;
>> env->base = env->upmbase;
>> break;
>> default:
>> g_assert_not_reached();
>> }
>> ctx->pm_mask = pm_mask[priv];
>> ctx->pm_base = pm_base[priv];
>> ctx->need_mask = true; /* new flag for mask */
>> } else if (get_xlen(ctx) < TARGET_LONG_BITS) {
>> env->mask = UINT32_MAX;
>> env->base = 0;
Certainly we cannot modify env in riscv_tr_init_disas_context.
>> ctx->pm_mask = tcg_constant_tl(UINT32_MAX);
>> ctx->pm_base = tcg_constant_tl(0);
>> ctx->need_mask = true;
>> } else {
>> env->mask = UINT64_MAX;
>> env->base = 0;
>> }
>
> I think the code is wrong, perhaps we should modify the write_mpmmask
> env->mask = env->mpmmask = value;
Something like that, yes. However, env->mask must be set based on env->priv, etc; you
can't just assign the same as mpmmask.
Then you also need to update env->mask in a hook like you created in patch 11 to switch
context (though I would call it from helper_mret and helper_sret directly, and not create
a new call from tcg). Then you need to call the hook as well on exception entry, reset,
and vmstate_riscv_cpu.post_load.
r~
next prev parent reply other threads:[~2021-11-09 9:26 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-01 10:01 [PATCH 00/13] Support UXL filed in xstatus LIU Zhiwei
2021-11-01 10:01 ` [PATCH 01/13] target/riscv: Sign extend pc for different ol LIU Zhiwei
2021-11-01 10:29 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 02/13] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-01 10:33 ` Richard Henderson
2021-11-02 1:48 ` LIU Zhiwei
2021-11-02 10:18 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-01 10:35 ` Richard Henderson
2021-11-02 10:20 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-01 10:40 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 05/13] target/riscv: Calculate address according to ol LIU Zhiwei
2021-11-01 10:46 ` Richard Henderson
2021-11-01 15:56 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 06/13] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-01 10:53 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol LIU Zhiwei
2021-11-01 10:55 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 08/13] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-01 13:41 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 09/13] target/riscv: Adjust vector address with ol LIU Zhiwei
2021-11-01 11:35 ` Richard Henderson
2021-11-08 9:28 ` LIU Zhiwei
2021-11-09 6:37 ` Richard Henderson
2021-11-09 8:04 ` LIU Zhiwei
2021-11-09 8:18 ` Richard Henderson
2021-11-09 8:39 ` LIU Zhiwei
2021-11-09 9:05 ` LIU Zhiwei
2021-11-09 9:25 ` Richard Henderson [this message]
2021-11-01 10:01 ` [PATCH 10/13] target/riscv: Adjust scalar reg in vector " LIU Zhiwei
2021-11-01 16:33 ` Richard Henderson
2021-11-08 9:38 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 11/13] target/riscv: Switch context in exception return LIU Zhiwei
2021-11-01 16:43 ` Richard Henderson
2021-11-08 11:23 ` LIU Zhiwei
2021-11-09 6:38 ` LIU Zhiwei
2021-11-09 6:51 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 12/13] target/riscv: Don't save pc when " LIU Zhiwei
2021-11-01 16:49 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 13/13] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-01 17:01 ` Richard Henderson
2021-11-08 12:10 ` LIU Zhiwei
2021-11-10 3:01 ` LIU Zhiwei
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