From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com
Subject: Re: [PATCH] target/riscv: Fix vill field write in vtype
Date: Wed, 2 Feb 2022 11:38:04 +1100 [thread overview]
Message-ID: <aceb893a-bcad-66da-a6cb-091b9b2f14c2@linaro.org> (raw)
In-Reply-To: <20220201064601.41143-1-zhiwei_liu@c-sky.com>
On 2/1/22 17:46, LIU Zhiwei wrote:
> The guest should be able to set the vill bit as part of vsetvl.
>
> Currently we may set env->vill to 1 in the vsetvl helper, but there
> is nowhere that we set it to 0, so once it transitions to 1 it's stuck
> there until the system is reset.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/vector_helper.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2022-02-02 3:58 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-01 6:46 [PATCH] target/riscv: Fix vill field write in vtype LIU Zhiwei
2022-02-02 0:38 ` Richard Henderson [this message]
2022-02-02 6:38 ` Alistair Francis
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