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From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
To: Jason Wang <jasowang@redhat.com>,
	"Duan, Zhenzhong" <zhenzhong.duan@intel.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
	"clg@redhat.com" <clg@redhat.com>,
	"eric.auger@redhat.com" <eric.auger@redhat.com>,
	"mst@redhat.com" <mst@redhat.com>,
	"peterx@redhat.com" <peterx@redhat.com>,
	"jgg@nvidia.com" <jgg@nvidia.com>,
	"nicolinc@nvidia.com" <nicolinc@nvidia.com>,
	"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
	"Tian, Kevin" <kevin.tian@intel.com>,
	"Liu, Yi L" <yi.l.liu@intel.com>,
	"Peng, Chao P" <chao.p.peng@intel.com>,
	Yi Sun <yi.y.sun@linux.intel.com>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Eduardo Habkost <eduardo@habkost.net>
Subject: Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode
Date: Wed, 11 Dec 2024 06:08:08 +0000	[thread overview]
Message-ID: <acfe82fe-f87e-4059-afd2-f59a1092d660@eviden.com> (raw)
In-Reply-To: <CACGkMEsRHytcZkR8OcK7cEiAordK9+EcG4Kei0RpABGApnBY4w@mail.gmail.com>




On 11/12/2024 04:03, Jason Wang wrote:
> Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
>
>
> On Wed, Dec 11, 2024 at 10:50 AM Duan, Zhenzhong
> <zhenzhong.duan@intel.com> wrote:
>> Hi Jason, Clement,
>>
>> Sorry for late reply, just back from vacation.
>>
>>> -----Original Message-----
>>> From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
>>> Subject: Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for
>>> scalable modern mode
>>>
>>>
>>>
>>>
>>> On 09/12/2024 07:24, Jason Wang wrote:
>>>> Caution: External email. Do not open attachments or click links, unless this
>>> email comes from a known sender and you know the content is safe.
>>>>
>>>> On Mon, Dec 9, 2024 at 2:15 PM CLEMENT MATHIEU--DRIF
>>>> <clement.mathieu--drif@eviden.com> wrote:
>>>>>
>>>>> On 09/12/2024 04:13, Jason Wang wrote:
>>>>>> Caution: External email. Do not open attachments or click links, unless this
>>> email comes from a known sender and you know the content is safe.
>>>>>>
>>>>>> On Wed, Dec 4, 2024 at 2:14 PM CLEMENT MATHIEU--DRIF
>>>>>> <clement.mathieu--drif@eviden.com> wrote:
>>>>>>>
>>>>>>> On 04/12/2024 04:34, Jason Wang wrote:
>>>>>>>> Caution: External email. Do not open attachments or click links, unless this
>>> email comes from a known sender and you know the content is safe.
>>>>>>>>
>>>>>>>> On Mon, Nov 11, 2024 at 4:39 PM Zhenzhong Duan
>>> <zhenzhong.duan@intel.com> wrote:
>>>>>>>>> Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities
>>>>>>>>> related to scalable mode translation, thus there are multiple
>>> combinations.
>>>>>>>>> This vIOMMU implementation wants to simplify it with a new property "x-
>>> flts".
>>>>>>>>> When enabled in scalable mode, first stage translation also known as
>>> scalable
>>>>>>>>> modern mode is supported. When enabled in legacy mode, throw out
>>> error.
>>>>>>>>> With scalable modern mode exposed to user, also accurate the pasid
>>> entry
>>>>>>>>> check in vtd_pe_type_check().
>>>>>>>>>
>>>>>>>>> Suggested-by: Jason Wang <jasowang@redhat.com>
>>>>>>>>> Signed-off-by: Yi Liu <yi.l.liu@intel.com>
>>>>>>>>> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
>>>>>>>>> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
>>>>>>>>> ---
>>>>>>>>>      hw/i386/intel_iommu_internal.h |  2 ++
>>>>>>>>>      hw/i386/intel_iommu.c          | 28 +++++++++++++++++++---------
>>>>>>>>>      2 files changed, 21 insertions(+), 9 deletions(-)
>>>>>>>>>
>>>>>>>>> diff --git a/hw/i386/intel_iommu_internal.h
>>> b/hw/i386/intel_iommu_internal.h
>>>>>>>>> index 2c977aa7da..e8b211e8b0 100644
>>>>>>>>> --- a/hw/i386/intel_iommu_internal.h
>>>>>>>>> +++ b/hw/i386/intel_iommu_internal.h
>> ...
>>>>>>>>> @@ -4737,6 +4742,11 @@ static bool
>>> vtd_decide_config(IntelIOMMUState *s, Error **errp)
>>>>>>>>>              }
>>>>>>>>>          }
>>>>>>>>>
>>>>>>>>> +    if (!s->scalable_mode && s->scalable_modern) {
>>>>>>>>> +        error_setg(errp, "Legacy mode: not support x-flts=on");
>>>>>>>> This seems to be wired, should we say "scalable mode is needed for
>>>>>>>> scalable modern mode"?
>>>>>>> Hi Jason,
>>>>>>>
>>>>>>> We agreed to use the following sentence: "x-flts is only available in
>>>>>>> scalable mode"
>>>>>>>
>>>>>>> Does it look goot to you?
>>>>>> Better but if we add more features to the scalable modern, we need to
>>>>>> change the error message here.
>>>>> Hi Jason
>>>>>
>>>>> Maybe the weirdness comes from the fact that x-flts on the command line
>>>>> is mapped to scalable_modern in the code?
>>>> Yes, actually the code checks if scalable mode is enabled if scalable
>>>> modern is enabled. But this is inconsistent with the error message
>>>> (though x-flts was implied there probably).
>>> Would you rename s->scalable_modern to s->flts?
>> Starting from v4, we replace x-scalable-mode=modern with flts=on on QEMU cmdline.
>> Scalable modern mode is an alias of stage-1 page table, so I reuse s->scalable_modern
>> in code, I'm fine to rename to s->flts if that's preferred. In that case, maybe we should
>> also drop the concept of 'scalable modern mode' totally?
> I think so, it helps to reduce the confusion.
>
> Thanks

Yep, at this stage dropping mentions to "modern" is clearer.

Thanks
 >cmd
>
>> Thanks
>> Zhenzhong

  reply	other threads:[~2024-12-11  6:09 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-11  8:34 [PATCH v5 00/20] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 01/20] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 02/20] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 03/20] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 04/20] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 05/20] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 06/20] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 07/20] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 08/20] intel_iommu: Check stage-1 translation result with interrupt range Zhenzhong Duan
2024-11-13  6:55   ` CLEMENT MATHIEU--DRIF
2024-11-13  8:49     ` Duan, Zhenzhong
2024-11-14  6:04       ` CLEMENT MATHIEU--DRIF
2024-12-04  2:11   ` Jason Wang
2024-11-11  8:34 ` [PATCH v5 09/20] intel_iommu: Set accessed and dirty bits during stage-1 translation Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 10/20] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 11/20] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 12/20] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 13/20] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-12-04  3:27   ` Jason Wang
2024-11-11  8:34 ` [PATCH v5 14/20] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 15/20] tests/acpi: q35: allow DMAR acpi table changes Zhenzhong Duan
2024-11-20  6:09   ` CLEMENT MATHIEU--DRIF
2024-12-04  3:27   ` Jason Wang
2024-11-11  8:34 ` [PATCH v5 16/20] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2 Zhenzhong Duan
2024-12-04  3:28   ` Jason Wang
2024-11-11  8:34 ` [PATCH v5 17/20] tests/acpi: q35: Update host address width in DMAR Zhenzhong Duan
2024-11-13  7:16   ` CLEMENT MATHIEU--DRIF
2024-11-13  8:50     ` Duan, Zhenzhong
2024-11-11  8:34 ` [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode Zhenzhong Duan
2024-11-19  6:54   ` CLEMENT MATHIEU--DRIF
2024-11-19  7:28     ` Duan, Zhenzhong
2024-11-19  8:59       ` CLEMENT MATHIEU--DRIF
2024-11-19  9:25         ` Duan, Zhenzhong
2024-11-20  6:11           ` CLEMENT MATHIEU--DRIF
2024-12-04  3:34   ` Jason Wang
2024-12-04  6:14     ` CLEMENT MATHIEU--DRIF
2024-12-09  3:13       ` Jason Wang
2024-12-09  6:14         ` CLEMENT MATHIEU--DRIF
2024-12-09  6:24           ` Jason Wang
2024-12-09  6:42             ` CLEMENT MATHIEU--DRIF
2024-12-11  2:22               ` Duan, Zhenzhong
2024-12-11  3:03                 ` Jason Wang
2024-12-11  6:08                   ` CLEMENT MATHIEU--DRIF [this message]
2024-11-11  8:34 ` [PATCH v5 19/20] intel_iommu: Introduce a property to control FS1GP cap bit setting Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 20/20] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-12-03  9:00 ` [PATCH v5 00/20] intel_iommu: Enable stage-1 translation for emulated device Duan, Zhenzhong

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