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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9a3372sm10824513f8f.21.2025.03.24.06.13.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Mar 2025 06:13:22 -0700 (PDT) Message-ID: Date: Mon, 24 Mar 2025 14:13:20 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 05/20] hw/arm/smmuv3-accel: Associate a pxb-pcie bus Content-Language: en-US To: Shameerali Kolothum Thodi , Nicolin Chen Cc: Donald Dutile , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , "jgg@nvidia.com" , "berrange@redhat.com" , "nathanc@nvidia.com" , "mochs@nvidia.com" , "smostafa@google.com" , Linuxarm , "Wangzhou (B)" , jiangkunkun , Jonathan Cameron , "zhangfei.gao@linaro.org" References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> <20250311141045.66620-6-shameerali.kolothum.thodi@huawei.com> <3d1312b411f04121a3be90879a915982@huawei.com> <2f84490d309440a4a2ac56fd893ddab8@huawei.com> From: Eric Auger In-Reply-To: <2f84490d309440a4a2ac56fd893ddab8@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Shameer, On 3/24/25 9:19 AM, Shameerali Kolothum Thodi wrote: > >> -----Original Message----- >> From: Nicolin Chen >> Sent: Thursday, March 20, 2025 5:03 PM >> To: Shameerali Kolothum Thodi >> Cc: Donald Dutile ; qemu-arm@nongnu.org; qemu- >> devel@nongnu.org; eric.auger@redhat.com; peter.maydell@linaro.org; >> jgg@nvidia.com; berrange@redhat.com; nathanc@nvidia.com; >> mochs@nvidia.com; smostafa@google.com; Linuxarm >> ; Wangzhou (B) ; >> jiangkunkun ; Jonathan Cameron >> ; zhangfei.gao@linaro.org >> Subject: Re: [RFC PATCH v2 05/20] hw/arm/smmuv3-accel: Associate a pxb- >> pcie bus >> >> On Wed, Mar 19, 2025 at 09:26:29AM +0000, Shameerali Kolothum Thodi >> wrote: >>> Having said that, current code only allows pxb-pcie root complexes >> avoiding >>> the pcie.0. The idea behind this was, user can use pcie.0 with a non accel >> SMMUv3 >>> for any emulated devices avoiding the performance bottlenecks we are >>> discussing for emulated dev+smmuv3-accel cases. But based on the >> feedback from >>> Eric and Daniel I will relax that restriction and will allow association with >> pcie.0. >> >> Just want a clarification here.. >> >> If VM has a passthrough device only: >> attach it to PCIE.0 <=> vSMMU0 (accel=on) > Yes. Basically support accel=on to pcie.0 as well. agreed we shall be able to instantiate the accelerated SMMU on pcie.0 too. > >> If VM has an emulated device and a passthrough device: >> attach the emulated device to PCIE.0 <=> vSMMU bypass (or accel=off?) >> attach the passthrough device to pxb-pcie <=> vSMMU0 (accel=on) > This can be other way around as well: > ie, > pass-through to pcie.0(accel=on) and emulated to any other pxb-pcie with accel = off. +1 > > I think the way bus numbers are allocated in Qemu for pcie.0 and pxb-pcie allows > us to support this in IORT ID maps. One trouble we may get into is possible bus reordering by the guest. I don't know the details but I remember that in certain conditions the guest can reorder the bus numbers. Besides what I don't get in the above discussion, related to whether the accelerated mode can also sipport emulated devices, is that if you use the originally suggested hierarchy (pxb-pcie + root port + VFIO device) you eventually get on guest side 2 devices protected by the SMMU instance: the root port and the VFIO device. They end up in different iommu groups. So there is already a mix of emulated and VFIO device. Thanks Eric > > Thanks, > Shameer >