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[92.88.170.6]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aba53231f5bsm123402466b.7.2025.02.13.04.37.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Feb 2025 04:37:11 -0800 (PST) Message-ID: Date: Thu, 13 Feb 2025 13:37:09 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/9] target/microblaze: Always use TARGET_LONG_BITS == 32 To: Richard Henderson , qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, "Edgar E. Iglesias" , Luc Michel , Sai Pavan Boddu , Michal Simek References: <20250212220155.1147144-1-richard.henderson@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250212220155.1147144-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philmd@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org +AMD folks On 12/2/25 23:01, Richard Henderson wrote: > Use out-of-line helpers to implement extended address memory ops. > With this, we can reduce TARGET_LONG_BITS to the more natural 32 > for this 32-bit cpu. I thought about something similar 2 months ago, but then realized MicroBlaze cores can be synthetized in 64-bit, and IIRC there is not much missing (I'd say effort would be to add 20% more of what we currently have). Just wanted to mention before taking the decision to restrict to 32-bit. OTOH if there are no plan for adding 64-bit support at AMD, then I'm more than happy to simplify by considering only 32-bit. > Richard Henderson (9): > target/microblaze: Split out mb_unaligned_access_internal > target/microblaze: Split out mb_transaction_failed_internal > target/microblaze: Implement extended address load/store out of line > target/microblaze: Use uint64_t for CPUMBState.ear > target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea > target/microblaze: Fix printf format in mmu_translate > target/microblaze: Use TARGET_LONG_BITS == 32 for system mode > target/microblaze: Drop DisasContext.r0 > target/microblaze: Simplify compute_ldst_addr_type{a,b}