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[24.31.215.130]) by smtp.gmail.com with ESMTPSA id h4sm11962277qkp.86.2021.09.27.06.10.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Sep 2021 06:11:00 -0700 (PDT) Subject: Re: [PATCH] tcg/riscv: Fix potential bug in clobbered call register set To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org References: <20210926213902.1713506-1-f4bug@amsat.org> From: Richard Henderson Message-ID: Date: Mon, 27 Sep 2021 09:10:57 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::82e; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82e.google.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-3.136, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , Joelle van Dyne , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/27/21 1:36 AM, Philippe Mathieu-Daudé wrote: >> There are not 64 registers, so this is incorrect. > > Currently there are 32 registers, but I was looking at this draft: > https://five-embeddev.com/riscv-v-spec/draft/v-spec.html#_vector_registers > "The vector extension adds 32 architectural vector registers, v0-v31 > to the base scalar RISC-V ISA." > If this were to be implemented (and available on the host), wouldn't > we have 64 registers? Sure. But there are *lots* of changes required before that happens, and certainly you shouldn't be assuming what the ABI is now. > Eventually this line would be easier to review as: > > tcg_target_call_clobber_regs = MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS); Would it? Or would it be eaier to review with tcg_target_call_clobber_regs = 0; followed by a set of each register that is call clobbered. Why are you assuming that it's safer to list unknown registers as call-clobbered? IF ANYTHING, it might be safer to assume that all new registers are caller saved. But as a general principal, I also don't like register masks containing set bits outside the range of the mask. r~