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[2.142.37.90]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f0b513sm3229607f8f.30.2025.11.13.02.54.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Nov 2025 02:54:25 -0800 (PST) Message-ID: Date: Thu, 13 Nov 2025 11:54:22 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] Add RISCV Zilsd extension To: Roan Richmond , qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, qemu-devel@nongnu.org, alistair23@gmail.com References: <20251110090510.84103-1-roan.richmond@codethink.co.uk> From: Richard Henderson Content-Language: en-US In-Reply-To: <20251110090510.84103-1-roan.richmond@codethink.co.uk> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/10/25 10:05, Roan Richmond wrote: > +/* Zilsd extension adds load/store double for 32bit arch */ > +static bool gen_store_zilsd(DisasContext *ctx, arg_sb *a) > +{ > + TCGv data_1 = tcg_temp_new(); > + TCGv data_2 = tcg_temp_new(); > + if (a->rs2 != 0) { > + data_1 = get_gpr(ctx, a->rs2, EXT_NONE); > + data_2 = get_gpr(ctx, a->rs2+1, EXT_NONE); > + } > + TCGv addr_1 = get_address(ctx, a->rs1, a->imm); > + TCGv addr_2 = get_address(ctx, a->rs1, a->imm+4); > + > + if (ctx->ztso) { > + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); > + } > + > + tcg_gen_qemu_st_tl(data_1, addr_1, ctx->mem_idx, MO_SL); > + tcg_gen_qemu_st_tl(data_2, addr_2, ctx->mem_idx, MO_SL); This is wrong, because if rs2 == 0, then data_1 and data_2 are uninitialized. If you're testing properly with --enable-debug-tcg, this should trigger an assertion failure. You wanted if (a->rs2 == 0) { data_1 = tcg_constant_tl(0); data_2 = data_1; } else { data_1 = get_gpr(ctx, a->rs2, EXT_NONE); data_2 = get_gpr(ctx, a->rs2 + 1, EXT_NONE); } You're also missing the endianness indicator: mo_endian(). You really should consider combining the two halves so that you can perform one 64-bit store. While I see that the spec allows the store to be non-atomic, you still probably do not want to to allow the first half store to succeed when the second half store faults. I don't see clear language about that. Anyway, that's as simple as TCGv_i64 data; MemOp end = mo_endian(ctx); if (a->rs2 == 0) { data = tcg_constant_i64(0); } else { TCGv data_1 = get_gpr(ctx, a->rs2, EXT_NONE); TCGv data_2 = get_gpr(ctx, a->rs2 + 1, EXT_NONE); data = tcg_temp_new_i64(); if (end == MO_LE) { tcg_gen_concat_tl_i64(data, data_1, data_2); } else { tcg_gen_concat_tl_i64(data, data_2, data_1); } } tcg_gen_qemu_st_i64(data, addr, ctx->mem_idx, MO_UQ | end); r~