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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5f0b03bsm3273154a91.34.2024.10.11.07.47.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Oct 2024 07:47:10 -0700 (PDT) Message-ID: Date: Fri, 11 Oct 2024 07:47:08 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 19/23] accel/tcg: Always use IntervalTree for code lookups To: Pierrick Bouvier , qemu-devel@nongnu.org References: <20241009150855.804605-1-richard.henderson@linaro.org> <20241009150855.804605-20-richard.henderson@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/9/24 17:35, Pierrick Bouvier wrote: >> @@ -1061,15 +1061,13 @@ static inline void tlb_set_compare(CPUTLBEntryFull *full, >> CPUTLBEntry *ent, >>                                      vaddr address, int flags, >>                                      MMUAccessType access_type, bool enable) >>   { >> -    if (enable) { >> -        address |= flags & TLB_FLAGS_MASK; >> -        flags &= TLB_SLOW_FLAGS_MASK; >> -        if (flags) { >> -            address |= TLB_FORCE_SLOW; >> -        } >> -    } else { >> -        address = -1; >> -        flags = 0; >> +    if (!enable) { >> +    address = TLB_INVALID_MASK; >> +    } >> +    address |= flags & TLB_FLAGS_MASK; >> +    flags &= TLB_SLOW_FLAGS_MASK; >> +    if (flags) { >> +        address |= TLB_FORCE_SLOW; >>       } > > I'm not sure to follow this change correctly. > After, the final address and flags value depend on flags in parameter, while before, it > used to depend on flags & enable parameter. This deserves to be split out; I even thought about it Monday night but then forgot when I restarted on Tuesday morning. Before, address is -1 for disabled, mostly because that mirrors what you get with memset to initialize the tlb. All of the flags are discarded. But the only thing that's important is that TLB_INVALID_MASK is set. After, TLB_INVALID_MASK is still set, but the flags are retained. This is because we want a source of those flags to use for MMU_INST_FETCH. With this patch set we no longer store flags for execute and instead grab them from the flags for read. From tlb_set_page_full... >> @@ -1215,9 +1213,6 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, >>       /* Now calculate the new entry */ >>       node->copy.addend = addend - addr_page; >> -    tlb_set_compare(full, &node->copy, addr_page, read_flags, >> -                    MMU_INST_FETCH, prot & PAGE_EXEC); >> - >>       if (wp_flags & BP_MEM_READ) { >>           read_flags |= TLB_WATCHPOINT; >>       } ... we can see that the only difference between the two is the watchpoint bit. Importantly, TLB_MMIO is common to all three comparators. > Sounds good to have a fast path for code fetch. Did you measure the benefit, or just > implemented this thinking it's worth? This is not about a fast path for code fetch, but always using the *slow* path. The object is to repurpose one word from CPUTLBEntry, removed here and added back in the next patch, to link CPUTLBEntry to CPUTLBEntryTree without changing sizeof(CPUTLBEntry). r~