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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3ee0fbf53cesm24281346f8f.59.2025.09.23.00.30.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Sep 2025 00:30:06 -0700 (PDT) Message-ID: Date: Tue, 23 Sep 2025 09:30:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 03/12] target/alpha: Simplify call_pal implementation To: Richard Henderson , qemu-devel@nongnu.org References: <20250923023922.3102471-1-richard.henderson@linaro.org> <20250923023922.3102471-4-richard.henderson@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250923023922.3102471-4-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 23/9/25 04:39, Richard Henderson wrote: > Since 288a5fe980f, we don't link translation blocks > directly to palcode entry points. If we load palbr > from env instead of encoding the constant, we avoid > all need for tb_flush(). > > Signed-off-by: Richard Henderson > --- > target/alpha/helper.h | 1 - > target/alpha/sys_helper.c | 6 ------ > target/alpha/translate.c | 21 ++++++--------------- > 3 files changed, 6 insertions(+), 22 deletions(-) > > diff --git a/target/alpha/helper.h b/target/alpha/helper.h > index d60f208703..788d2fbf28 100644 > --- a/target/alpha/helper.h > +++ b/target/alpha/helper.h > @@ -90,7 +90,6 @@ DEF_HELPER_FLAGS_2(ieee_input_s, TCG_CALL_NO_WG, void, env, i64) > #if !defined (CONFIG_USER_ONLY) > DEF_HELPER_FLAGS_1(tbia, TCG_CALL_NO_RWG, void, env) > DEF_HELPER_FLAGS_2(tbis, TCG_CALL_NO_RWG, void, env, i64) > -DEF_HELPER_FLAGS_1(tb_flush, TCG_CALL_NO_RWG, void, env) > > DEF_HELPER_1(halt, void, i64) > > diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c > index 51e3254428..87e37605c1 100644 > --- a/target/alpha/sys_helper.c > +++ b/target/alpha/sys_helper.c > @@ -20,7 +20,6 @@ > #include "qemu/osdep.h" > #include "cpu.h" > #include "exec/cputlb.h" > -#include "exec/tb-flush.h" > #include "exec/helper-proto.h" > #include "system/runstate.h" > #include "system/system.h" > @@ -38,11 +37,6 @@ void helper_tbis(CPUAlphaState *env, uint64_t p) > tlb_flush_page(env_cpu(env), p); > } > > -void helper_tb_flush(CPUAlphaState *env) > -{ > - tb_flush(env_cpu(env)); > -} > - > void helper_halt(uint64_t restart) > { > if (restart) { > diff --git a/target/alpha/translate.c b/target/alpha/translate.c > index cebab0318c..f11b382438 100644 > --- a/target/alpha/translate.c > +++ b/target/alpha/translate.c > @@ -48,8 +48,6 @@ struct DisasContext { > > #ifdef CONFIG_USER_ONLY > MemOp unalign; > -#else > - uint64_t palbr; > #endif > uint32_t tbflags; > int mem_idx; > @@ -1155,7 +1153,6 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode) > #else > { > TCGv tmp = tcg_temp_new(); > - uint64_t entry; > > gen_pc_disp(ctx, tmp, 0); > if (ctx->tbflags & ENV_FLAG_PAL_MODE) { > @@ -1165,12 +1162,11 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode) > } > tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUAlphaState, exc_addr)); > > - entry = ctx->palbr; > - entry += (palcode & 0x80 > - ? 0x2000 + (palcode - 0x80) * 64 > - : 0x1000 + palcode * 64); > - > - tcg_gen_movi_i64(cpu_pc, entry); > + tcg_gen_ld_i64(cpu_pc, tcg_env, offsetof(CPUAlphaState, palbr)); > + tcg_gen_addi_i64(cpu_pc, cpu_pc, > + palcode & 0x80 > + ? 0x2000 + (palcode - 0x80) * 64 > + : 0x1000 + palcode * 64); > return DISAS_PC_UPDATED; > } > #endif > @@ -1292,11 +1288,7 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno) > case 7: > /* PALBR */ > tcg_gen_st_i64(vb, tcg_env, offsetof(CPUAlphaState, palbr)); > - /* Changing the PAL base register implies un-chaining all of the TBs > - that ended with a CALL_PAL. Since the base register usually only > - changes during boot, flushing everything works well. */ > - gen_helper_tb_flush(tcg_env); > - return DISAS_PC_STALE; > + break; > > case 32 ... 39: > /* Accessing the "non-shadow" general registers. */ > @@ -2874,7 +2866,6 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) > ctx->ir = cpu_std_ir; > ctx->unalign = (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); > #else > - ctx->palbr = env->palbr; > ctx->ir = (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir); > #endif > Probably unrelated but still same target, could you also update the comment added in commit fe57ca82b09 ("target-alpha: Add placeholders for missing userspace PALcalls")? case 0x86: /* IMB */ /* ??? We can probably elide the code using page_unprotect that is checking for self-modifying code. Instead we could simply call tb_flush here. Until we work out the changes required to turn off the extra write protection, this can be a no-op. */ break;