* [RFC PATCH 37/75] system/rtc.c: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
@ 2023-10-13 7:47 ` Emmanouil Pitsidianakis
2023-10-13 7:47 ` [RFC PATCH 38/75] hw/scsi: " Emmanouil Pitsidianakis
` (18 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:47 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block; +Cc: Emmanouil Pitsidianakis
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
system/rtc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/system/rtc.c b/system/rtc.c
index 4904581abe..bb406542c8 100644
--- a/system/rtc.c
+++ b/system/rtc.c
@@ -48,22 +48,22 @@ QEMUClockType rtc_clock;
/***********************************************************/
/* RTC reference time/date access */
static time_t qemu_ref_timedate(QEMUClockType clock)
{
time_t value = qemu_clock_get_ms(clock) / 1000;
switch (clock) {
case QEMU_CLOCK_REALTIME:
value -= rtc_realtime_clock_offset;
- /* fall through */
+ fallthrough;
case QEMU_CLOCK_VIRTUAL:
value += rtc_ref_start_datetime;
break;
case QEMU_CLOCK_HOST:
if (rtc_base_type == RTC_BASE_DATETIME) {
value -= rtc_host_datetime_offset;
}
break;
default:
assert(0);
}
return value;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 38/75] hw/scsi: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
2023-10-13 7:47 ` [RFC PATCH 37/75] system/rtc.c: add fallthrough pseudo-keyword Emmanouil Pitsidianakis
@ 2023-10-13 7:47 ` Emmanouil Pitsidianakis
2023-10-13 7:47 ` [RFC PATCH 39/75] hw/sd/sdhci.c: " Emmanouil Pitsidianakis
` (17 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:47 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block
Cc: Emmanouil Pitsidianakis, Paolo Bonzini, Fam Zheng,
Hannes Reinecke
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/scsi/esp.c | 2 +-
hw/scsi/megasas.c | 2 +-
hw/scsi/scsi-bus.c | 4 ++--
hw/scsi/scsi-disk.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 9b11d8c573..d6c8298f51 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -1022,130 +1022,130 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
{
trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
switch (saddr) {
case ESP_TCHI:
s->tchi_written = true;
- /* fall through */
+ fallthrough;
case ESP_TCLO:
case ESP_TCMID:
s->rregs[ESP_RSTAT] &= ~STAT_TC;
break;
case ESP_FIFO:
if (s->do_cmd) {
esp_fifo_push(&s->cmdfifo, val);
/*
* If any unexpected message out/command phase data is
* transferred using non-DMA, raise the interrupt
*/
if (s->rregs[ESP_CMD] == CMD_TI) {
s->rregs[ESP_RINTR] |= INTR_BS;
esp_raise_irq(s);
}
} else {
esp_fifo_push(&s->fifo, val);
}
break;
case ESP_CMD:
s->rregs[saddr] = val;
if (val & CMD_DMA) {
s->dma = 1;
/* Reload DMA counter. */
if (esp_get_stc(s) == 0) {
esp_set_tc(s, 0x10000);
} else {
esp_set_tc(s, esp_get_stc(s));
}
} else {
s->dma = 0;
}
switch (val & CMD_CMD) {
case CMD_NOP:
trace_esp_mem_writeb_cmd_nop(val);
break;
case CMD_FLUSH:
trace_esp_mem_writeb_cmd_flush(val);
fifo8_reset(&s->fifo);
break;
case CMD_RESET:
trace_esp_mem_writeb_cmd_reset(val);
esp_soft_reset(s);
break;
case CMD_BUSRESET:
trace_esp_mem_writeb_cmd_bus_reset(val);
esp_bus_reset(s);
if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
s->rregs[ESP_RINTR] |= INTR_RST;
esp_raise_irq(s);
}
break;
case CMD_TI:
trace_esp_mem_writeb_cmd_ti(val);
handle_ti(s);
break;
case CMD_ICCS:
trace_esp_mem_writeb_cmd_iccs(val);
write_response(s);
s->rregs[ESP_RINTR] |= INTR_FC;
s->rregs[ESP_RSTAT] |= STAT_MI;
break;
case CMD_MSGACC:
trace_esp_mem_writeb_cmd_msgacc(val);
s->rregs[ESP_RINTR] |= INTR_DC;
s->rregs[ESP_RSEQ] = 0;
s->rregs[ESP_RFLAGS] = 0;
esp_raise_irq(s);
break;
case CMD_PAD:
trace_esp_mem_writeb_cmd_pad(val);
s->rregs[ESP_RSTAT] = STAT_TC;
s->rregs[ESP_RINTR] |= INTR_FC;
s->rregs[ESP_RSEQ] = 0;
break;
case CMD_SATN:
trace_esp_mem_writeb_cmd_satn(val);
break;
case CMD_RSTATN:
trace_esp_mem_writeb_cmd_rstatn(val);
break;
case CMD_SEL:
trace_esp_mem_writeb_cmd_sel(val);
handle_s_without_atn(s);
break;
case CMD_SELATN:
trace_esp_mem_writeb_cmd_selatn(val);
handle_satn(s);
break;
case CMD_SELATNS:
trace_esp_mem_writeb_cmd_selatns(val);
handle_satn_stop(s);
break;
case CMD_ENSEL:
trace_esp_mem_writeb_cmd_ensel(val);
s->rregs[ESP_RINTR] = 0;
break;
case CMD_DISSEL:
trace_esp_mem_writeb_cmd_dissel(val);
s->rregs[ESP_RINTR] = 0;
esp_raise_irq(s);
break;
default:
trace_esp_error_unhandled_command(val);
break;
}
break;
case ESP_WBUSID ... ESP_WSYNO:
break;
case ESP_CFG1:
case ESP_CFG2: case ESP_CFG3:
case ESP_RES3: case ESP_RES4:
s->rregs[saddr] = val;
break;
case ESP_WCCF ... ESP_WTEST:
break;
default:
trace_esp_error_invalid_write(val, saddr);
return;
}
s->wregs[saddr] = val;
}
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 32c70c9e99..54e4d7c8b6 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -2084,113 +2084,113 @@ static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
static void megasas_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MegasasState *s = opaque;
PCIDevice *pci_dev = PCI_DEVICE(s);
uint64_t frame_addr;
uint32_t frame_count;
int i;
switch (addr) {
case MFI_IDB:
trace_megasas_mmio_writel("MFI_IDB", val);
if (val & MFI_FWINIT_ABORT) {
/* Abort all pending cmds */
for (i = 0; i < s->fw_cmds; i++) {
megasas_abort_command(&s->frames[i]);
}
}
if (val & MFI_FWINIT_READY) {
/* move to FW READY */
megasas_soft_reset(s);
}
if (val & MFI_FWINIT_MFIMODE) {
/* discard MFIs */
}
if (val & MFI_FWINIT_STOP_ADP) {
/* Terminal error, stop processing */
s->fw_state = MFI_FWSTATE_FAULT;
}
break;
case MFI_OMSK:
trace_megasas_mmio_writel("MFI_OMSK", val);
s->intr_mask = val;
if (!megasas_intr_enabled(s) &&
!msi_enabled(pci_dev) &&
!msix_enabled(pci_dev)) {
trace_megasas_irq_lower();
pci_irq_deassert(pci_dev);
}
if (megasas_intr_enabled(s)) {
if (msix_enabled(pci_dev)) {
trace_megasas_msix_enabled(0);
} else if (msi_enabled(pci_dev)) {
trace_megasas_msi_enabled(0);
} else {
trace_megasas_intr_enabled();
}
} else {
trace_megasas_intr_disabled();
megasas_soft_reset(s);
}
break;
case MFI_ODCR0:
trace_megasas_mmio_writel("MFI_ODCR0", val);
s->doorbell = 0;
if (megasas_intr_enabled(s)) {
if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
trace_megasas_irq_lower();
pci_irq_deassert(pci_dev);
}
}
break;
case MFI_IQPH:
trace_megasas_mmio_writel("MFI_IQPH", val);
/* Received high 32 bits of a 64 bit MFI frame address */
s->frame_hi = val;
break;
case MFI_IQPL:
trace_megasas_mmio_writel("MFI_IQPL", val);
/* Received low 32 bits of a 64 bit MFI frame address */
- /* Fallthrough */
+ fallthrough;
case MFI_IQP:
if (addr == MFI_IQP) {
trace_megasas_mmio_writel("MFI_IQP", val);
/* Received 64 bit MFI frame address */
s->frame_hi = 0;
}
frame_addr = (val & ~0x1F);
/* Add possible 64 bit offset */
frame_addr |= ((uint64_t)s->frame_hi << 32);
s->frame_hi = 0;
frame_count = (val >> 1) & 0xF;
megasas_handle_frame(s, frame_addr, frame_count);
break;
case MFI_SEQ:
trace_megasas_mmio_writel("MFI_SEQ", val);
/* Magic sequence to start ADP reset */
if (adp_reset_seq[s->adp_reset++] == val) {
if (s->adp_reset == 6) {
s->adp_reset = 0;
s->diag = MFI_DIAG_WRITE_ENABLE;
}
} else {
s->adp_reset = 0;
s->diag = 0;
}
break;
case MFI_DIAG:
trace_megasas_mmio_writel("MFI_DIAG", val);
/* ADP reset */
if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
(val & MFI_DIAG_RESET_ADP)) {
s->diag |= MFI_DIAG_RESET_ADP;
megasas_soft_reset(s);
s->adp_reset = 0;
s->diag = 0;
}
break;
default:
trace_megasas_mmio_invalid_writel(addr, val);
break;
}
}
diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c
index fc4b77fdb0..a1c298a92c 100644
--- a/hw/scsi/scsi-bus.c
+++ b/hw/scsi/scsi-bus.c
@@ -1015,141 +1015,141 @@ static int ata_passthrough_16_xfer(SCSIDevice *dev, uint8_t *buf)
static int scsi_req_xfer(SCSICommand *cmd, SCSIDevice *dev, uint8_t *buf)
{
cmd->xfer = scsi_cdb_xfer(buf);
switch (buf[0]) {
case TEST_UNIT_READY:
case REWIND:
case START_STOP:
case SET_CAPACITY:
case WRITE_FILEMARKS:
case WRITE_FILEMARKS_16:
case SPACE:
case RESERVE:
case RELEASE:
case ERASE:
case ALLOW_MEDIUM_REMOVAL:
case SEEK_10:
case SYNCHRONIZE_CACHE:
case SYNCHRONIZE_CACHE_16:
case LOCATE_16:
case LOCK_UNLOCK_CACHE:
case SET_CD_SPEED:
case SET_LIMITS:
case WRITE_LONG_10:
case UPDATE_BLOCK:
case RESERVE_TRACK:
case SET_READ_AHEAD:
case PRE_FETCH:
case PRE_FETCH_16:
case ALLOW_OVERWRITE:
cmd->xfer = 0;
break;
case VERIFY_10:
case VERIFY_12:
case VERIFY_16:
if ((buf[1] & 2) == 0) {
cmd->xfer = 0;
} else if ((buf[1] & 4) != 0) {
cmd->xfer = 1;
}
cmd->xfer *= dev->blocksize;
break;
case MODE_SENSE:
break;
case WRITE_SAME_10:
case WRITE_SAME_16:
cmd->xfer = buf[1] & 1 ? 0 : dev->blocksize;
break;
case READ_CAPACITY_10:
cmd->xfer = 8;
break;
case READ_BLOCK_LIMITS:
cmd->xfer = 6;
break;
case SEND_VOLUME_TAG:
/* GPCMD_SET_STREAMING from multimedia commands. */
if (dev->type == TYPE_ROM) {
cmd->xfer = buf[10] | (buf[9] << 8);
} else {
cmd->xfer = buf[9] | (buf[8] << 8);
}
break;
case WRITE_6:
/* length 0 means 256 blocks */
if (cmd->xfer == 0) {
cmd->xfer = 256;
}
- /* fall through */
+ fallthrough;
case WRITE_10:
case WRITE_VERIFY_10:
case WRITE_12:
case WRITE_VERIFY_12:
case WRITE_16:
case WRITE_VERIFY_16:
cmd->xfer *= dev->blocksize;
break;
case READ_6:
case READ_REVERSE:
/* length 0 means 256 blocks */
if (cmd->xfer == 0) {
cmd->xfer = 256;
}
- /* fall through */
+ fallthrough;
case READ_10:
case READ_12:
case READ_16:
cmd->xfer *= dev->blocksize;
break;
case FORMAT_UNIT:
/* MMC mandates the parameter list to be 12-bytes long. Parameters
* for block devices are restricted to the header right now. */
if (dev->type == TYPE_ROM && (buf[1] & 16)) {
cmd->xfer = 12;
} else {
cmd->xfer = (buf[1] & 16) == 0 ? 0 : (buf[1] & 32 ? 8 : 4);
}
break;
case INQUIRY:
case RECEIVE_DIAGNOSTIC:
case SEND_DIAGNOSTIC:
cmd->xfer = buf[4] | (buf[3] << 8);
break;
case READ_CD:
case READ_BUFFER:
case WRITE_BUFFER:
case SEND_CUE_SHEET:
cmd->xfer = buf[8] | (buf[7] << 8) | (buf[6] << 16);
break;
case PERSISTENT_RESERVE_OUT:
cmd->xfer = ldl_be_p(&buf[5]) & 0xffffffffULL;
break;
case ERASE_12:
if (dev->type == TYPE_ROM) {
/* MMC command GET PERFORMANCE. */
cmd->xfer = scsi_get_performance_length(buf[9] | (buf[8] << 8),
buf[10], buf[1] & 0x1f);
}
break;
case MECHANISM_STATUS:
case READ_DVD_STRUCTURE:
case SEND_DVD_STRUCTURE:
case MAINTENANCE_OUT:
case MAINTENANCE_IN:
if (dev->type == TYPE_ROM) {
/* GPCMD_REPORT_KEY and GPCMD_SEND_KEY from multi media commands */
cmd->xfer = buf[9] | (buf[8] << 8);
}
break;
case ATA_PASSTHROUGH_12:
if (dev->type == TYPE_ROM) {
/* BLANK command of MMC */
cmd->xfer = 0;
} else {
cmd->xfer = ata_passthrough_12_xfer(dev, buf);
}
break;
case ATA_PASSTHROUGH_16:
cmd->xfer = ata_passthrough_16_xfer(dev, buf);
break;
}
return 0;
}
diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
index 6691f5edb8..6564ca638c 100644
--- a/hw/scsi/scsi-disk.c
+++ b/hw/scsi/scsi-disk.c
@@ -2256,86 +2256,86 @@ illegal_lba:
static int32_t scsi_disk_dma_command(SCSIRequest *req, uint8_t *buf)
{
SCSIDiskReq *r = DO_UPCAST(SCSIDiskReq, req, req);
SCSIDiskState *s = DO_UPCAST(SCSIDiskState, qdev, req->dev);
SCSIDiskClass *sdc = (SCSIDiskClass *) object_get_class(OBJECT(s));
uint32_t len;
uint8_t command;
command = buf[0];
if (!blk_is_available(s->qdev.conf.blk)) {
scsi_check_condition(r, SENSE_CODE(NO_MEDIUM));
return 0;
}
len = scsi_data_cdb_xfer(r->req.cmd.buf);
switch (command) {
case READ_6:
case READ_10:
case READ_12:
case READ_16:
trace_scsi_disk_dma_command_READ(r->req.cmd.lba, len);
/* Protection information is not supported. For SCSI versions 2 and
* older (as determined by snooping the guest's INQUIRY commands),
* there is no RD/WR/VRPROTECT, so skip this check in these versions.
*/
if (s->qdev.scsi_version > 2 && (r->req.cmd.buf[1] & 0xe0)) {
goto illegal_request;
}
if (!check_lba_range(s, r->req.cmd.lba, len)) {
goto illegal_lba;
}
r->sector = r->req.cmd.lba * (s->qdev.blocksize / BDRV_SECTOR_SIZE);
r->sector_count = len * (s->qdev.blocksize / BDRV_SECTOR_SIZE);
break;
case WRITE_6:
case WRITE_10:
case WRITE_12:
case WRITE_16:
case WRITE_VERIFY_10:
case WRITE_VERIFY_12:
case WRITE_VERIFY_16:
if (!blk_is_writable(s->qdev.conf.blk)) {
scsi_check_condition(r, SENSE_CODE(WRITE_PROTECTED));
return 0;
}
trace_scsi_disk_dma_command_WRITE(
(command & 0xe) == 0xe ? "And Verify " : "",
r->req.cmd.lba, len);
- /* fall through */
+ fallthrough;
case VERIFY_10:
case VERIFY_12:
case VERIFY_16:
/* We get here only for BYTCHK == 0x01 and only for scsi-block.
* As far as DMA is concerned, we can treat it the same as a write;
* scsi_block_do_sgio will send VERIFY commands.
*/
if (s->qdev.scsi_version > 2 && (r->req.cmd.buf[1] & 0xe0)) {
goto illegal_request;
}
if (!check_lba_range(s, r->req.cmd.lba, len)) {
goto illegal_lba;
}
r->sector = r->req.cmd.lba * (s->qdev.blocksize / BDRV_SECTOR_SIZE);
r->sector_count = len * (s->qdev.blocksize / BDRV_SECTOR_SIZE);
break;
default:
abort();
illegal_request:
scsi_check_condition(r, SENSE_CODE(INVALID_FIELD));
return 0;
illegal_lba:
scsi_check_condition(r, SENSE_CODE(LBA_OUT_OF_RANGE));
return 0;
}
r->need_fua_emulation = sdc->need_fua_emulation(&r->req.cmd);
if (r->sector_count == 0) {
scsi_req_complete(&r->req, GOOD);
}
assert(r->iov.iov_len == 0);
if (r->req.cmd.mode == SCSI_XFER_TO_DEV) {
return -r->sector_count * BDRV_SECTOR_SIZE;
} else {
return r->sector_count * BDRV_SECTOR_SIZE;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 39/75] hw/sd/sdhci.c: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
2023-10-13 7:47 ` [RFC PATCH 37/75] system/rtc.c: add fallthrough pseudo-keyword Emmanouil Pitsidianakis
2023-10-13 7:47 ` [RFC PATCH 38/75] hw/scsi: " Emmanouil Pitsidianakis
@ 2023-10-13 7:47 ` Emmanouil Pitsidianakis
2023-10-13 7:47 ` [RFC PATCH 40/75] linux-user: " Emmanouil Pitsidianakis
` (16 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:47 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block
Cc: Emmanouil Pitsidianakis, Philippe Mathieu-Daudé, Bin Meng
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/sd/sdhci.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 5564765a9b..5c641d24de 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -75,138 +75,138 @@ static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc,
static void sdhci_check_capareg(SDHCIState *s, Error **errp)
{
uint64_t msk = s->capareg;
uint32_t val;
bool y;
switch (s->sd_spec_version) {
case 4:
val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4);
trace_sdhci_capareg("64-bit system bus (v4)", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II);
trace_sdhci_capareg("UHS-II", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3);
trace_sdhci_capareg("ADMA3", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0);
- /* fallthrough */
+ fallthrough;
case 3:
val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT);
trace_sdhci_capareg("async interrupt", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE);
if (val) {
error_setg(errp, "slot-type not supported");
return;
}
trace_sdhci_capareg("slot type", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0);
if (val != 2) {
val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT);
trace_sdhci_capareg("8-bit bus", val);
}
msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED);
trace_sdhci_capareg("bus speed mask", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH);
trace_sdhci_capareg("driver strength mask", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING);
trace_sdhci_capareg("timer re-tuning", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING);
trace_sdhci_capareg("use SDR50 tuning", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE);
trace_sdhci_capareg("re-tuning mode", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT);
trace_sdhci_capareg("clock multiplier", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0);
- /* fallthrough */
+ fallthrough;
case 2: /* default version */
val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2);
trace_sdhci_capareg("ADMA2", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1);
trace_sdhci_capareg("ADMA1", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT);
trace_sdhci_capareg("64-bit system bus (v3)", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0);
- /* fallthrough */
+ fallthrough;
case 1:
y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT);
msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ);
trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val);
if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) {
return;
}
msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ);
trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val);
if (sdhci_check_capab_freq_range(s, "base", val, errp)) {
return;
}
msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH);
if (val >= 3) {
error_setg(errp, "block size can be 512, 1024 or 2048 only");
return;
}
trace_sdhci_capareg("max block length", sdhci_get_fifolen(s));
msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED);
trace_sdhci_capareg("high speed", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA);
trace_sdhci_capareg("SDMA", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME);
trace_sdhci_capareg("suspend/resume", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33);
trace_sdhci_capareg("3.3v", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30);
trace_sdhci_capareg("3.0v", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18);
trace_sdhci_capareg("1.8v", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0);
break;
default:
error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version);
}
if (msk) {
qemu_log_mask(LOG_UNIMP,
"SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk);
}
}
@@ -1688,160 +1688,160 @@ static void
usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
{
SDHCIState *s = SYSBUS_SDHCI(opaque);
uint8_t hostctl1;
uint32_t value = (uint32_t)val;
switch (offset) {
case USDHC_DLL_CTRL:
case USDHC_TUNE_CTRL_STATUS:
case USDHC_UNDOCUMENTED_REG27:
case USDHC_TUNING_CTRL:
case USDHC_WTMK_LVL:
break;
case USDHC_VENDOR_SPEC:
s->vendor_spec = value;
switch (s->vendor) {
case SDHCI_VENDOR_IMX:
if (value & USDHC_IMX_FRC_SDCLK_ON) {
s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
} else {
s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
}
break;
default:
break;
}
break;
case SDHC_HOSTCTL:
/*
* Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL)
*
* 7 6 5 4 3 2 1 0
* |-----------+--------+--------+-----------+----------+---------|
* | Card | Card | Endian | DATA3 | Data | Led |
* | Detect | Detect | Mode | as Card | Transfer | Control |
* | Signal | Test | | Detection | Width | |
* | Selection | Level | | Pin | | |
* |-----------+--------+--------+-----------+----------+---------|
*
* and 0x29
*
* 15 10 9 8
* |----------+------|
* | Reserved | DMA |
* | | Sel. |
* | | |
* |----------+------|
*
* and here's what SDCHI spec expects those offsets to be:
*
* 0x28 (Host Control Register)
*
* 7 6 5 4 3 2 1 0
* |--------+--------+----------+------+--------+----------+---------|
* | Card | Card | Extended | DMA | High | Data | LED |
* | Detect | Detect | Data | Sel. | Speed | Transfer | Control |
* | Signal | Test | Transfer | | Enable | Width | |
* | Sel. | Level | Width | | | | |
* |--------+--------+----------+------+--------+----------+---------|
*
* and 0x29 (Power Control Register)
*
* |----------------------------------|
* | Power Control Register |
* | |
* | Description omitted, |
* | since it has no analog in ESDHCI |
* | |
* |----------------------------------|
*
* Since offsets 0x2A and 0x2B should be compatible between
* both IP specs we only need to reconcile least 16-bit of the
* word we've been given.
*/
/*
* First, save bits 7 6 and 0 since they are identical
*/
hostctl1 = value & (SDHC_CTRL_LED |
SDHC_CTRL_CDTEST_INS |
SDHC_CTRL_CDTEST_EN);
/*
* Second, split "Data Transfer Width" from bits 2 and 1 in to
* bits 5 and 1
*/
if (value & USDHC_CTRL_8BITBUS) {
hostctl1 |= SDHC_CTRL_8BITBUS;
}
if (value & USDHC_CTRL_4BITBUS) {
hostctl1 |= USDHC_CTRL_4BITBUS;
}
/*
* Third, move DMA select from bits 9 and 8 to bits 4 and 3
*/
hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3));
/*
* Now place the corrected value into low 16-bit of the value
* we are going to give standard SDHCI write function
*
* NOTE: This transformation should be the inverse of what can
* be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux
* kernel
*/
value &= ~UINT16_MAX;
value |= hostctl1;
value |= (uint16_t)s->pwrcon << 8;
sdhci_write(opaque, offset, value, size);
break;
case USDHC_MIX_CTRL:
/*
* So, when SD/MMC stack in Linux tries to write to "Transfer
* Mode Register", ESDHC i.MX quirk code will translate it
* into a write to ESDHC_MIX_CTRL, so we do the opposite in
* order to get where we started
*
* Note that Auto CMD23 Enable bit is located in a wrong place
* on i.MX, but since it is not used by QEMU we do not care.
*
* We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
* here because it will result in a call to
* sdhci_send_command(s) which we don't want.
*
*/
s->trnmod = value & UINT16_MAX;
break;
case SDHC_TRNMOD:
/*
* Similar to above, but this time a write to "Command
* Register" will be translated into a 4-byte write to
* "Transfer Mode register" where lower 16-bit of value would
* be set to zero. So what we do is fill those bits with
* cached value from s->trnmod and let the SDHCI
* infrastructure handle the rest
*/
sdhci_write(opaque, offset, val | s->trnmod, size);
break;
case SDHC_BLKSIZE:
/*
* ESDHCI does not implement "Host SDMA Buffer Boundary", and
* Linux driver will try to zero this field out which will
* break the rest of SDHCI emulation.
*
* Linux defaults to maximum possible setting (512K boundary)
* and it seems to be the only option that i.MX IP implements,
* so we artificially set it to that value.
*/
val |= 0x7 << 12;
- /* FALLTHROUGH */
+ fallthrough;
default:
sdhci_write(opaque, offset, val, size);
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 40/75] linux-user: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (2 preceding siblings ...)
2023-10-13 7:47 ` [RFC PATCH 39/75] hw/sd/sdhci.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:47 ` Emmanouil Pitsidianakis
2023-10-13 7:47 ` [RFC PATCH 41/75] hw/i386: " Emmanouil Pitsidianakis
` (15 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:47 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block; +Cc: Emmanouil Pitsidianakis, Laurent Vivier
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
linux-user/mips/cpu_loop.c | 8 ++++----
linux-user/mmap.c | 2 +-
linux-user/syscall.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 8735e58bad..38ddcadfc6 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -63,68 +63,68 @@ static void do_tr_or_bp(CPUMIPSState *env, unsigned int code, bool trap)
void cpu_loop(CPUMIPSState *env)
{
CPUState *cs = env_cpu(env);
int trapnr, si_code;
unsigned int code;
abi_long ret;
# ifdef TARGET_ABI_MIPSO32
unsigned int syscall_num;
# endif
for(;;) {
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
process_queued_cpu_work(cs);
switch(trapnr) {
case EXCP_SYSCALL:
env->active_tc.PC += 4;
# ifdef TARGET_ABI_MIPSO32
syscall_num = env->active_tc.gpr[2] - 4000;
if (syscall_num >= sizeof(mips_syscall_args)) {
/* syscall_num is larger that any defined for MIPS O32 */
ret = -TARGET_ENOSYS;
} else if (mips_syscall_args[syscall_num] ==
MIPS_SYSCALL_NUMBER_UNUSED) {
/* syscall_num belongs to the range not defined for MIPS O32 */
ret = -TARGET_ENOSYS;
} else {
/* syscall_num is valid */
int nb_args;
abi_ulong sp_reg;
abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
nb_args = mips_syscall_args[syscall_num];
sp_reg = env->active_tc.gpr[29];
switch (nb_args) {
/* these arguments are taken from the stack */
case 8:
if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
goto done_syscall;
}
- /* fall through */
+ fallthrough;
case 7:
if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
goto done_syscall;
}
- /* fall through */
+ fallthrough;
case 6:
if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
goto done_syscall;
}
- /* fall through */
+ fallthrough;
case 5:
if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
goto done_syscall;
}
- /* fall through */
+ fallthrough;
default:
break;
}
ret = do_syscall(env, env->active_tc.gpr[2],
env->active_tc.gpr[4],
env->active_tc.gpr[5],
env->active_tc.gpr[6],
env->active_tc.gpr[7],
arg5, arg6, arg7, arg8);
}
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
index 8ccaab7859..ff33b4ccf6 100644
--- a/linux-user/mmap.c
+++ b/linux-user/mmap.c
@@ -960,84 +960,84 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size,
abi_long target_madvise(abi_ulong start, abi_ulong len_in, int advice)
{
abi_ulong len;
int ret = 0;
if (start & ~TARGET_PAGE_MASK) {
return -TARGET_EINVAL;
}
if (len_in == 0) {
return 0;
}
len = TARGET_PAGE_ALIGN(len_in);
if (len == 0 || !guest_range_valid_untagged(start, len)) {
return -TARGET_EINVAL;
}
/* Translate for some architectures which have different MADV_xxx values */
switch (advice) {
case TARGET_MADV_DONTNEED: /* alpha */
advice = MADV_DONTNEED;
break;
case TARGET_MADV_WIPEONFORK: /* parisc */
advice = MADV_WIPEONFORK;
break;
case TARGET_MADV_KEEPONFORK: /* parisc */
advice = MADV_KEEPONFORK;
break;
/* we do not care about the other MADV_xxx values yet */
}
/*
* Most advice values are hints, so ignoring and returning success is ok.
*
* However, some advice values such as MADV_DONTNEED, MADV_WIPEONFORK and
* MADV_KEEPONFORK are not hints and need to be emulated.
*
* A straight passthrough for those may not be safe because qemu sometimes
* turns private file-backed mappings into anonymous mappings.
* If all guest pages have PAGE_PASSTHROUGH set, mappings have the
* same semantics for the host as for the guest.
*
* We pass through MADV_WIPEONFORK and MADV_KEEPONFORK if possible and
* return failure if not.
*
* MADV_DONTNEED is passed through as well, if possible.
* If passthrough isn't possible, we nevertheless (wrongly!) return
* success, which is broken but some userspace programs fail to work
* otherwise. Completely implementing such emulation is quite complicated
* though.
*/
mmap_lock();
switch (advice) {
case MADV_WIPEONFORK:
case MADV_KEEPONFORK:
ret = -EINVAL;
- /* fall through */
+ fallthrough;
case MADV_DONTNEED:
if (page_check_range(start, len, PAGE_PASSTHROUGH)) {
ret = get_errno(madvise(g2h_untagged(start), len, advice));
if ((advice == MADV_DONTNEED) && (ret == 0)) {
page_reset_target_data(start, start + len - 1);
}
}
}
mmap_unlock();
return ret;
}
#ifndef TARGET_FORCE_SHMLBA
/*
* For most architectures, SHMLBA is the same as the page size;
* some architectures have larger values, in which case they should
* define TARGET_FORCE_SHMLBA and provide a target_shmlba() function.
* This corresponds to the kernel arch code defining __ARCH_FORCE_SHMLBA
* and defining its own value for SHMLBA.
*
* The kernel also permits SHMLBA to be set by the architecture to a
* value larger than the page size without setting __ARCH_FORCE_SHMLBA;
* this means that addresses are rounded to the large size if
* SHM_RND is set but addresses not aligned to that size are not rejected
* as long as they are at least page-aligned. Since the only architecture
* which uses this is ia64 this code doesn't provide for that oddity.
*/
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index d49cd314a2..d15817846c 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -7740,74 +7740,74 @@ static int do_safe_futex(int *uaddr, int op, int val,
/* ??? Using host futex calls even when target atomic operations
are not really atomic probably breaks things. However implementing
futexes locally would make futexes shared between multiple processes
tricky. However they're probably useless because guest atomic
operations won't work either. */
#if defined(TARGET_NR_futex) || defined(TARGET_NR_futex_time64)
static int do_futex(CPUState *cpu, bool time64, target_ulong uaddr,
int op, int val, target_ulong timeout,
target_ulong uaddr2, int val3)
{
struct timespec ts, *pts = NULL;
void *haddr2 = NULL;
int base_op;
/* We assume FUTEX_* constants are the same on both host and target. */
#ifdef FUTEX_CMD_MASK
base_op = op & FUTEX_CMD_MASK;
#else
base_op = op;
#endif
switch (base_op) {
case FUTEX_WAIT:
case FUTEX_WAIT_BITSET:
val = tswap32(val);
break;
case FUTEX_WAIT_REQUEUE_PI:
val = tswap32(val);
haddr2 = g2h(cpu, uaddr2);
break;
case FUTEX_LOCK_PI:
case FUTEX_LOCK_PI2:
break;
case FUTEX_WAKE:
case FUTEX_WAKE_BITSET:
case FUTEX_TRYLOCK_PI:
case FUTEX_UNLOCK_PI:
timeout = 0;
break;
case FUTEX_FD:
val = target_to_host_signal(val);
timeout = 0;
break;
case FUTEX_CMP_REQUEUE:
case FUTEX_CMP_REQUEUE_PI:
val3 = tswap32(val3);
- /* fall through */
+ fallthrough;
case FUTEX_REQUEUE:
case FUTEX_WAKE_OP:
/*
* For these, the 4th argument is not TIMEOUT, but VAL2.
* But the prototype of do_safe_futex takes a pointer, so
* insert casts to satisfy the compiler. We do not need
* to tswap VAL2 since it's not compared to guest memory.
*/
pts = (struct timespec *)(uintptr_t)timeout;
timeout = 0;
haddr2 = g2h(cpu, uaddr2);
break;
default:
return -TARGET_ENOSYS;
}
if (timeout) {
pts = &ts;
if (time64
? target_to_host_timespec64(pts, timeout)
: target_to_host_timespec(pts, timeout)) {
return -TARGET_EFAULT;
}
}
return do_safe_futex(g2h(cpu, uaddr), op, val, pts, haddr2, val3);
}
#endif
#if defined(TARGET_NR_name_to_handle_at) && defined(CONFIG_OPEN_BY_HANDLE)
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 41/75] hw/i386: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (3 preceding siblings ...)
2023-10-13 7:47 ` [RFC PATCH 40/75] linux-user: " Emmanouil Pitsidianakis
@ 2023-10-13 7:47 ` Emmanouil Pitsidianakis
2023-10-13 7:47 ` [RFC PATCH 42/75] hw/misc: " Emmanouil Pitsidianakis
` (14 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:47 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block
Cc: Emmanouil Pitsidianakis, Michael S. Tsirkin, Peter Xu, Jason Wang,
Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, David Woodhouse, Paul Durrant
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/i386/intel_iommu.c | 4 ++--
hw/i386/kvm/xen_evtchn.c | 2 +-
hw/i386/x86.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 2c832ab68b..bdb2ea3ac5 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2100,29 +2100,29 @@ static void vtd_context_device_invalidate(IntelIOMMUState *s,
/* Context-cache invalidation
* Returns the Context Actual Invalidation Granularity.
* @val: the content of the CCMD_REG
*/
static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val)
{
uint64_t caig;
uint64_t type = val & VTD_CCMD_CIRG_MASK;
switch (type) {
case VTD_CCMD_DOMAIN_INVL:
- /* Fall through */
+ fallthrough;
case VTD_CCMD_GLOBAL_INVL:
caig = VTD_CCMD_GLOBAL_INVL_A;
vtd_context_global_invalidate(s);
break;
case VTD_CCMD_DEVICE_INVL:
caig = VTD_CCMD_DEVICE_INVL_A;
vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val));
break;
default:
error_report_once("%s: invalid context: 0x%" PRIx64,
__func__, val);
caig = 0;
}
return caig;
}
@@ -2513,34 +2513,34 @@ static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
static bool vtd_process_context_cache_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
uint16_t sid, fmask;
if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) {
error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64
" (reserved nonzero)", __func__, inv_desc->hi,
inv_desc->lo);
return false;
}
switch (inv_desc->lo & VTD_INV_DESC_CC_G) {
case VTD_INV_DESC_CC_DOMAIN:
trace_vtd_inv_desc_cc_domain(
(uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo));
- /* Fall through */
+ fallthrough;
case VTD_INV_DESC_CC_GLOBAL:
vtd_context_global_invalidate(s);
break;
case VTD_INV_DESC_CC_DEVICE:
sid = VTD_INV_DESC_CC_SID(inv_desc->lo);
fmask = VTD_INV_DESC_CC_FM(inv_desc->lo);
vtd_context_device_invalidate(s, sid, fmask);
break;
default:
error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64
" (invalid type)", __func__, inv_desc->hi,
inv_desc->lo);
return false;
}
return true;
}
diff --git a/hw/i386/kvm/xen_evtchn.c b/hw/i386/kvm/xen_evtchn.c
index a731738411..d15e324f6e 100644
--- a/hw/i386/kvm/xen_evtchn.c
+++ b/hw/i386/kvm/xen_evtchn.c
@@ -2028,71 +2028,71 @@ static int find_be_port(XenEvtchnState *s, struct xenevtchn_handle *xc)
int xen_be_evtchn_bind_interdomain(struct xenevtchn_handle *xc, uint32_t domid,
evtchn_port_t guest_port)
{
XenEvtchnState *s = xen_evtchn_singleton;
XenEvtchnPort *gp;
uint16_t be_port = 0;
int ret;
if (!s) {
return -ENOTSUP;
}
if (!xc) {
return -EFAULT;
}
if (domid != xen_domid) {
return -ESRCH;
}
if (!valid_port(guest_port)) {
return -EINVAL;
}
qemu_mutex_lock(&s->port_lock);
/* The guest has to have an unbound port waiting for us to bind */
gp = &s->port_table[guest_port];
switch (gp->type) {
case EVTCHNSTAT_interdomain:
/* Allow rebinding after migration, preserve port # if possible */
be_port = gp->type_val & ~PORT_INFO_TYPEVAL_REMOTE_QEMU;
assert(be_port != 0);
if (!s->be_handles[be_port]) {
s->be_handles[be_port] = xc;
xc->guest_port = guest_port;
ret = xc->be_port = be_port;
if (kvm_xen_has_cap(EVTCHN_SEND)) {
assign_kernel_eventfd(gp->type, guest_port, xc->fd);
}
break;
}
- /* fall through */
+ fallthrough;
case EVTCHNSTAT_unbound:
be_port = find_be_port(s, xc);
if (!be_port) {
ret = -ENOSPC;
goto out;
}
gp->type = EVTCHNSTAT_interdomain;
gp->type_val = be_port | PORT_INFO_TYPEVAL_REMOTE_QEMU;
xc->guest_port = guest_port;
if (kvm_xen_has_cap(EVTCHN_SEND)) {
assign_kernel_eventfd(gp->type, guest_port, xc->fd);
}
ret = be_port;
break;
default:
ret = -EINVAL;
break;
}
out:
qemu_mutex_unlock(&s->port_lock);
return ret;
}
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index b3d054889b..c1fd0a966a 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -597,32 +597,32 @@ DeviceState *cpu_get_current_apic(void)
void gsi_handler(void *opaque, int n, int level)
{
GSIState *s = opaque;
trace_x86_gsi_interrupt(n, level);
switch (n) {
case 0 ... ISA_NUM_IRQS - 1:
if (s->i8259_irq[n]) {
/* Under KVM, Kernel will forward to both PIC and IOAPIC */
qemu_set_irq(s->i8259_irq[n], level);
}
- /* fall through */
+ fallthrough;
case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1:
#ifdef CONFIG_XEN_EMU
/*
* Xen delivers the GSI to the Legacy PIC (not that Legacy PIC
* routing actually works properly under Xen). And then to
* *either* the PIRQ handling or the I/OAPIC depending on
* whether the former wants it.
*/
if (xen_mode == XEN_EMULATE && xen_evtchn_set_gsi(n, level)) {
break;
}
#endif
qemu_set_irq(s->ioapic_irq[n], level);
break;
case IO_APIC_SECONDARY_IRQBASE
... IO_APIC_SECONDARY_IRQBASE + IOAPIC_NUM_PINS - 1:
qemu_set_irq(s->ioapic2_irq[n - IO_APIC_SECONDARY_IRQBASE], level);
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 42/75] hw/misc: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (4 preceding siblings ...)
2023-10-13 7:47 ` [RFC PATCH 41/75] hw/i386: " Emmanouil Pitsidianakis
@ 2023-10-13 7:47 ` Emmanouil Pitsidianakis
2023-10-13 8:11 ` Cédric Le Goater
2023-10-13 7:47 ` [RFC PATCH 43/75] hw/m68k/mcf_intc.c: " Emmanouil Pitsidianakis
` (13 subsequent siblings)
19 siblings, 1 reply; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:47 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block
Cc: Emmanouil Pitsidianakis, Peter Maydell, Cédric Le Goater,
Andrew Jeffery, Joel Stanley, Philippe Mathieu-Daudé,
Mark Cave-Ayland, open list:New World (mac99)
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/misc/a9scu.c | 2 ++
hw/misc/aspeed_scu.c | 2 +-
hw/misc/bcm2835_property.c | 12 ++++++------
hw/misc/mos6522.c | 4 ++--
4 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
index a375ebc987..b422bec3c4 100644
--- a/hw/misc/a9scu.c
+++ b/hw/misc/a9scu.c
@@ -21,26 +21,27 @@
static uint64_t a9_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
A9SCUState *s = (A9SCUState *)opaque;
switch (offset) {
case 0x00: /* Control */
return s->control;
case 0x04: /* Configuration */
return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
case 0x08: /* CPU Power Status */
return s->status;
case 0x0c: /* Invalidate All Registers In Secure State */
return 0;
case 0x40: /* Filtering Start Address Register */
case 0x44: /* Filtering End Address Register */
/* RAZ/WI, like an implementation with only one AXI master */
return 0;
case 0x50: /* SCU Access Control Register */
case 0x54: /* SCU Non-secure Access Control Register */
/* unimplemented, fall through */
+ fallthrough;
default:
qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx"\n",
__func__, offset);
return 0;
}
}
@@ -48,31 +49,32 @@ static uint64_t a9_scu_read(void *opaque, hwaddr offset,
static void a9_scu_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
A9SCUState *s = (A9SCUState *)opaque;
switch (offset) {
case 0x00: /* Control */
s->control = value & 1;
break;
case 0x4: /* Configuration: RO */
break;
case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
s->status = value;
break;
case 0x0c: /* Invalidate All Registers In Secure State */
/* no-op as we do not implement caches */
break;
case 0x40: /* Filtering Start Address Register */
case 0x44: /* Filtering End Address Register */
/* RAZ/WI, like an implementation with only one AXI master */
break;
case 0x50: /* SCU Access Control Register */
case 0x54: /* SCU Non-secure Access Control Register */
/* unimplemented, fall through */
+ fallthrough;
default:
qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx
" value 0x%"PRIx64"\n",
__func__, offset, value);
break;
}
}
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 8335364906..4a1ea2fa21 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -645,65 +645,65 @@ static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset,
static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset,
uint64_t data64, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
int reg = TO_REG(offset);
/* Truncate here so bitwise operations below behave as expected */
uint32_t data = data64;
if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
return;
}
if (reg > PROT_KEY && !s->regs[PROT_KEY]) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
}
trace_aspeed_scu_write(offset, size, data);
switch (reg) {
case AST2600_PROT_KEY:
s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
return;
case AST2600_HW_STRAP1:
case AST2600_HW_STRAP2:
if (s->regs[reg + 2]) {
return;
}
- /* fall through */
+ fallthrough;
case AST2600_SYS_RST_CTRL:
case AST2600_SYS_RST_CTRL2:
case AST2600_CLK_STOP_CTRL:
case AST2600_CLK_STOP_CTRL2:
/* W1S (Write 1 to set) registers */
s->regs[reg] |= data;
return;
case AST2600_SYS_RST_CTRL_CLR:
case AST2600_SYS_RST_CTRL2_CLR:
case AST2600_CLK_STOP_CTRL_CLR:
case AST2600_CLK_STOP_CTRL2_CLR:
case AST2600_HW_STRAP1_CLR:
case AST2600_HW_STRAP2_CLR:
/*
* W1C (Write 1 to clear) registers are offset by one address from
* the data register
*/
s->regs[reg - 1] &= ~data;
return;
case AST2600_RNG_DATA:
case AST2600_SILICON_REV:
case AST2600_SILICON_REV2:
case AST2600_CHIP_ID0:
case AST2600_CHIP_ID1:
/* Add read only registers here */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
return;
}
s->regs[reg] = data;
}
diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c
index 4ed9faa54a..98170f34a6 100644
--- a/hw/misc/bcm2835_property.c
+++ b/hw/misc/bcm2835_property.c
@@ -24,303 +24,303 @@
static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value)
{
uint32_t tag;
uint32_t bufsize;
uint32_t tot_len;
size_t resplen;
uint32_t tmp;
int n;
uint32_t offset, length, color;
/*
* Copy the current state of the framebuffer config; we will update
* this copy as we process tags and then ask the framebuffer to use
* it at the end.
*/
BCM2835FBConfig fbconfig = s->fbdev->config;
bool fbconfig_updated = false;
value &= ~0xf;
s->addr = value;
tot_len = ldl_le_phys(&s->dma_as, value);
/* @(addr + 4) : Buffer response code */
value = s->addr + 8;
while (value + 8 <= s->addr + tot_len) {
tag = ldl_le_phys(&s->dma_as, value);
bufsize = ldl_le_phys(&s->dma_as, value + 4);
/* @(value + 8) : Request/response indicator */
resplen = 0;
switch (tag) {
case RPI_FWREQ_PROPERTY_END:
break;
case RPI_FWREQ_GET_FIRMWARE_REVISION:
stl_le_phys(&s->dma_as, value + 12, 346337);
resplen = 4;
break;
case RPI_FWREQ_GET_BOARD_MODEL:
qemu_log_mask(LOG_UNIMP,
"bcm2835_property: 0x%08x get board model NYI\n",
tag);
resplen = 4;
break;
case RPI_FWREQ_GET_BOARD_REVISION:
stl_le_phys(&s->dma_as, value + 12, s->board_rev);
resplen = 4;
break;
case RPI_FWREQ_GET_BOARD_MAC_ADDRESS:
resplen = sizeof(s->macaddr.a);
dma_memory_write(&s->dma_as, value + 12, s->macaddr.a, resplen,
MEMTXATTRS_UNSPECIFIED);
break;
case RPI_FWREQ_GET_BOARD_SERIAL:
qemu_log_mask(LOG_UNIMP,
"bcm2835_property: 0x%08x get board serial NYI\n",
tag);
resplen = 8;
break;
case RPI_FWREQ_GET_ARM_MEMORY:
/* base */
stl_le_phys(&s->dma_as, value + 12, 0);
/* size */
stl_le_phys(&s->dma_as, value + 16, s->fbdev->vcram_base);
resplen = 8;
break;
case RPI_FWREQ_GET_VC_MEMORY:
/* base */
stl_le_phys(&s->dma_as, value + 12, s->fbdev->vcram_base);
/* size */
stl_le_phys(&s->dma_as, value + 16, s->fbdev->vcram_size);
resplen = 8;
break;
case RPI_FWREQ_SET_POWER_STATE:
/* Assume that whatever device they asked for exists,
* and we'll just claim we set it to the desired state
*/
tmp = ldl_le_phys(&s->dma_as, value + 16);
stl_le_phys(&s->dma_as, value + 16, (tmp & 1));
resplen = 8;
break;
/* Clocks */
case RPI_FWREQ_GET_CLOCK_STATE:
stl_le_phys(&s->dma_as, value + 16, 0x1);
resplen = 8;
break;
case RPI_FWREQ_SET_CLOCK_STATE:
qemu_log_mask(LOG_UNIMP,
"bcm2835_property: 0x%08x set clock state NYI\n",
tag);
resplen = 8;
break;
case RPI_FWREQ_GET_CLOCK_RATE:
case RPI_FWREQ_GET_MAX_CLOCK_RATE:
case RPI_FWREQ_GET_MIN_CLOCK_RATE:
switch (ldl_le_phys(&s->dma_as, value + 12)) {
case RPI_FIRMWARE_EMMC_CLK_ID:
stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_EMMC_CLK_RATE);
break;
case RPI_FIRMWARE_UART_CLK_ID:
stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_UART_CLK_RATE);
break;
case RPI_FIRMWARE_CORE_CLK_ID:
stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_CORE_CLK_RATE);
break;
default:
stl_le_phys(&s->dma_as, value + 16,
RPI_FIRMWARE_DEFAULT_CLK_RATE);
break;
}
resplen = 8;
break;
case RPI_FWREQ_SET_CLOCK_RATE:
case RPI_FWREQ_SET_MAX_CLOCK_RATE:
case RPI_FWREQ_SET_MIN_CLOCK_RATE:
qemu_log_mask(LOG_UNIMP,
"bcm2835_property: 0x%08x set clock rate NYI\n",
tag);
resplen = 8;
break;
/* Temperature */
case RPI_FWREQ_GET_TEMPERATURE:
stl_le_phys(&s->dma_as, value + 16, 25000);
resplen = 8;
break;
case RPI_FWREQ_GET_MAX_TEMPERATURE:
stl_le_phys(&s->dma_as, value + 16, 99000);
resplen = 8;
break;
/* Frame buffer */
case RPI_FWREQ_FRAMEBUFFER_ALLOCATE:
stl_le_phys(&s->dma_as, value + 12, fbconfig.base);
stl_le_phys(&s->dma_as, value + 16,
bcm2835_fb_get_size(&fbconfig));
resplen = 8;
break;
case RPI_FWREQ_FRAMEBUFFER_RELEASE:
resplen = 0;
break;
case RPI_FWREQ_FRAMEBUFFER_BLANK:
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT:
case RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT:
resplen = 8;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT:
fbconfig.xres = ldl_le_phys(&s->dma_as, value + 12);
fbconfig.yres = ldl_le_phys(&s->dma_as, value + 16);
bcm2835_fb_validate_config(&fbconfig);
fbconfig_updated = true;
- /* fall through */
+ fallthrough;
case RPI_FWREQ_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT:
stl_le_phys(&s->dma_as, value + 12, fbconfig.xres);
stl_le_phys(&s->dma_as, value + 16, fbconfig.yres);
resplen = 8;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT:
fbconfig.xres_virtual = ldl_le_phys(&s->dma_as, value + 12);
fbconfig.yres_virtual = ldl_le_phys(&s->dma_as, value + 16);
bcm2835_fb_validate_config(&fbconfig);
fbconfig_updated = true;
- /* fall through */
+ fallthrough;
case RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT:
stl_le_phys(&s->dma_as, value + 12, fbconfig.xres_virtual);
stl_le_phys(&s->dma_as, value + 16, fbconfig.yres_virtual);
resplen = 8;
break;
case RPI_FWREQ_FRAMEBUFFER_TEST_DEPTH:
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_DEPTH:
fbconfig.bpp = ldl_le_phys(&s->dma_as, value + 12);
bcm2835_fb_validate_config(&fbconfig);
fbconfig_updated = true;
- /* fall through */
+ fallthrough;
case RPI_FWREQ_FRAMEBUFFER_GET_DEPTH:
stl_le_phys(&s->dma_as, value + 12, fbconfig.bpp);
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_TEST_PIXEL_ORDER:
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_PIXEL_ORDER:
fbconfig.pixo = ldl_le_phys(&s->dma_as, value + 12);
bcm2835_fb_validate_config(&fbconfig);
fbconfig_updated = true;
- /* fall through */
+ fallthrough;
case RPI_FWREQ_FRAMEBUFFER_GET_PIXEL_ORDER:
stl_le_phys(&s->dma_as, value + 12, fbconfig.pixo);
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_TEST_ALPHA_MODE:
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_ALPHA_MODE:
fbconfig.alpha = ldl_le_phys(&s->dma_as, value + 12);
bcm2835_fb_validate_config(&fbconfig);
fbconfig_updated = true;
- /* fall through */
+ fallthrough;
case RPI_FWREQ_FRAMEBUFFER_GET_ALPHA_MODE:
stl_le_phys(&s->dma_as, value + 12, fbconfig.alpha);
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_GET_PITCH:
stl_le_phys(&s->dma_as, value + 12,
bcm2835_fb_get_pitch(&fbconfig));
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_OFFSET:
resplen = 8;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_OFFSET:
fbconfig.xoffset = ldl_le_phys(&s->dma_as, value + 12);
fbconfig.yoffset = ldl_le_phys(&s->dma_as, value + 16);
bcm2835_fb_validate_config(&fbconfig);
fbconfig_updated = true;
- /* fall through */
+ fallthrough;
case RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_OFFSET:
stl_le_phys(&s->dma_as, value + 12, fbconfig.xoffset);
stl_le_phys(&s->dma_as, value + 16, fbconfig.yoffset);
resplen = 8;
break;
case RPI_FWREQ_FRAMEBUFFER_GET_OVERSCAN:
case RPI_FWREQ_FRAMEBUFFER_TEST_OVERSCAN:
case RPI_FWREQ_FRAMEBUFFER_SET_OVERSCAN:
stl_le_phys(&s->dma_as, value + 12, 0);
stl_le_phys(&s->dma_as, value + 16, 0);
stl_le_phys(&s->dma_as, value + 20, 0);
stl_le_phys(&s->dma_as, value + 24, 0);
resplen = 16;
break;
case RPI_FWREQ_FRAMEBUFFER_SET_PALETTE:
offset = ldl_le_phys(&s->dma_as, value + 12);
length = ldl_le_phys(&s->dma_as, value + 16);
n = 0;
while (n < length - offset) {
color = ldl_le_phys(&s->dma_as, value + 20 + (n << 2));
stl_le_phys(&s->dma_as,
s->fbdev->vcram_base + ((offset + n) << 2), color);
n++;
}
stl_le_phys(&s->dma_as, value + 12, 0);
resplen = 4;
break;
case RPI_FWREQ_FRAMEBUFFER_GET_NUM_DISPLAYS:
stl_le_phys(&s->dma_as, value + 12, 1);
resplen = 4;
break;
case RPI_FWREQ_GET_DMA_CHANNELS:
/* channels 2-5 */
stl_le_phys(&s->dma_as, value + 12, 0x003C);
resplen = 4;
break;
case RPI_FWREQ_GET_COMMAND_LINE:
/*
* We follow the firmware behaviour: no NUL terminator is
* written to the buffer, and if the buffer is too short
* we report the required length in the response header
* and copy nothing to the buffer.
*/
resplen = strlen(s->command_line);
if (bufsize >= resplen)
address_space_write(&s->dma_as, value + 12,
MEMTXATTRS_UNSPECIFIED, s->command_line,
resplen);
break;
default:
qemu_log_mask(LOG_UNIMP,
"bcm2835_property: unhandled tag 0x%08x\n", tag);
break;
}
trace_bcm2835_mbox_property(tag, bufsize, resplen);
if (tag == 0) {
break;
}
stl_le_phys(&s->dma_as, value + 8, (1 << 31) | resplen);
value += bufsize + 12;
}
/* Reconfigure framebuffer if required */
if (fbconfig_updated) {
bcm2835_fb_reconfigure(s->fbdev, &fbconfig);
}
/* Buffer response code */
stl_le_phys(&s->dma_as, s->addr + 4, (1 << 31));
}
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index d6ba47bde9..a62349e6a0 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -296,97 +296,97 @@ static void mos6522_portB_write(MOS6522State *s)
uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
{
MOS6522State *s = opaque;
uint32_t val;
int ctrl;
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (now >= s->timers[0].next_irq_time) {
mos6522_timer1_update(s, &s->timers[0], now);
s->ifr |= T1_INT;
}
if (now >= s->timers[1].next_irq_time) {
mos6522_timer2_update(s, &s->timers[1], now);
s->ifr |= T2_INT;
}
switch (addr) {
case VIA_REG_B:
val = s->b;
ctrl = (s->pcr & CB2_CTRL_MASK) >> CB2_CTRL_SHIFT;
if (!(ctrl & C2_IND)) {
s->ifr &= ~CB2_INT;
}
s->ifr &= ~CB1_INT;
mos6522_update_irq(s);
break;
case VIA_REG_A:
qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake");
- /* fall through */
+ fallthrough;
case VIA_REG_ANH:
val = s->a;
ctrl = (s->pcr & CA2_CTRL_MASK) >> CA2_CTRL_SHIFT;
if (!(ctrl & C2_IND)) {
s->ifr &= ~CA2_INT;
}
s->ifr &= ~CA1_INT;
mos6522_update_irq(s);
break;
case VIA_REG_DIRB:
val = s->dirb;
break;
case VIA_REG_DIRA:
val = s->dira;
break;
case VIA_REG_T1CL:
val = get_counter(s, &s->timers[0]) & 0xff;
s->ifr &= ~T1_INT;
mos6522_update_irq(s);
break;
case VIA_REG_T1CH:
val = get_counter(s, &s->timers[0]) >> 8;
mos6522_update_irq(s);
break;
case VIA_REG_T1LL:
val = s->timers[0].latch & 0xff;
break;
case VIA_REG_T1LH:
/* XXX: check this */
val = (s->timers[0].latch >> 8) & 0xff;
break;
case VIA_REG_T2CL:
val = get_counter(s, &s->timers[1]) & 0xff;
s->ifr &= ~T2_INT;
mos6522_update_irq(s);
break;
case VIA_REG_T2CH:
val = get_counter(s, &s->timers[1]) >> 8;
break;
case VIA_REG_SR:
val = s->sr;
s->ifr &= ~SR_INT;
mos6522_update_irq(s);
break;
case VIA_REG_ACR:
val = s->acr;
break;
case VIA_REG_PCR:
val = s->pcr;
break;
case VIA_REG_IFR:
val = s->ifr;
if (s->ifr & s->ier) {
val |= 0x80;
}
break;
case VIA_REG_IER:
val = s->ier | 0x80;
break;
default:
g_assert_not_reached();
}
if (addr != VIA_REG_IFR || val != 0) {
trace_mos6522_read(addr, mos6522_reg_names[addr], val);
}
return val;
}
@@ -394,105 +394,105 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
{
MOS6522State *s = opaque;
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s);
int ctrl;
trace_mos6522_write(addr, mos6522_reg_names[addr], val);
switch (addr) {
case VIA_REG_B:
s->b = (s->b & ~s->dirb) | (val & s->dirb);
mdc->portB_write(s);
ctrl = (s->pcr & CB2_CTRL_MASK) >> CB2_CTRL_SHIFT;
if (!(ctrl & C2_IND)) {
s->ifr &= ~CB2_INT;
}
s->ifr &= ~CB1_INT;
mos6522_update_irq(s);
break;
case VIA_REG_A:
qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake");
- /* fall through */
+ fallthrough;
case VIA_REG_ANH:
s->a = (s->a & ~s->dira) | (val & s->dira);
mdc->portA_write(s);
ctrl = (s->pcr & CA2_CTRL_MASK) >> CA2_CTRL_SHIFT;
if (!(ctrl & C2_IND)) {
s->ifr &= ~CA2_INT;
}
s->ifr &= ~CA1_INT;
mos6522_update_irq(s);
break;
case VIA_REG_DIRB:
s->dirb = val;
break;
case VIA_REG_DIRA:
s->dira = val;
break;
case VIA_REG_T1CL:
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
mos6522_timer1_update(s, &s->timers[0],
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
case VIA_REG_T1CH:
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
s->ifr &= ~T1_INT;
set_counter(s, &s->timers[0], s->timers[0].latch);
break;
case VIA_REG_T1LL:
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
mos6522_timer1_update(s, &s->timers[0],
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
case VIA_REG_T1LH:
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
s->ifr &= ~T1_INT;
mos6522_timer1_update(s, &s->timers[0],
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
case VIA_REG_T2CL:
s->timers[1].latch = (s->timers[1].latch & 0xff00) | val;
break;
case VIA_REG_T2CH:
/* To ensure T2 generates an interrupt on zero crossing with the
common timer code, write the value directly from the latch to
the counter */
s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8);
s->ifr &= ~T2_INT;
set_counter(s, &s->timers[1], s->timers[1].latch);
break;
case VIA_REG_SR:
s->sr = val;
break;
case VIA_REG_ACR:
s->acr = val;
mos6522_timer1_update(s, &s->timers[0],
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
case VIA_REG_PCR:
s->pcr = val;
break;
case VIA_REG_IFR:
/* reset bits */
s->ifr &= ~val;
mos6522_update_irq(s);
break;
case VIA_REG_IER:
if (val & IER_SET) {
/* set bits */
s->ier |= val & 0x7f;
} else {
/* reset bits */
s->ier &= ~val;
}
mos6522_update_irq(s);
/* if IER is modified starts needed timers */
mos6522_timer1_update(s, &s->timers[0],
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
mos6522_timer2_update(s, &s->timers[1],
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
default:
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [RFC PATCH 42/75] hw/misc: add fallthrough pseudo-keyword
2023-10-13 7:47 ` [RFC PATCH 42/75] hw/misc: " Emmanouil Pitsidianakis
@ 2023-10-13 8:11 ` Cédric Le Goater
0 siblings, 0 replies; 22+ messages in thread
From: Cédric Le Goater @ 2023-10-13 8:11 UTC (permalink / raw)
To: Emmanouil Pitsidianakis, qemu-devel, qemu-arm, qemu-block
Cc: Peter Maydell, Andrew Jeffery, Joel Stanley,
Philippe Mathieu-Daudé, Mark Cave-Ayland,
open list:New World (mac99)
On 10/13/23 09:47, Emmanouil Pitsidianakis wrote:
> Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
> ---
> hw/misc/a9scu.c | 2 ++
> hw/misc/aspeed_scu.c | 2 +-
> hw/misc/bcm2835_property.c | 12 ++++++------
> hw/misc/mos6522.c | 4 ++--
> 4 files changed, 11 insertions(+), 9 deletions(-)
For aspeed,
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
>
> diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
> index a375ebc987..b422bec3c4 100644
> --- a/hw/misc/a9scu.c
> +++ b/hw/misc/a9scu.c
> @@ -21,26 +21,27 @@
> static uint64_t a9_scu_read(void *opaque, hwaddr offset,
> unsigned size)
> {
> A9SCUState *s = (A9SCUState *)opaque;
> switch (offset) {
> case 0x00: /* Control */
> return s->control;
> case 0x04: /* Configuration */
> return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
> case 0x08: /* CPU Power Status */
> return s->status;
> case 0x0c: /* Invalidate All Registers In Secure State */
> return 0;
> case 0x40: /* Filtering Start Address Register */
> case 0x44: /* Filtering End Address Register */
> /* RAZ/WI, like an implementation with only one AXI master */
> return 0;
> case 0x50: /* SCU Access Control Register */
> case 0x54: /* SCU Non-secure Access Control Register */
> /* unimplemented, fall through */
> + fallthrough;
> default:
> qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx"\n",
> __func__, offset);
> return 0;
> }
> }
> @@ -48,31 +49,32 @@ static uint64_t a9_scu_read(void *opaque, hwaddr offset,
> static void a9_scu_write(void *opaque, hwaddr offset,
> uint64_t value, unsigned size)
> {
> A9SCUState *s = (A9SCUState *)opaque;
>
> switch (offset) {
> case 0x00: /* Control */
> s->control = value & 1;
> break;
> case 0x4: /* Configuration: RO */
> break;
> case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
> s->status = value;
> break;
> case 0x0c: /* Invalidate All Registers In Secure State */
> /* no-op as we do not implement caches */
> break;
> case 0x40: /* Filtering Start Address Register */
> case 0x44: /* Filtering End Address Register */
> /* RAZ/WI, like an implementation with only one AXI master */
> break;
> case 0x50: /* SCU Access Control Register */
> case 0x54: /* SCU Non-secure Access Control Register */
> /* unimplemented, fall through */
> + fallthrough;
> default:
> qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx
> " value 0x%"PRIx64"\n",
> __func__, offset, value);
> break;
> }
> }
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> index 8335364906..4a1ea2fa21 100644
> --- a/hw/misc/aspeed_scu.c
> +++ b/hw/misc/aspeed_scu.c
> @@ -645,65 +645,65 @@ static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset,
> static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset,
> uint64_t data64, unsigned size)
> {
> AspeedSCUState *s = ASPEED_SCU(opaque);
> int reg = TO_REG(offset);
> /* Truncate here so bitwise operations below behave as expected */
> uint32_t data = data64;
>
> if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
> qemu_log_mask(LOG_GUEST_ERROR,
> "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
> __func__, offset);
> return;
> }
>
> if (reg > PROT_KEY && !s->regs[PROT_KEY]) {
> qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
> }
>
> trace_aspeed_scu_write(offset, size, data);
>
> switch (reg) {
> case AST2600_PROT_KEY:
> s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
> return;
> case AST2600_HW_STRAP1:
> case AST2600_HW_STRAP2:
> if (s->regs[reg + 2]) {
> return;
> }
> - /* fall through */
> + fallthrough;
> case AST2600_SYS_RST_CTRL:
> case AST2600_SYS_RST_CTRL2:
> case AST2600_CLK_STOP_CTRL:
> case AST2600_CLK_STOP_CTRL2:
> /* W1S (Write 1 to set) registers */
> s->regs[reg] |= data;
> return;
> case AST2600_SYS_RST_CTRL_CLR:
> case AST2600_SYS_RST_CTRL2_CLR:
> case AST2600_CLK_STOP_CTRL_CLR:
> case AST2600_CLK_STOP_CTRL2_CLR:
> case AST2600_HW_STRAP1_CLR:
> case AST2600_HW_STRAP2_CLR:
> /*
> * W1C (Write 1 to clear) registers are offset by one address from
> * the data register
> */
> s->regs[reg - 1] &= ~data;
> return;
>
> case AST2600_RNG_DATA:
> case AST2600_SILICON_REV:
> case AST2600_SILICON_REV2:
> case AST2600_CHIP_ID0:
> case AST2600_CHIP_ID1:
> /* Add read only registers here */
> qemu_log_mask(LOG_GUEST_ERROR,
> "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
> __func__, offset);
> return;
> }
>
> s->regs[reg] = data;
> }
> diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c
> index 4ed9faa54a..98170f34a6 100644
> --- a/hw/misc/bcm2835_property.c
> +++ b/hw/misc/bcm2835_property.c
> @@ -24,303 +24,303 @@
> static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value)
> {
> uint32_t tag;
> uint32_t bufsize;
> uint32_t tot_len;
> size_t resplen;
> uint32_t tmp;
> int n;
> uint32_t offset, length, color;
>
> /*
> * Copy the current state of the framebuffer config; we will update
> * this copy as we process tags and then ask the framebuffer to use
> * it at the end.
> */
> BCM2835FBConfig fbconfig = s->fbdev->config;
> bool fbconfig_updated = false;
>
> value &= ~0xf;
>
> s->addr = value;
>
> tot_len = ldl_le_phys(&s->dma_as, value);
>
> /* @(addr + 4) : Buffer response code */
> value = s->addr + 8;
> while (value + 8 <= s->addr + tot_len) {
> tag = ldl_le_phys(&s->dma_as, value);
> bufsize = ldl_le_phys(&s->dma_as, value + 4);
> /* @(value + 8) : Request/response indicator */
> resplen = 0;
> switch (tag) {
> case RPI_FWREQ_PROPERTY_END:
> break;
> case RPI_FWREQ_GET_FIRMWARE_REVISION:
> stl_le_phys(&s->dma_as, value + 12, 346337);
> resplen = 4;
> break;
> case RPI_FWREQ_GET_BOARD_MODEL:
> qemu_log_mask(LOG_UNIMP,
> "bcm2835_property: 0x%08x get board model NYI\n",
> tag);
> resplen = 4;
> break;
> case RPI_FWREQ_GET_BOARD_REVISION:
> stl_le_phys(&s->dma_as, value + 12, s->board_rev);
> resplen = 4;
> break;
> case RPI_FWREQ_GET_BOARD_MAC_ADDRESS:
> resplen = sizeof(s->macaddr.a);
> dma_memory_write(&s->dma_as, value + 12, s->macaddr.a, resplen,
> MEMTXATTRS_UNSPECIFIED);
> break;
> case RPI_FWREQ_GET_BOARD_SERIAL:
> qemu_log_mask(LOG_UNIMP,
> "bcm2835_property: 0x%08x get board serial NYI\n",
> tag);
> resplen = 8;
> break;
> case RPI_FWREQ_GET_ARM_MEMORY:
> /* base */
> stl_le_phys(&s->dma_as, value + 12, 0);
> /* size */
> stl_le_phys(&s->dma_as, value + 16, s->fbdev->vcram_base);
> resplen = 8;
> break;
> case RPI_FWREQ_GET_VC_MEMORY:
> /* base */
> stl_le_phys(&s->dma_as, value + 12, s->fbdev->vcram_base);
> /* size */
> stl_le_phys(&s->dma_as, value + 16, s->fbdev->vcram_size);
> resplen = 8;
> break;
> case RPI_FWREQ_SET_POWER_STATE:
> /* Assume that whatever device they asked for exists,
> * and we'll just claim we set it to the desired state
> */
> tmp = ldl_le_phys(&s->dma_as, value + 16);
> stl_le_phys(&s->dma_as, value + 16, (tmp & 1));
> resplen = 8;
> break;
>
> /* Clocks */
>
> case RPI_FWREQ_GET_CLOCK_STATE:
> stl_le_phys(&s->dma_as, value + 16, 0x1);
> resplen = 8;
> break;
>
> case RPI_FWREQ_SET_CLOCK_STATE:
> qemu_log_mask(LOG_UNIMP,
> "bcm2835_property: 0x%08x set clock state NYI\n",
> tag);
> resplen = 8;
> break;
>
> case RPI_FWREQ_GET_CLOCK_RATE:
> case RPI_FWREQ_GET_MAX_CLOCK_RATE:
> case RPI_FWREQ_GET_MIN_CLOCK_RATE:
> switch (ldl_le_phys(&s->dma_as, value + 12)) {
> case RPI_FIRMWARE_EMMC_CLK_ID:
> stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_EMMC_CLK_RATE);
> break;
> case RPI_FIRMWARE_UART_CLK_ID:
> stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_UART_CLK_RATE);
> break;
> case RPI_FIRMWARE_CORE_CLK_ID:
> stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_CORE_CLK_RATE);
> break;
> default:
> stl_le_phys(&s->dma_as, value + 16,
> RPI_FIRMWARE_DEFAULT_CLK_RATE);
> break;
> }
> resplen = 8;
> break;
>
> case RPI_FWREQ_SET_CLOCK_RATE:
> case RPI_FWREQ_SET_MAX_CLOCK_RATE:
> case RPI_FWREQ_SET_MIN_CLOCK_RATE:
> qemu_log_mask(LOG_UNIMP,
> "bcm2835_property: 0x%08x set clock rate NYI\n",
> tag);
> resplen = 8;
> break;
>
> /* Temperature */
>
> case RPI_FWREQ_GET_TEMPERATURE:
> stl_le_phys(&s->dma_as, value + 16, 25000);
> resplen = 8;
> break;
>
> case RPI_FWREQ_GET_MAX_TEMPERATURE:
> stl_le_phys(&s->dma_as, value + 16, 99000);
> resplen = 8;
> break;
>
> /* Frame buffer */
>
> case RPI_FWREQ_FRAMEBUFFER_ALLOCATE:
> stl_le_phys(&s->dma_as, value + 12, fbconfig.base);
> stl_le_phys(&s->dma_as, value + 16,
> bcm2835_fb_get_size(&fbconfig));
> resplen = 8;
> break;
> case RPI_FWREQ_FRAMEBUFFER_RELEASE:
> resplen = 0;
> break;
> case RPI_FWREQ_FRAMEBUFFER_BLANK:
> resplen = 4;
> break;
> case RPI_FWREQ_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT:
> case RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT:
> resplen = 8;
> break;
> case RPI_FWREQ_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT:
> fbconfig.xres = ldl_le_phys(&s->dma_as, value + 12);
> fbconfig.yres = ldl_le_phys(&s->dma_as, value + 16);
> bcm2835_fb_validate_config(&fbconfig);
> fbconfig_updated = true;
> - /* fall through */
> + fallthrough;
> case RPI_FWREQ_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT:
> stl_le_phys(&s->dma_as, value + 12, fbconfig.xres);
> stl_le_phys(&s->dma_as, value + 16, fbconfig.yres);
> resplen = 8;
> break;
> case RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT:
> fbconfig.xres_virtual = ldl_le_phys(&s->dma_as, value + 12);
> fbconfig.yres_virtual = ldl_le_phys(&s->dma_as, value + 16);
> bcm2835_fb_validate_config(&fbconfig);
> fbconfig_updated = true;
> - /* fall through */
> + fallthrough;
> case RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT:
> stl_le_phys(&s->dma_as, value + 12, fbconfig.xres_virtual);
> stl_le_phys(&s->dma_as, value + 16, fbconfig.yres_virtual);
> resplen = 8;
> break;
> case RPI_FWREQ_FRAMEBUFFER_TEST_DEPTH:
> resplen = 4;
> break;
> case RPI_FWREQ_FRAMEBUFFER_SET_DEPTH:
> fbconfig.bpp = ldl_le_phys(&s->dma_as, value + 12);
> bcm2835_fb_validate_config(&fbconfig);
> fbconfig_updated = true;
> - /* fall through */
> + fallthrough;
> case RPI_FWREQ_FRAMEBUFFER_GET_DEPTH:
> stl_le_phys(&s->dma_as, value + 12, fbconfig.bpp);
> resplen = 4;
> break;
> case RPI_FWREQ_FRAMEBUFFER_TEST_PIXEL_ORDER:
> resplen = 4;
> break;
> case RPI_FWREQ_FRAMEBUFFER_SET_PIXEL_ORDER:
> fbconfig.pixo = ldl_le_phys(&s->dma_as, value + 12);
> bcm2835_fb_validate_config(&fbconfig);
> fbconfig_updated = true;
> - /* fall through */
> + fallthrough;
> case RPI_FWREQ_FRAMEBUFFER_GET_PIXEL_ORDER:
> stl_le_phys(&s->dma_as, value + 12, fbconfig.pixo);
> resplen = 4;
> break;
> case RPI_FWREQ_FRAMEBUFFER_TEST_ALPHA_MODE:
> resplen = 4;
> break;
> case RPI_FWREQ_FRAMEBUFFER_SET_ALPHA_MODE:
> fbconfig.alpha = ldl_le_phys(&s->dma_as, value + 12);
> bcm2835_fb_validate_config(&fbconfig);
> fbconfig_updated = true;
> - /* fall through */
> + fallthrough;
> case RPI_FWREQ_FRAMEBUFFER_GET_ALPHA_MODE:
> stl_le_phys(&s->dma_as, value + 12, fbconfig.alpha);
> resplen = 4;
> break;
> case RPI_FWREQ_FRAMEBUFFER_GET_PITCH:
> stl_le_phys(&s->dma_as, value + 12,
> bcm2835_fb_get_pitch(&fbconfig));
> resplen = 4;
> break;
> case RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_OFFSET:
> resplen = 8;
> break;
> case RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_OFFSET:
> fbconfig.xoffset = ldl_le_phys(&s->dma_as, value + 12);
> fbconfig.yoffset = ldl_le_phys(&s->dma_as, value + 16);
> bcm2835_fb_validate_config(&fbconfig);
> fbconfig_updated = true;
> - /* fall through */
> + fallthrough;
> case RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_OFFSET:
> stl_le_phys(&s->dma_as, value + 12, fbconfig.xoffset);
> stl_le_phys(&s->dma_as, value + 16, fbconfig.yoffset);
> resplen = 8;
> break;
> case RPI_FWREQ_FRAMEBUFFER_GET_OVERSCAN:
> case RPI_FWREQ_FRAMEBUFFER_TEST_OVERSCAN:
> case RPI_FWREQ_FRAMEBUFFER_SET_OVERSCAN:
> stl_le_phys(&s->dma_as, value + 12, 0);
> stl_le_phys(&s->dma_as, value + 16, 0);
> stl_le_phys(&s->dma_as, value + 20, 0);
> stl_le_phys(&s->dma_as, value + 24, 0);
> resplen = 16;
> break;
> case RPI_FWREQ_FRAMEBUFFER_SET_PALETTE:
> offset = ldl_le_phys(&s->dma_as, value + 12);
> length = ldl_le_phys(&s->dma_as, value + 16);
> n = 0;
> while (n < length - offset) {
> color = ldl_le_phys(&s->dma_as, value + 20 + (n << 2));
> stl_le_phys(&s->dma_as,
> s->fbdev->vcram_base + ((offset + n) << 2), color);
> n++;
> }
> stl_le_phys(&s->dma_as, value + 12, 0);
> resplen = 4;
> break;
> case RPI_FWREQ_FRAMEBUFFER_GET_NUM_DISPLAYS:
> stl_le_phys(&s->dma_as, value + 12, 1);
> resplen = 4;
> break;
>
> case RPI_FWREQ_GET_DMA_CHANNELS:
> /* channels 2-5 */
> stl_le_phys(&s->dma_as, value + 12, 0x003C);
> resplen = 4;
> break;
>
> case RPI_FWREQ_GET_COMMAND_LINE:
> /*
> * We follow the firmware behaviour: no NUL terminator is
> * written to the buffer, and if the buffer is too short
> * we report the required length in the response header
> * and copy nothing to the buffer.
> */
> resplen = strlen(s->command_line);
> if (bufsize >= resplen)
> address_space_write(&s->dma_as, value + 12,
> MEMTXATTRS_UNSPECIFIED, s->command_line,
> resplen);
> break;
>
> default:
> qemu_log_mask(LOG_UNIMP,
> "bcm2835_property: unhandled tag 0x%08x\n", tag);
> break;
> }
>
> trace_bcm2835_mbox_property(tag, bufsize, resplen);
> if (tag == 0) {
> break;
> }
>
> stl_le_phys(&s->dma_as, value + 8, (1 << 31) | resplen);
> value += bufsize + 12;
> }
>
> /* Reconfigure framebuffer if required */
> if (fbconfig_updated) {
> bcm2835_fb_reconfigure(s->fbdev, &fbconfig);
> }
>
> /* Buffer response code */
> stl_le_phys(&s->dma_as, s->addr + 4, (1 << 31));
> }
> diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
> index d6ba47bde9..a62349e6a0 100644
> --- a/hw/misc/mos6522.c
> +++ b/hw/misc/mos6522.c
> @@ -296,97 +296,97 @@ static void mos6522_portB_write(MOS6522State *s)
> uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
> {
> MOS6522State *s = opaque;
> uint32_t val;
> int ctrl;
> int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
>
> if (now >= s->timers[0].next_irq_time) {
> mos6522_timer1_update(s, &s->timers[0], now);
> s->ifr |= T1_INT;
> }
> if (now >= s->timers[1].next_irq_time) {
> mos6522_timer2_update(s, &s->timers[1], now);
> s->ifr |= T2_INT;
> }
> switch (addr) {
> case VIA_REG_B:
> val = s->b;
> ctrl = (s->pcr & CB2_CTRL_MASK) >> CB2_CTRL_SHIFT;
> if (!(ctrl & C2_IND)) {
> s->ifr &= ~CB2_INT;
> }
> s->ifr &= ~CB1_INT;
> mos6522_update_irq(s);
> break;
> case VIA_REG_A:
> qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake");
> - /* fall through */
> + fallthrough;
> case VIA_REG_ANH:
> val = s->a;
> ctrl = (s->pcr & CA2_CTRL_MASK) >> CA2_CTRL_SHIFT;
> if (!(ctrl & C2_IND)) {
> s->ifr &= ~CA2_INT;
> }
> s->ifr &= ~CA1_INT;
> mos6522_update_irq(s);
> break;
> case VIA_REG_DIRB:
> val = s->dirb;
> break;
> case VIA_REG_DIRA:
> val = s->dira;
> break;
> case VIA_REG_T1CL:
> val = get_counter(s, &s->timers[0]) & 0xff;
> s->ifr &= ~T1_INT;
> mos6522_update_irq(s);
> break;
> case VIA_REG_T1CH:
> val = get_counter(s, &s->timers[0]) >> 8;
> mos6522_update_irq(s);
> break;
> case VIA_REG_T1LL:
> val = s->timers[0].latch & 0xff;
> break;
> case VIA_REG_T1LH:
> /* XXX: check this */
> val = (s->timers[0].latch >> 8) & 0xff;
> break;
> case VIA_REG_T2CL:
> val = get_counter(s, &s->timers[1]) & 0xff;
> s->ifr &= ~T2_INT;
> mos6522_update_irq(s);
> break;
> case VIA_REG_T2CH:
> val = get_counter(s, &s->timers[1]) >> 8;
> break;
> case VIA_REG_SR:
> val = s->sr;
> s->ifr &= ~SR_INT;
> mos6522_update_irq(s);
> break;
> case VIA_REG_ACR:
> val = s->acr;
> break;
> case VIA_REG_PCR:
> val = s->pcr;
> break;
> case VIA_REG_IFR:
> val = s->ifr;
> if (s->ifr & s->ier) {
> val |= 0x80;
> }
> break;
> case VIA_REG_IER:
> val = s->ier | 0x80;
> break;
> default:
> g_assert_not_reached();
> }
>
> if (addr != VIA_REG_IFR || val != 0) {
> trace_mos6522_read(addr, mos6522_reg_names[addr], val);
> }
>
> return val;
> }
> @@ -394,105 +394,105 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
> void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
> {
> MOS6522State *s = opaque;
> MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s);
> int ctrl;
>
> trace_mos6522_write(addr, mos6522_reg_names[addr], val);
>
> switch (addr) {
> case VIA_REG_B:
> s->b = (s->b & ~s->dirb) | (val & s->dirb);
> mdc->portB_write(s);
> ctrl = (s->pcr & CB2_CTRL_MASK) >> CB2_CTRL_SHIFT;
> if (!(ctrl & C2_IND)) {
> s->ifr &= ~CB2_INT;
> }
> s->ifr &= ~CB1_INT;
> mos6522_update_irq(s);
> break;
> case VIA_REG_A:
> qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake");
> - /* fall through */
> + fallthrough;
> case VIA_REG_ANH:
> s->a = (s->a & ~s->dira) | (val & s->dira);
> mdc->portA_write(s);
> ctrl = (s->pcr & CA2_CTRL_MASK) >> CA2_CTRL_SHIFT;
> if (!(ctrl & C2_IND)) {
> s->ifr &= ~CA2_INT;
> }
> s->ifr &= ~CA1_INT;
> mos6522_update_irq(s);
> break;
> case VIA_REG_DIRB:
> s->dirb = val;
> break;
> case VIA_REG_DIRA:
> s->dira = val;
> break;
> case VIA_REG_T1CL:
> s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
> mos6522_timer1_update(s, &s->timers[0],
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
> break;
> case VIA_REG_T1CH:
> s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
> s->ifr &= ~T1_INT;
> set_counter(s, &s->timers[0], s->timers[0].latch);
> break;
> case VIA_REG_T1LL:
> s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
> mos6522_timer1_update(s, &s->timers[0],
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
> break;
> case VIA_REG_T1LH:
> s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
> s->ifr &= ~T1_INT;
> mos6522_timer1_update(s, &s->timers[0],
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
> break;
> case VIA_REG_T2CL:
> s->timers[1].latch = (s->timers[1].latch & 0xff00) | val;
> break;
> case VIA_REG_T2CH:
> /* To ensure T2 generates an interrupt on zero crossing with the
> common timer code, write the value directly from the latch to
> the counter */
> s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8);
> s->ifr &= ~T2_INT;
> set_counter(s, &s->timers[1], s->timers[1].latch);
> break;
> case VIA_REG_SR:
> s->sr = val;
> break;
> case VIA_REG_ACR:
> s->acr = val;
> mos6522_timer1_update(s, &s->timers[0],
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
> break;
> case VIA_REG_PCR:
> s->pcr = val;
> break;
> case VIA_REG_IFR:
> /* reset bits */
> s->ifr &= ~val;
> mos6522_update_irq(s);
> break;
> case VIA_REG_IER:
> if (val & IER_SET) {
> /* set bits */
> s->ier |= val & 0x7f;
> } else {
> /* reset bits */
> s->ier &= ~val;
> }
> mos6522_update_irq(s);
> /* if IER is modified starts needed timers */
> mos6522_timer1_update(s, &s->timers[0],
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
> mos6522_timer2_update(s, &s->timers[1],
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
> break;
> default:
> g_assert_not_reached();
> }
> }
^ permalink raw reply [flat|nested] 22+ messages in thread
* [RFC PATCH 43/75] hw/m68k/mcf_intc.c: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (5 preceding siblings ...)
2023-10-13 7:47 ` [RFC PATCH 42/75] hw/misc: " Emmanouil Pitsidianakis
@ 2023-10-13 7:47 ` Emmanouil Pitsidianakis
2023-10-13 7:47 ` [RFC PATCH 44/75] hw/dma: " Emmanouil Pitsidianakis
` (12 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:47 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block; +Cc: Emmanouil Pitsidianakis, Thomas Huth
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/m68k/mcf_intc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/m68k/mcf_intc.c b/hw/m68k/mcf_intc.c
index 4cd30188c0..9556a0ccb7 100644
--- a/hw/m68k/mcf_intc.c
+++ b/hw/m68k/mcf_intc.c
@@ -58,34 +58,34 @@ static void mcf_intc_update(mcf_intc_state *s)
static uint64_t mcf_intc_read(void *opaque, hwaddr addr,
unsigned size)
{
int offset;
mcf_intc_state *s = (mcf_intc_state *)opaque;
offset = addr & 0xff;
if (offset >= 0x40 && offset < 0x80) {
return s->icr[offset - 0x40];
}
switch (offset) {
case 0x00:
return (uint32_t)(s->ipr >> 32);
case 0x04:
return (uint32_t)s->ipr;
case 0x08:
return (uint32_t)(s->imr >> 32);
case 0x0c:
return (uint32_t)s->imr;
case 0x10:
return (uint32_t)(s->ifr >> 32);
case 0x14:
return (uint32_t)s->ifr;
case 0xe0: /* SWIACK. */
return s->active_vector;
case 0xe1: case 0xe2: case 0xe3: case 0xe4:
case 0xe5: case 0xe6: case 0xe7:
/* LnIACK */
qemu_log_mask(LOG_UNIMP, "%s: LnIACK not implemented (offset 0x%02x)\n",
__func__, offset);
- /* fallthru */
+ fallthrough;
default:
return 0;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 44/75] hw/dma: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (6 preceding siblings ...)
2023-10-13 7:47 ` [RFC PATCH 43/75] hw/m68k/mcf_intc.c: " Emmanouil Pitsidianakis
@ 2023-10-13 7:47 ` Emmanouil Pitsidianakis
2023-10-13 7:47 ` [RFC PATCH 45/75] disas: " Emmanouil Pitsidianakis
` (11 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:47 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block
Cc: Emmanouil Pitsidianakis, Peter Maydell, Mark Cave-Ayland
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/dma/omap_dma.c | 32 ++++++++++++++++----------------
hw/dma/pxa2xx_dma.c | 4 ++--
hw/dma/sparc32_dma.c | 2 +-
3 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c
index 77797a67b5..dd43dbf3d2 100644
--- a/hw/dma/omap_dma.c
+++ b/hw/dma/omap_dma.c
@@ -1457,46 +1457,46 @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_dma_s *s = opaque;
int reg, ch;
uint16_t ret;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x300 ... 0x3fe:
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
break;
return ret;
}
- /* Fall through. */
+ fallthrough;
case 0x000 ... 0x2fe:
reg = addr & 0x3f;
ch = (addr >> 6) & 0x0f;
if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
break;
return ret;
case 0x404 ... 0x4fe:
if (s->model <= omap_dma_3_1)
break;
- /* Fall through. */
+ fallthrough;
case 0x400:
if (omap_dma_sys_read(s, addr, &ret))
break;
return ret;
case 0xb00 ... 0xbfe:
if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
break;
return ret;
}
break;
}
OMAP_BAD_REG(addr);
return 0;
}
@@ -1504,46 +1504,46 @@ static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
static void omap_dma_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = opaque;
int reg, ch;
if (size != 2) {
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
case 0x300 ... 0x3fe:
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
break;
return;
}
- /* Fall through. */
+ fallthrough;
case 0x000 ... 0x2fe:
reg = addr & 0x3f;
ch = (addr >> 6) & 0x0f;
if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
break;
return;
case 0x404 ... 0x4fe:
if (s->model <= omap_dma_3_1)
break;
- /* fall through */
+ fallthrough;
case 0x400:
if (omap_dma_sys_write(s, addr, value))
break;
return;
case 0xb00 ... 0xbfe:
if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
break;
return;
}
break;
}
OMAP_BAD_REG(addr);
}
@@ -1702,155 +1702,155 @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dma_s *s = opaque;
int irqn = 0, chnum;
struct omap_dma_channel_s *ch;
if (size == 1) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x00: /* DMA4_REVISION */
return 0x40;
case 0x14: /* DMA4_IRQSTATUS_L3 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x10: /* DMA4_IRQSTATUS_L2 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x0c: /* DMA4_IRQSTATUS_L1 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x08: /* DMA4_IRQSTATUS_L0 */
return s->irqstat[irqn];
case 0x24: /* DMA4_IRQENABLE_L3 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x20: /* DMA4_IRQENABLE_L2 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x1c: /* DMA4_IRQENABLE_L1 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x18: /* DMA4_IRQENABLE_L0 */
return s->irqen[irqn];
case 0x28: /* DMA4_SYSSTATUS */
return 1; /* RESETDONE */
case 0x2c: /* DMA4_OCP_SYSCONFIG */
return s->ocp;
case 0x64: /* DMA4_CAPS_0 */
return s->caps[0];
case 0x6c: /* DMA4_CAPS_2 */
return s->caps[2];
case 0x70: /* DMA4_CAPS_3 */
return s->caps[3];
case 0x74: /* DMA4_CAPS_4 */
return s->caps[4];
case 0x78: /* DMA4_GCR */
return s->gcr;
case 0x80 ... 0xfff:
addr -= 0x80;
chnum = addr / 0x60;
ch = s->ch + chnum;
addr -= chnum * 0x60;
break;
default:
OMAP_BAD_REG(addr);
return 0;
}
/* Per-channel registers */
switch (addr) {
case 0x00: /* DMA4_CCR */
return (ch->buf_disable << 25) |
(ch->src_sync << 24) |
(ch->prefetch << 23) |
((ch->sync & 0x60) << 14) |
(ch->bs << 18) |
(ch->transparent_copy << 17) |
(ch->constant_fill << 16) |
(ch->mode[1] << 14) |
(ch->mode[0] << 12) |
(0 << 10) | (0 << 9) |
(ch->suspend << 8) |
(ch->enable << 7) |
(ch->priority << 6) |
(ch->fs << 5) | (ch->sync & 0x1f);
case 0x04: /* DMA4_CLNK_CTRL */
return (ch->link_enabled << 15) | ch->link_next_ch;
case 0x08: /* DMA4_CICR */
return ch->interrupts;
case 0x0c: /* DMA4_CSR */
return ch->cstatus;
case 0x10: /* DMA4_CSDP */
return (ch->endian[0] << 21) |
(ch->endian_lock[0] << 20) |
(ch->endian[1] << 19) |
(ch->endian_lock[1] << 18) |
(ch->write_mode << 16) |
(ch->burst[1] << 14) |
(ch->pack[1] << 13) |
(ch->translate[1] << 9) |
(ch->burst[0] << 7) |
(ch->pack[0] << 6) |
(ch->translate[0] << 2) |
(ch->data_type >> 1);
case 0x14: /* DMA4_CEN */
return ch->elements;
case 0x18: /* DMA4_CFN */
return ch->frames;
case 0x1c: /* DMA4_CSSA */
return ch->addr[0];
case 0x20: /* DMA4_CDSA */
return ch->addr[1];
case 0x24: /* DMA4_CSEI */
return ch->element_index[0];
case 0x28: /* DMA4_CSFI */
return ch->frame_index[0];
case 0x2c: /* DMA4_CDEI */
return ch->element_index[1];
case 0x30: /* DMA4_CDFI */
return ch->frame_index[1];
case 0x34: /* DMA4_CSAC */
return ch->active_set.src & 0xffff;
case 0x38: /* DMA4_CDAC */
return ch->active_set.dest & 0xffff;
case 0x3c: /* DMA4_CCEN */
return ch->active_set.element;
case 0x40: /* DMA4_CCFN */
return ch->active_set.frame;
case 0x44: /* DMA4_COLOR */
/* XXX only in sDMA */
return ch->color;
default:
OMAP_BAD_REG(addr);
return 0;
}
}
@@ -1858,213 +1858,213 @@ static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
static void omap_dma4_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = opaque;
int chnum, irqn = 0;
struct omap_dma_channel_s *ch;
if (size == 1) {
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
case 0x14: /* DMA4_IRQSTATUS_L3 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x10: /* DMA4_IRQSTATUS_L2 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x0c: /* DMA4_IRQSTATUS_L1 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x08: /* DMA4_IRQSTATUS_L0 */
s->irqstat[irqn] &= ~value;
if (!s->irqstat[irqn])
qemu_irq_lower(s->irq[irqn]);
return;
case 0x24: /* DMA4_IRQENABLE_L3 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x20: /* DMA4_IRQENABLE_L2 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x1c: /* DMA4_IRQENABLE_L1 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x18: /* DMA4_IRQENABLE_L0 */
s->irqen[irqn] = value;
return;
case 0x2c: /* DMA4_OCP_SYSCONFIG */
if (value & 2) /* SOFTRESET */
omap_dma_reset(s->dma);
s->ocp = value & 0x3321;
if (((s->ocp >> 12) & 3) == 3) { /* MIDLEMODE */
qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA power mode\n",
__func__);
}
return;
case 0x78: /* DMA4_GCR */
s->gcr = value & 0x00ff00ff;
if ((value & 0xff) == 0x00) { /* MAX_CHANNEL_FIFO_DEPTH */
qemu_log_mask(LOG_GUEST_ERROR, "%s: wrong FIFO depth in GCR\n",
__func__);
}
return;
case 0x80 ... 0xfff:
addr -= 0x80;
chnum = addr / 0x60;
ch = s->ch + chnum;
addr -= chnum * 0x60;
break;
case 0x00: /* DMA4_REVISION */
case 0x28: /* DMA4_SYSSTATUS */
case 0x64: /* DMA4_CAPS_0 */
case 0x6c: /* DMA4_CAPS_2 */
case 0x70: /* DMA4_CAPS_3 */
case 0x74: /* DMA4_CAPS_4 */
OMAP_RO_REG(addr);
return;
default:
OMAP_BAD_REG(addr);
return;
}
/* Per-channel registers */
switch (addr) {
case 0x00: /* DMA4_CCR */
ch->buf_disable = (value >> 25) & 1;
ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */
if (ch->buf_disable && !ch->src_sync) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Buffering disable is not allowed in "
"destination synchronised mode\n", __func__);
}
ch->prefetch = (value >> 23) & 1;
ch->bs = (value >> 18) & 1;
ch->transparent_copy = (value >> 17) & 1;
ch->constant_fill = (value >> 16) & 1;
ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
ch->suspend = (value & 0x0100) >> 8;
ch->priority = (value & 0x0040) >> 6;
ch->fs = (value & 0x0020) >> 5;
if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: For a packet transfer at least one port "
"must be constant-addressed\n", __func__);
}
ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060);
/* XXX must be 0x01 for CamDMA */
if (value & 0x0080)
omap_dma_enable_channel(s, ch);
else
omap_dma_disable_channel(s, ch);
break;
case 0x04: /* DMA4_CLNK_CTRL */
ch->link_enabled = (value >> 15) & 0x1;
ch->link_next_ch = value & 0x1f;
break;
case 0x08: /* DMA4_CICR */
ch->interrupts = value & 0x09be;
break;
case 0x0c: /* DMA4_CSR */
ch->cstatus &= ~value;
break;
case 0x10: /* DMA4_CSDP */
ch->endian[0] =(value >> 21) & 1;
ch->endian_lock[0] =(value >> 20) & 1;
ch->endian[1] =(value >> 19) & 1;
ch->endian_lock[1] =(value >> 18) & 1;
if (ch->endian[0] != ch->endian[1]) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: DMA endianness conversion enable attempt\n",
__func__);
}
ch->write_mode = (value >> 16) & 3;
ch->burst[1] = (value & 0xc000) >> 14;
ch->pack[1] = (value & 0x2000) >> 13;
ch->translate[1] = (value & 0x1e00) >> 9;
ch->burst[0] = (value & 0x0180) >> 7;
ch->pack[0] = (value & 0x0040) >> 6;
ch->translate[0] = (value & 0x003c) >> 2;
if (ch->translate[0] | ch->translate[1]) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: bad MReqAddressTranslate sideband signal\n",
__func__);
}
ch->data_type = 1 << (value & 3);
if ((value & 3) == 3) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: bad data_type for DMA channel\n", __func__);
ch->data_type >>= 1;
}
break;
case 0x14: /* DMA4_CEN */
ch->set_update = 1;
ch->elements = value & 0xffffff;
break;
case 0x18: /* DMA4_CFN */
ch->frames = value & 0xffff;
ch->set_update = 1;
break;
case 0x1c: /* DMA4_CSSA */
ch->addr[0] = (hwaddr) (uint32_t) value;
ch->set_update = 1;
break;
case 0x20: /* DMA4_CDSA */
ch->addr[1] = (hwaddr) (uint32_t) value;
ch->set_update = 1;
break;
case 0x24: /* DMA4_CSEI */
ch->element_index[0] = (int16_t) value;
ch->set_update = 1;
break;
case 0x28: /* DMA4_CSFI */
ch->frame_index[0] = (int32_t) value;
ch->set_update = 1;
break;
case 0x2c: /* DMA4_CDEI */
ch->element_index[1] = (int16_t) value;
ch->set_update = 1;
break;
case 0x30: /* DMA4_CDFI */
ch->frame_index[1] = (int32_t) value;
ch->set_update = 1;
break;
case 0x44: /* DMA4_COLOR */
/* XXX only in sDMA */
ch->color = value;
break;
case 0x34: /* DMA4_CSAC */
case 0x38: /* DMA4_CDAC */
case 0x3c: /* DMA4_CCEN */
case 0x40: /* DMA4_CCFN */
OMAP_RO_REG(addr);
break;
default:
OMAP_BAD_REG(addr);
}
}
diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c
index fa896f7edf..ac47256572 100644
--- a/hw/dma/pxa2xx_dma.c
+++ b/hw/dma/pxa2xx_dma.c
@@ -266,59 +266,59 @@ static void pxa2xx_dma_run(PXA2xxDMAState *s)
static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
unsigned int channel;
if (size != 4) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
__func__, size);
return 5;
}
switch (offset) {
case DRCMR64 ... DRCMR74:
offset -= DRCMR64 - DRCMR0 - (64 << 2);
- /* Fall through */
+ fallthrough;
case DRCMR0 ... DRCMR63:
channel = (offset - DRCMR0) >> 2;
return s->req[channel];
case DRQSR0:
case DRQSR1:
case DRQSR2:
return 0;
case DCSR0 ... DCSR31:
channel = offset >> 2;
if (s->chan[channel].request)
return s->chan[channel].state | DCSR_REQPEND;
return s->chan[channel].state;
case DINT:
return s->stopintr | s->eorintr | s->rasintr |
s->startintr | s->endintr;
case DALGN:
return s->align;
case DPCSR:
return s->pio;
}
if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
channel = (offset - D_CH0) >> 4;
switch ((offset & 0x0f) >> 2) {
case DDADR:
return s->chan[channel].descr;
case DSADR:
return s->chan[channel].src;
case DTADR:
return s->chan[channel].dest;
case DCMD:
return s->chan[channel].cmd;
}
}
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
__func__, offset);
return 7;
}
@@ -326,105 +326,105 @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
static void pxa2xx_dma_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
unsigned int channel;
if (size != 4) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
__func__, size);
return;
}
switch (offset) {
case DRCMR64 ... DRCMR74:
offset -= DRCMR64 - DRCMR0 - (64 << 2);
- /* Fall through */
+ fallthrough;
case DRCMR0 ... DRCMR63:
channel = (offset - DRCMR0) >> 2;
if (value & DRCMR_MAPVLD)
if ((value & DRCMR_CHLNUM) > s->channels)
hw_error("%s: Bad DMA channel %i\n",
__func__, (unsigned)value & DRCMR_CHLNUM);
s->req[channel] = value;
break;
case DRQSR0:
case DRQSR1:
case DRQSR2:
/* Nothing to do */
break;
case DCSR0 ... DCSR31:
channel = offset >> 2;
s->chan[channel].state &= 0x0000071f & ~(value &
(DCSR_EORINT | DCSR_ENDINTR |
DCSR_STARTINTR | DCSR_BUSERRINTR));
s->chan[channel].state |= value & 0xfc800000;
if (s->chan[channel].state & DCSR_STOPIRQEN)
s->chan[channel].state &= ~DCSR_STOPINTR;
if (value & DCSR_NODESCFETCH) {
/* No-descriptor-fetch mode */
if (value & DCSR_RUN) {
s->chan[channel].state &= ~DCSR_STOPINTR;
pxa2xx_dma_run(s);
}
} else {
/* Descriptor-fetch mode */
if (value & DCSR_RUN) {
s->chan[channel].state &= ~DCSR_STOPINTR;
pxa2xx_dma_descriptor_fetch(s, channel);
pxa2xx_dma_run(s);
}
}
/* Shouldn't matter as our DMA is synchronous. */
if (!(value & (DCSR_RUN | DCSR_MASKRUN)))
s->chan[channel].state |= DCSR_STOPINTR;
if (value & DCSR_CLRCMPST)
s->chan[channel].state &= ~DCSR_CMPST;
if (value & DCSR_SETCMPST)
s->chan[channel].state |= DCSR_CMPST;
pxa2xx_dma_update(s, channel);
break;
case DALGN:
s->align = value;
break;
case DPCSR:
s->pio = value & 0x80000001;
break;
default:
if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
channel = (offset - D_CH0) >> 4;
switch ((offset & 0x0f) >> 2) {
case DDADR:
s->chan[channel].descr = value;
break;
case DSADR:
s->chan[channel].src = value;
break;
case DTADR:
s->chan[channel].dest = value;
break;
case DCMD:
s->chan[channel].cmd = value;
break;
default:
goto fail;
}
break;
}
fail:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
__func__, offset);
}
}
diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c
index 0ef13c5e9a..c68e068cc9 100644
--- a/hw/dma/sparc32_dma.c
+++ b/hw/dma/sparc32_dma.c
@@ -180,49 +180,49 @@ static uint64_t dma_mem_read(void *opaque, hwaddr addr,
static void dma_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
DMADeviceState *s = opaque;
uint32_t saddr;
saddr = (addr & DMA_MASK) >> 2;
trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
switch (saddr) {
case 0:
if (val & DMA_INTREN) {
if (s->dmaregs[0] & DMA_INTR) {
trace_sparc32_dma_set_irq_raise();
qemu_irq_raise(s->irq);
}
} else {
if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
trace_sparc32_dma_set_irq_lower();
qemu_irq_lower(s->irq);
}
}
if (val & DMA_RESET) {
qemu_irq_raise(s->gpio[GPIO_RESET]);
qemu_irq_lower(s->gpio[GPIO_RESET]);
} else if (val & DMA_DRAIN_FIFO) {
val &= ~DMA_DRAIN_FIFO;
} else if (val == 0)
val = DMA_DRAIN_FIFO;
if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
trace_sparc32_dma_enable_raise();
qemu_irq_raise(s->gpio[GPIO_DMA]);
} else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
trace_sparc32_dma_enable_lower();
qemu_irq_lower(s->gpio[GPIO_DMA]);
}
val &= ~DMA_CSR_RO_MASK;
val |= DMA_VER;
s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
break;
case 1:
s->dmaregs[0] |= DMA_LOADED;
- /* fall through */
+ fallthrough;
default:
s->dmaregs[saddr] = val;
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 45/75] disas: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (7 preceding siblings ...)
2023-10-13 7:47 ` [RFC PATCH 44/75] hw/dma: " Emmanouil Pitsidianakis
@ 2023-10-13 7:47 ` Emmanouil Pitsidianakis
2023-10-13 7:47 ` [RFC PATCH 46/75] contrib/rdmacm-mux: " Emmanouil Pitsidianakis
` (10 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:47 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block
Cc: Emmanouil Pitsidianakis, Richard Henderson, Laurent Vivier,
Yoshinori Sato, Mark Cave-Ayland, Artyom Tarasenko
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
disas/hppa.c | 4 ++--
disas/m68k.c | 2 +-
disas/sh4.c | 4 +++-
disas/sparc.c | 2 +-
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/disas/hppa.c b/disas/hppa.c
index dcf9a47f34..1a2bdb8d39 100644
--- a/disas/hppa.c
+++ b/disas/hppa.c
@@ -1954,878 +1954,878 @@ int
print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
{
bfd_byte buffer[4];
unsigned int insn, i;
{
int status =
(*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
}
insn = bfd_getb32 (buffer);
for (i = 0; i < NUMOPCODES; ++i)
{
const struct pa_opcode *opcode = &pa_opcodes[i];
if ((insn & opcode->mask) == opcode->match)
{
const char *s;
#ifndef BFD64
if (opcode->arch == pa20w)
continue;
#endif
(*info->fprintf_func) (info->stream, "%s", opcode->name);
if (!strchr ("cfCY?-+nHNZFIuv{", opcode->args[0]))
(*info->fprintf_func) (info->stream, " ");
for (s = opcode->args; *s != '\0'; ++s)
{
switch (*s)
{
case 'x':
fput_reg (GET_FIELD (insn, 11, 15), info);
break;
case 'a':
case 'b':
fput_reg (GET_FIELD (insn, 6, 10), info);
break;
case '^':
fput_creg (GET_FIELD (insn, 6, 10), info);
break;
case 't':
fput_reg (GET_FIELD (insn, 27, 31), info);
break;
/* Handle floating point registers. */
case 'f':
switch (*++s)
{
case 't':
fput_fp_reg (GET_FIELD (insn, 27, 31), info);
break;
case 'T':
if (GET_FIELD (insn, 25, 25))
fput_fp_reg_r (GET_FIELD (insn, 27, 31), info);
else
fput_fp_reg (GET_FIELD (insn, 27, 31), info);
break;
case 'a':
if (GET_FIELD (insn, 25, 25))
fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
else
fput_fp_reg (GET_FIELD (insn, 6, 10), info);
break;
/* 'fA' will not generate a space before the register
name. Normally that is fine. Except that it
causes problems with xmpyu which has no FP format
completer. */
case 'X':
fputs_filtered (" ", info);
- /* FALLTHRU */
+ fallthrough;
case 'A':
if (GET_FIELD (insn, 24, 24))
fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
else
fput_fp_reg (GET_FIELD (insn, 6, 10), info);
break;
case 'b':
if (GET_FIELD (insn, 25, 25))
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
else
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
break;
case 'B':
if (GET_FIELD (insn, 19, 19))
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
else
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
break;
case 'C':
{
int reg = GET_FIELD (insn, 21, 22);
reg |= GET_FIELD (insn, 16, 18) << 2;
if (GET_FIELD (insn, 23, 23) != 0)
fput_fp_reg_r (reg, info);
else
fput_fp_reg (reg, info);
break;
}
case 'i':
{
int reg = GET_FIELD (insn, 6, 10);
reg |= (GET_FIELD (insn, 26, 26) << 4);
fput_fp_reg (reg, info);
break;
}
case 'j':
{
int reg = GET_FIELD (insn, 11, 15);
reg |= (GET_FIELD (insn, 26, 26) << 4);
fput_fp_reg (reg, info);
break;
}
case 'k':
{
int reg = GET_FIELD (insn, 27, 31);
reg |= (GET_FIELD (insn, 26, 26) << 4);
fput_fp_reg (reg, info);
break;
}
case 'l':
{
int reg = GET_FIELD (insn, 21, 25);
reg |= (GET_FIELD (insn, 26, 26) << 4);
fput_fp_reg (reg, info);
break;
}
case 'm':
{
int reg = GET_FIELD (insn, 16, 20);
reg |= (GET_FIELD (insn, 26, 26) << 4);
fput_fp_reg (reg, info);
break;
}
/* 'fe' will not generate a space before the register
name. Normally that is fine. Except that it
causes problems with fstw fe,y(b) which has no FP
format completer. */
case 'E':
fputs_filtered (" ", info);
- /* FALLTHRU */
+ fallthrough;
case 'e':
if (GET_FIELD (insn, 30, 30))
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
else
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
break;
case 'x':
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
break;
}
break;
case '5':
fput_const (extract_5_load (insn), info);
break;
case 's':
{
int space = GET_FIELD (insn, 16, 17);
/* Zero means implicit addressing, not use of sr0. */
if (space != 0)
(*info->fprintf_func) (info->stream, "sr%d", space);
}
break;
case 'S':
(*info->fprintf_func) (info->stream, "sr%d",
extract_3 (insn));
break;
/* Handle completers. */
case 'c':
switch (*++s)
{
case 'x':
(*info->fprintf_func)
(info->stream, "%s",
index_compl_names[GET_COMPL (insn)]);
break;
case 'X':
(*info->fprintf_func)
(info->stream, "%s ",
index_compl_names[GET_COMPL (insn)]);
break;
case 'm':
(*info->fprintf_func)
(info->stream, "%s",
short_ldst_compl_names[GET_COMPL (insn)]);
break;
case 'M':
(*info->fprintf_func)
(info->stream, "%s ",
short_ldst_compl_names[GET_COMPL (insn)]);
break;
case 'A':
(*info->fprintf_func)
(info->stream, "%s ",
short_bytes_compl_names[GET_COMPL (insn)]);
break;
case 's':
(*info->fprintf_func)
(info->stream, "%s",
short_bytes_compl_names[GET_COMPL (insn)]);
break;
case 'c':
case 'C':
switch (GET_FIELD (insn, 20, 21))
{
case 1:
(*info->fprintf_func) (info->stream, ",bc ");
break;
case 2:
(*info->fprintf_func) (info->stream, ",sl ");
break;
default:
(*info->fprintf_func) (info->stream, " ");
}
break;
case 'd':
switch (GET_FIELD (insn, 20, 21))
{
case 1:
(*info->fprintf_func) (info->stream, ",co ");
break;
default:
(*info->fprintf_func) (info->stream, " ");
}
break;
case 'o':
(*info->fprintf_func) (info->stream, ",o");
break;
case 'g':
(*info->fprintf_func) (info->stream, ",gate");
break;
case 'p':
(*info->fprintf_func) (info->stream, ",l,push");
break;
case 'P':
(*info->fprintf_func) (info->stream, ",pop");
break;
case 'l':
case 'L':
(*info->fprintf_func) (info->stream, ",l");
break;
case 'w':
(*info->fprintf_func)
(info->stream, "%s ",
read_write_names[GET_FIELD (insn, 25, 25)]);
break;
case 'W':
(*info->fprintf_func) (info->stream, ",w ");
break;
case 'r':
if (GET_FIELD (insn, 23, 26) == 5)
(*info->fprintf_func) (info->stream, ",r");
break;
case 'Z':
if (GET_FIELD (insn, 26, 26))
(*info->fprintf_func) (info->stream, ",m ");
else
(*info->fprintf_func) (info->stream, " ");
break;
case 'i':
if (GET_FIELD (insn, 25, 25))
(*info->fprintf_func) (info->stream, ",i");
break;
case 'z':
if (!GET_FIELD (insn, 21, 21))
(*info->fprintf_func) (info->stream, ",z");
break;
case 'a':
(*info->fprintf_func)
(info->stream, "%s",
add_compl_names[GET_FIELD (insn, 20, 21)]);
break;
case 'Y':
(*info->fprintf_func)
(info->stream, ",dc%s",
add_compl_names[GET_FIELD (insn, 20, 21)]);
break;
case 'y':
(*info->fprintf_func)
(info->stream, ",c%s",
add_compl_names[GET_FIELD (insn, 20, 21)]);
break;
case 'v':
if (GET_FIELD (insn, 20, 20))
(*info->fprintf_func) (info->stream, ",tsv");
break;
case 't':
(*info->fprintf_func) (info->stream, ",tc");
if (GET_FIELD (insn, 20, 20))
(*info->fprintf_func) (info->stream, ",tsv");
break;
case 'B':
(*info->fprintf_func) (info->stream, ",db");
if (GET_FIELD (insn, 20, 20))
(*info->fprintf_func) (info->stream, ",tsv");
break;
case 'b':
(*info->fprintf_func) (info->stream, ",b");
if (GET_FIELD (insn, 20, 20))
(*info->fprintf_func) (info->stream, ",tsv");
break;
case 'T':
if (GET_FIELD (insn, 25, 25))
(*info->fprintf_func) (info->stream, ",tc");
break;
case 'S':
/* EXTRD/W has a following condition. */
if (*(s + 1) == '?')
(*info->fprintf_func)
(info->stream, "%s",
signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
else
(*info->fprintf_func)
(info->stream, "%s ",
signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
break;
case 'h':
(*info->fprintf_func)
(info->stream, "%s",
mix_half_names[GET_FIELD (insn, 17, 17)]);
break;
case 'H':
(*info->fprintf_func)
(info->stream, "%s ",
saturation_names[GET_FIELD (insn, 24, 25)]);
break;
case '*':
(*info->fprintf_func)
(info->stream, ",%d%d%d%d ",
GET_FIELD (insn, 17, 18), GET_FIELD (insn, 20, 21),
GET_FIELD (insn, 22, 23), GET_FIELD (insn, 24, 25));
break;
case 'q':
{
int m, a;
m = GET_FIELD (insn, 28, 28);
a = GET_FIELD (insn, 29, 29);
if (m && !a)
fputs_filtered (",ma ", info);
else if (m && a)
fputs_filtered (",mb ", info);
else
fputs_filtered (" ", info);
break;
}
case 'J':
{
int opc = GET_FIELD (insn, 0, 5);
if (opc == 0x16 || opc == 0x1e)
{
if (GET_FIELD (insn, 29, 29) == 0)
fputs_filtered (",ma ", info);
else
fputs_filtered (",mb ", info);
}
else
fputs_filtered (" ", info);
break;
}
case 'e':
{
int opc = GET_FIELD (insn, 0, 5);
if (opc == 0x13 || opc == 0x1b)
{
if (GET_FIELD (insn, 18, 18) == 1)
fputs_filtered (",mb ", info);
else
fputs_filtered (",ma ", info);
}
else if (opc == 0x17 || opc == 0x1f)
{
if (GET_FIELD (insn, 31, 31) == 1)
fputs_filtered (",ma ", info);
else
fputs_filtered (",mb ", info);
}
else
fputs_filtered (" ", info);
break;
}
}
break;
/* Handle conditions. */
case '?':
{
s++;
switch (*s)
{
case 'f':
(*info->fprintf_func)
(info->stream, "%s ",
float_comp_names[GET_FIELD (insn, 27, 31)]);
break;
/* These four conditions are for the set of instructions
which distinguish true/false conditions by opcode
rather than by the 'f' bit (sigh): comb, comib,
addb, addib. */
case 't':
fputs_filtered
(compare_cond_names[GET_FIELD (insn, 16, 18)], info);
break;
case 'n':
fputs_filtered
(compare_cond_names[GET_FIELD (insn, 16, 18)
+ GET_FIELD (insn, 4, 4) * 8],
info);
break;
case 'N':
fputs_filtered
(compare_cond_64_names[GET_FIELD (insn, 16, 18)
+ GET_FIELD (insn, 2, 2) * 8],
info);
break;
case 'Q':
fputs_filtered
(cmpib_cond_64_names[GET_FIELD (insn, 16, 18)],
info);
break;
case '@':
fputs_filtered
(add_cond_names[GET_FIELD (insn, 16, 18)
+ GET_FIELD (insn, 4, 4) * 8],
info);
break;
case 's':
(*info->fprintf_func)
(info->stream, "%s ",
compare_cond_names[GET_COND (insn)]);
break;
case 'S':
(*info->fprintf_func)
(info->stream, "%s ",
compare_cond_64_names[GET_COND (insn)]);
break;
case 'a':
(*info->fprintf_func)
(info->stream, "%s ",
add_cond_names[GET_COND (insn)]);
break;
case 'A':
(*info->fprintf_func)
(info->stream, "%s ",
add_cond_64_names[GET_COND (insn)]);
break;
case 'd':
(*info->fprintf_func)
(info->stream, "%s",
add_cond_names[GET_FIELD (insn, 16, 18)]);
break;
case 'W':
(*info->fprintf_func)
(info->stream, "%s",
wide_add_cond_names[GET_FIELD (insn, 16, 18) +
GET_FIELD (insn, 4, 4) * 8]);
break;
case 'l':
(*info->fprintf_func)
(info->stream, "%s ",
logical_cond_names[GET_COND (insn)]);
break;
case 'L':
(*info->fprintf_func)
(info->stream, "%s ",
logical_cond_64_names[GET_COND (insn)]);
break;
case 'u':
(*info->fprintf_func)
(info->stream, "%s ",
unit_cond_names[GET_COND (insn)]);
break;
case 'U':
(*info->fprintf_func)
(info->stream, "%s ",
unit_cond_64_names[GET_COND (insn)]);
break;
case 'y':
case 'x':
case 'b':
(*info->fprintf_func)
(info->stream, "%s",
shift_cond_names[GET_FIELD (insn, 16, 18)]);
/* If the next character in args is 'n', it will handle
putting out the space. */
if (s[1] != 'n')
(*info->fprintf_func) (info->stream, " ");
break;
case 'X':
(*info->fprintf_func)
(info->stream, "%s ",
shift_cond_64_names[GET_FIELD (insn, 16, 18)]);
break;
case 'B':
(*info->fprintf_func)
(info->stream, "%s",
bb_cond_64_names[GET_FIELD (insn, 16, 16)]);
/* If the next character in args is 'n', it will handle
putting out the space. */
if (s[1] != 'n')
(*info->fprintf_func) (info->stream, " ");
break;
}
break;
}
case 'V':
fput_const (extract_5_store (insn), info);
break;
case 'r':
fput_const (extract_5r_store (insn), info);
break;
case 'R':
fput_const (extract_5R_store (insn), info);
break;
case 'U':
fput_const (extract_10U_store (insn), info);
break;
case 'B':
case 'Q':
fput_const (extract_5Q_store (insn), info);
break;
case 'i':
fput_const (extract_11 (insn), info);
break;
case 'j':
fput_const (extract_14 (insn), info);
break;
case 'k':
fputs_filtered ("L%", info);
fput_const (extract_21 (insn), info);
break;
case '<':
case 'l':
/* 16-bit long disp., PA2.0 wide only. */
fput_const (extract_16 (insn), info);
break;
case 'n':
if (insn & 0x2)
(*info->fprintf_func) (info->stream, ",n ");
else
(*info->fprintf_func) (info->stream, " ");
break;
case 'N':
if ((insn & 0x20) && s[1])
(*info->fprintf_func) (info->stream, ",n ");
else if (insn & 0x20)
(*info->fprintf_func) (info->stream, ",n");
else if (s[1])
(*info->fprintf_func) (info->stream, " ");
break;
case 'w':
(*info->print_address_func)
(memaddr + 8 + extract_12 (insn), info);
break;
case 'W':
/* 17 bit PC-relative branch. */
(*info->print_address_func)
((memaddr + 8 + extract_17 (insn)), info);
break;
case 'z':
/* 17 bit displacement. This is an offset from a register
so it gets disasssembled as just a number, not any sort
of address. */
fput_const (extract_17 (insn), info);
break;
case 'Z':
/* addil %r1 implicit output. */
fputs_filtered ("r1", info);
break;
case 'Y':
/* be,l %sr0,%r31 implicit output. */
fputs_filtered ("sr0,r31", info);
break;
case '@':
(*info->fprintf_func) (info->stream, "0");
break;
case '.':
(*info->fprintf_func) (info->stream, "%d",
GET_FIELD (insn, 24, 25));
break;
case '*':
(*info->fprintf_func) (info->stream, "%d",
GET_FIELD (insn, 22, 25));
break;
case '!':
fputs_filtered ("sar", info);
break;
case 'p':
(*info->fprintf_func) (info->stream, "%d",
31 - GET_FIELD (insn, 22, 26));
break;
case '~':
{
int num;
num = GET_FIELD (insn, 20, 20) << 5;
num |= GET_FIELD (insn, 22, 26);
(*info->fprintf_func) (info->stream, "%d", 63 - num);
break;
}
case 'P':
(*info->fprintf_func) (info->stream, "%d",
GET_FIELD (insn, 22, 26));
break;
case 'q':
{
int num;
num = GET_FIELD (insn, 20, 20) << 5;
num |= GET_FIELD (insn, 22, 26);
(*info->fprintf_func) (info->stream, "%d", num);
break;
}
case 'T':
(*info->fprintf_func) (info->stream, "%d",
32 - GET_FIELD (insn, 27, 31));
break;
case '%':
{
int num;
num = (GET_FIELD (insn, 23, 23) + 1) * 32;
num -= GET_FIELD (insn, 27, 31);
(*info->fprintf_func) (info->stream, "%d", num);
break;
}
case '|':
{
int num;
num = (GET_FIELD (insn, 19, 19) + 1) * 32;
num -= GET_FIELD (insn, 27, 31);
(*info->fprintf_func) (info->stream, "%d", num);
break;
}
case '$':
fput_const (GET_FIELD (insn, 20, 28), info);
break;
case 'A':
fput_const (GET_FIELD (insn, 6, 18), info);
break;
case 'D':
fput_const (GET_FIELD (insn, 6, 31), info);
break;
case 'v':
(*info->fprintf_func) (info->stream, ",%d",
GET_FIELD (insn, 23, 25));
break;
case 'O':
fput_const ((GET_FIELD (insn, 6,20) << 5 |
GET_FIELD (insn, 27, 31)), info);
break;
case 'o':
fput_const (GET_FIELD (insn, 6, 20), info);
break;
case '2':
fput_const ((GET_FIELD (insn, 6, 22) << 5 |
GET_FIELD (insn, 27, 31)), info);
break;
case '1':
fput_const ((GET_FIELD (insn, 11, 20) << 5 |
GET_FIELD (insn, 27, 31)), info);
break;
case '0':
fput_const ((GET_FIELD (insn, 16, 20) << 5 |
GET_FIELD (insn, 27, 31)), info);
break;
case 'u':
(*info->fprintf_func) (info->stream, ",%d",
GET_FIELD (insn, 23, 25));
break;
case 'F':
/* If no destination completer and not before a completer
for fcmp, need a space here. */
if (s[1] == 'G' || s[1] == '?')
fputs_filtered
(float_format_names[GET_FIELD (insn, 19, 20)], info);
else
(*info->fprintf_func)
(info->stream, "%s ",
float_format_names[GET_FIELD (insn, 19, 20)]);
break;
case 'G':
(*info->fprintf_func)
(info->stream, "%s ",
float_format_names[GET_FIELD (insn, 17, 18)]);
break;
case 'H':
if (GET_FIELD (insn, 26, 26) == 1)
(*info->fprintf_func) (info->stream, "%s ",
float_format_names[0]);
else
(*info->fprintf_func) (info->stream, "%s ",
float_format_names[1]);
break;
case 'I':
/* If no destination completer and not before a completer
for fcmp, need a space here. */
if (s[1] == '?')
fputs_filtered
(float_format_names[GET_FIELD (insn, 20, 20)], info);
else
(*info->fprintf_func)
(info->stream, "%s ",
float_format_names[GET_FIELD (insn, 20, 20)]);
break;
case 'J':
fput_const (extract_14 (insn), info);
break;
case '#':
{
int sign = GET_FIELD (insn, 31, 31);
int imm10 = GET_FIELD (insn, 18, 27);
int disp;
if (sign)
disp = (-1 << 10) | imm10;
else
disp = imm10;
disp <<= 3;
fput_const (disp, info);
break;
}
case 'K':
case 'd':
{
int sign = GET_FIELD (insn, 31, 31);
int imm11 = GET_FIELD (insn, 18, 28);
int disp;
if (sign)
disp = (-1 << 11) | imm11;
else
disp = imm11;
disp <<= 2;
fput_const (disp, info);
break;
}
case '>':
case 'y':
{
/* 16-bit long disp., PA2.0 wide only. */
int disp = extract_16 (insn);
disp &= ~3;
fput_const (disp, info);
break;
}
case '&':
{
/* 16-bit long disp., PA2.0 wide only. */
int disp = extract_16 (insn);
disp &= ~7;
fput_const (disp, info);
break;
}
case '_':
break; /* Dealt with by '{' */
case '{':
{
int sub = GET_FIELD (insn, 14, 16);
int df = GET_FIELD (insn, 17, 18);
int sf = GET_FIELD (insn, 19, 20);
const char * const * source = float_format_names;
const char * const * dest = float_format_names;
const char *t = "";
if (sub == 4)
{
fputs_filtered (",UND ", info);
break;
}
if ((sub & 3) == 3)
t = ",t";
if ((sub & 3) == 1)
source = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
if (sub & 2)
dest = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
(*info->fprintf_func) (info->stream, "%s%s%s ",
t, source[sf], dest[df]);
break;
}
case 'm':
{
int y = GET_FIELD (insn, 16, 18);
if (y != 1)
fput_const ((y ^ 1) - 1, info);
}
break;
case 'h':
{
int cbit;
cbit = GET_FIELD (insn, 16, 18);
if (cbit > 0)
(*info->fprintf_func) (info->stream, ",%d", cbit - 1);
break;
}
case '=':
{
int cond = GET_FIELD (insn, 27, 31);
switch (cond)
{
case 0: fputs_filtered (" ", info); break;
case 1: fputs_filtered ("acc ", info); break;
case 2: fputs_filtered ("rej ", info); break;
case 5: fputs_filtered ("acc8 ", info); break;
case 6: fputs_filtered ("rej8 ", info); break;
case 9: fputs_filtered ("acc6 ", info); break;
case 13: fputs_filtered ("acc4 ", info); break;
case 17: fputs_filtered ("acc2 ", info); break;
default: break;
}
break;
}
case 'X':
(*info->print_address_func)
(memaddr + 8 + extract_22 (insn), info);
break;
case 'L':
fputs_filtered (",rp", info);
break;
default:
(*info->fprintf_func) (info->stream, "%c", *s);
break;
}
}
return sizeof (insn);
}
}
(*info->fprintf_func) (info->stream, "#%8x", insn);
return sizeof (insn);
}
diff --git a/disas/m68k.c b/disas/m68k.c
index 1f16e295ab..a755951bb7 100644
--- a/disas/m68k.c
+++ b/disas/m68k.c
@@ -1087,634 +1087,634 @@ static int
print_insn_arg (const char *d,
unsigned char *buffer,
unsigned char *p0,
bfd_vma addr,
disassemble_info *info)
{
int val = 0;
int place = d[1];
unsigned char *p = p0;
int regno;
const char *regname;
unsigned char *p1;
double flval;
int flt_p;
bfd_signed_vma disp;
unsigned int uval;
switch (*d)
{
case 'c': /* Cache identifier. */
{
static const char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" };
val = fetch_arg (buffer, place, 2, info);
(*info->fprintf_func) (info->stream, "%s", cacheFieldName[val]);
break;
}
case 'a': /* Address register indirect only. Cf. case '+'. */
{
(*info->fprintf_func)
(info->stream,
"%s@",
reg_names[fetch_arg (buffer, place, 3, info) + 8]);
break;
}
case '_': /* 32-bit absolute address for move16. */
{
uval = NEXTULONG (p);
(*info->print_address_func) (uval, info);
break;
}
case 'C':
(*info->fprintf_func) (info->stream, "%%ccr");
break;
case 'S':
(*info->fprintf_func) (info->stream, "%%sr");
break;
case 'U':
(*info->fprintf_func) (info->stream, "%%usp");
break;
case 'E':
(*info->fprintf_func) (info->stream, "%%acc");
break;
case 'G':
(*info->fprintf_func) (info->stream, "%%macsr");
break;
case 'H':
(*info->fprintf_func) (info->stream, "%%mask");
break;
case 'J':
{
/* FIXME: There's a problem here, different m68k processors call the
same address different names. This table can't get it right
because it doesn't know which processor it's disassembling for. */
static const struct { const char *name; int value; } names[]
= {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
{"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
{"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
{"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
{"%msp", 0x803}, {"%isp", 0x804},
{"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these. */
/* Should we be calling this psr like we do in case 'Y'? */
{"%mmusr",0x805},
{"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}};
val = fetch_arg (buffer, place, 12, info);
for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--)
if (names[regno].value == val)
{
(*info->fprintf_func) (info->stream, "%s", names[regno].name);
break;
}
if (regno < 0)
(*info->fprintf_func) (info->stream, "%d", val);
}
break;
case 'Q':
val = fetch_arg (buffer, place, 3, info);
/* 0 means 8, except for the bkpt instruction... */
if (val == 0 && d[1] != 's')
val = 8;
(*info->fprintf_func) (info->stream, "#%d", val);
break;
case 'x':
val = fetch_arg (buffer, place, 3, info);
/* 0 means -1. */
if (val == 0)
val = -1;
(*info->fprintf_func) (info->stream, "#%d", val);
break;
case 'M':
if (place == 'h')
{
static const char *const scalefactor_name[] = { "<<", ">>" };
val = fetch_arg (buffer, place, 1, info);
(*info->fprintf_func) (info->stream, "%s", scalefactor_name[val]);
}
else
{
val = fetch_arg (buffer, place, 8, info);
if (val & 0x80)
val = val - 0x100;
(*info->fprintf_func) (info->stream, "#%d", val);
}
break;
case 'T':
val = fetch_arg (buffer, place, 4, info);
(*info->fprintf_func) (info->stream, "#%d", val);
break;
case 'D':
(*info->fprintf_func) (info->stream, "%s",
reg_names[fetch_arg (buffer, place, 3, info)]);
break;
case 'A':
(*info->fprintf_func)
(info->stream, "%s",
reg_names[fetch_arg (buffer, place, 3, info) + 010]);
break;
case 'R':
(*info->fprintf_func)
(info->stream, "%s",
reg_names[fetch_arg (buffer, place, 4, info)]);
break;
case 'r':
regno = fetch_arg (buffer, place, 4, info);
if (regno > 7)
(*info->fprintf_func) (info->stream, "%s@", reg_names[regno]);
else
(*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]);
break;
case 'F':
(*info->fprintf_func)
(info->stream, "%%fp%d",
fetch_arg (buffer, place, 3, info));
break;
case 'O':
val = fetch_arg (buffer, place, 6, info);
if (val & 0x20)
(*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]);
else
(*info->fprintf_func) (info->stream, "%d", val);
break;
case '+':
(*info->fprintf_func)
(info->stream, "%s@+",
reg_names[fetch_arg (buffer, place, 3, info) + 8]);
break;
case '-':
(*info->fprintf_func)
(info->stream, "%s@-",
reg_names[fetch_arg (buffer, place, 3, info) + 8]);
break;
case 'k':
if (place == 'k')
(*info->fprintf_func)
(info->stream, "{%s}",
reg_names[fetch_arg (buffer, place, 3, info)]);
else if (place == 'C')
{
val = fetch_arg (buffer, place, 7, info);
if (val > 63) /* This is a signed constant. */
val -= 128;
(*info->fprintf_func) (info->stream, "{#%d}", val);
}
else
return -2;
break;
case '#':
case '^':
p1 = buffer + (*d == '#' ? 2 : 4);
if (place == 's')
val = fetch_arg (buffer, place, 4, info);
else if (place == 'C')
val = fetch_arg (buffer, place, 7, info);
else if (place == '8')
val = fetch_arg (buffer, place, 3, info);
else if (place == '3')
val = fetch_arg (buffer, place, 8, info);
else if (place == 'b')
val = NEXTBYTE (p1);
else if (place == 'w' || place == 'W')
val = NEXTWORD (p1);
else if (place == 'l')
val = NEXTLONG (p1);
else
return -2;
(*info->fprintf_func) (info->stream, "#%d", val);
break;
case 'B':
if (place == 'b')
disp = NEXTBYTE (p);
else if (place == 'B')
disp = COERCE_SIGNED_CHAR (buffer[1]);
else if (place == 'w' || place == 'W')
disp = NEXTWORD (p);
else if (place == 'l' || place == 'L' || place == 'C')
disp = NEXTLONG (p);
else if (place == 'g')
{
disp = NEXTBYTE (buffer);
if (disp == 0)
disp = NEXTWORD (p);
else if (disp == -1)
disp = NEXTLONG (p);
}
else if (place == 'c')
{
if (buffer[1] & 0x40) /* If bit six is one, long offset. */
disp = NEXTLONG (p);
else
disp = NEXTWORD (p);
}
else
return -2;
(*info->print_address_func) (addr + disp, info);
break;
case 'd':
val = NEXTWORD (p);
(*info->fprintf_func)
(info->stream, "%s@(%d)",
reg_names[fetch_arg (buffer, place, 3, info) + 8], val);
break;
case 's':
(*info->fprintf_func) (info->stream, "%s",
fpcr_names[fetch_arg (buffer, place, 3, info)]);
break;
case 'e':
val = fetch_arg(buffer, place, 2, info);
(*info->fprintf_func) (info->stream, "%%acc%d", val);
break;
case 'g':
val = fetch_arg(buffer, place, 1, info);
(*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23");
break;
case 'i':
val = fetch_arg(buffer, place, 2, info);
if (val == 1)
(*info->fprintf_func) (info->stream, "<<");
else if (val == 3)
(*info->fprintf_func) (info->stream, ">>");
else
return -1;
break;
case 'I':
/* Get coprocessor ID... */
val = fetch_arg (buffer, 'd', 3, info);
if (val != 1) /* Unusual coprocessor ID? */
(*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
break;
case '4':
case '*':
case '~':
case '%':
case ';':
case '@':
case '!':
case '$':
case '?':
case '/':
case '&':
case '|':
case '<':
case '>':
case 'm':
case 'n':
case 'o':
case 'p':
case 'q':
case 'v':
case 'b':
case 'w':
case 'y':
case 'z':
if (place == 'd')
{
val = fetch_arg (buffer, 'x', 6, info);
val = ((val & 7) << 3) + ((val >> 3) & 7);
}
else
val = fetch_arg (buffer, 's', 6, info);
/* If the <ea> is invalid for *d, then reject this match. */
if (!m68k_valid_ea (*d, val))
return -1;
/* Get register number assuming address register. */
regno = (val & 7) + 8;
regname = reg_names[regno];
switch (val >> 3)
{
case 0:
(*info->fprintf_func) (info->stream, "%s", reg_names[val]);
break;
case 1:
(*info->fprintf_func) (info->stream, "%s", regname);
break;
case 2:
(*info->fprintf_func) (info->stream, "%s@", regname);
break;
case 3:
(*info->fprintf_func) (info->stream, "%s@+", regname);
break;
case 4:
(*info->fprintf_func) (info->stream, "%s@-", regname);
break;
case 5:
val = NEXTWORD (p);
(*info->fprintf_func) (info->stream, "%s@(%d)", regname, val);
break;
case 6:
p = print_indexed (regno, p, addr, info);
break;
case 7:
switch (val & 7)
{
case 0:
val = NEXTWORD (p);
(*info->print_address_func) (val, info);
break;
case 1:
uval = NEXTULONG (p);
(*info->print_address_func) (uval, info);
break;
case 2:
val = NEXTWORD (p);
(*info->fprintf_func) (info->stream, "%%pc@(");
(*info->print_address_func) (addr + val, info);
(*info->fprintf_func) (info->stream, ")");
break;
case 3:
p = print_indexed (-1, p, addr, info);
break;
case 4:
flt_p = 1; /* Assume it's a float... */
switch (place)
{
case 'b':
val = NEXTBYTE (p);
flt_p = 0;
break;
case 'w':
val = NEXTWORD (p);
flt_p = 0;
break;
case 'l':
val = NEXTLONG (p);
flt_p = 0;
break;
case 'f':
NEXTSINGLE (flval, p);
break;
case 'F':
NEXTDOUBLE (flval, p);
break;
case 'x':
NEXTEXTEND (flval, p);
break;
case 'p':
flval = NEXTPACKED (p);
break;
default:
return -1;
}
if (flt_p) /* Print a float? */
(*info->fprintf_func) (info->stream, "#%g", flval);
else
(*info->fprintf_func) (info->stream, "#%d", val);
break;
default:
return -1;
}
}
/* If place is '/', then this is the case of the mask bit for
mac/emac loads. Now that the arg has been printed, grab the
mask bit and if set, add a '&' to the arg. */
if (place == '/')
{
val = fetch_arg (buffer, place, 1, info);
if (val)
info->fprintf_func (info->stream, "&");
}
break;
case 'L':
case 'l':
if (place == 'w')
{
char doneany;
p1 = buffer + 2;
val = NEXTWORD (p1);
/* Move the pointer ahead if this point is farther ahead
than the last. */
p = p1 > p ? p1 : p;
if (val == 0)
{
(*info->fprintf_func) (info->stream, "#0");
break;
}
if (*d == 'l')
{
int newval = 0;
for (regno = 0; regno < 16; ++regno)
if (val & (0x8000 >> regno))
newval |= 1 << regno;
val = newval;
}
val &= 0xffff;
doneany = 0;
for (regno = 0; regno < 16; ++regno)
if (val & (1 << regno))
{
int first_regno;
if (doneany)
(*info->fprintf_func) (info->stream, "/");
doneany = 1;
(*info->fprintf_func) (info->stream, "%s", reg_names[regno]);
first_regno = regno;
while (val & (1 << (regno + 1)))
++regno;
if (regno > first_regno)
(*info->fprintf_func) (info->stream, "-%s",
reg_names[regno]);
}
}
else if (place == '3')
{
/* `fmovem' insn. */
char doneany;
val = fetch_arg (buffer, place, 8, info);
if (val == 0)
{
(*info->fprintf_func) (info->stream, "#0");
break;
}
if (*d == 'l')
{
int newval = 0;
for (regno = 0; regno < 8; ++regno)
if (val & (0x80 >> regno))
newval |= 1 << regno;
val = newval;
}
val &= 0xff;
doneany = 0;
for (regno = 0; regno < 8; ++regno)
if (val & (1 << regno))
{
int first_regno;
if (doneany)
(*info->fprintf_func) (info->stream, "/");
doneany = 1;
(*info->fprintf_func) (info->stream, "%%fp%d", regno);
first_regno = regno;
while (val & (1 << (regno + 1)))
++regno;
if (regno > first_regno)
(*info->fprintf_func) (info->stream, "-%%fp%d", regno);
}
}
else if (place == '8')
{
/* fmoveml for FP status registers. */
(*info->fprintf_func) (info->stream, "%s",
fpcr_names[fetch_arg (buffer, place, 3,
info)]);
}
else
return -2;
break;
case 'X':
place = '8';
- /* fall through */
+ fallthrough;
case 'Y':
case 'Z':
case 'W':
case '0':
case '1':
case '2':
case '3':
{
int reg = fetch_arg (buffer, place, 5, info);
const char *name = 0;
switch (reg)
{
case 2: name = "%tt0"; break;
case 3: name = "%tt1"; break;
case 0x10: name = "%tc"; break;
case 0x11: name = "%drp"; break;
case 0x12: name = "%srp"; break;
case 0x13: name = "%crp"; break;
case 0x14: name = "%cal"; break;
case 0x15: name = "%val"; break;
case 0x16: name = "%scc"; break;
case 0x17: name = "%ac"; break;
case 0x18: name = "%psr"; break;
case 0x19: name = "%pcsr"; break;
case 0x1c:
case 0x1d:
{
int break_reg = ((buffer[3] >> 2) & 7);
(*info->fprintf_func)
(info->stream, reg == 0x1c ? "%%bad%d" : "%%bac%d",
break_reg);
}
break;
default:
(*info->fprintf_func) (info->stream, "<mmu register %d>", reg);
}
if (name)
(*info->fprintf_func) (info->stream, "%s", name);
}
break;
case 'f':
{
int fc = fetch_arg (buffer, place, 5, info);
if (fc == 1)
(*info->fprintf_func) (info->stream, "%%dfc");
else if (fc == 0)
(*info->fprintf_func) (info->stream, "%%sfc");
else
/* xgettext:c-format */
(*info->fprintf_func) (info->stream, "<function code %d>", fc);
}
break;
case 'V':
(*info->fprintf_func) (info->stream, "%%val");
break;
case 't':
{
int level = fetch_arg (buffer, place, 3, info);
(*info->fprintf_func) (info->stream, "%d", level);
}
break;
case 'u':
{
short is_upper = 0;
int reg = fetch_arg (buffer, place, 5, info);
if (reg & 0x10)
{
is_upper = 1;
reg &= 0xf;
}
(*info->fprintf_func) (info->stream, "%s%s",
reg_half_names[reg],
is_upper ? "u" : "l");
}
break;
default:
return -2;
}
return p - p0;
}
/* Try to match the current instruction to best and if so, return the
number of bytes consumed from the instruction stream, else zero. */
diff --git a/disas/sh4.c b/disas/sh4.c
index dcdbdf26d8..3c51fd707d 100644
--- a/disas/sh4.c
+++ b/disas/sh4.c
@@ -1509,565 +1509,567 @@ int
print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
{
fprintf_function fprintf_fn = info->fprintf_func;
void *stream = info->stream;
unsigned char insn[4];
unsigned char nibs[8];
int status;
bfd_vma relmask = ~(bfd_vma) 0;
const sh_opcode_info *op;
unsigned int target_arch;
int allow_op32;
switch (info->mach)
{
case bfd_mach_sh:
target_arch = arch_sh1;
break;
case bfd_mach_sh4:
target_arch = arch_sh4;
break;
case bfd_mach_sh5:
#ifdef INCLUDE_SHMEDIA
status = print_insn_sh64 (memaddr, info);
if (status != -2)
return status;
#endif
/* When we get here for sh64, it's because we want to disassemble
SHcompact, i.e. arch_sh4. */
target_arch = arch_sh4;
break;
default:
fprintf (stderr, "sh architecture not supported\n");
return -1;
}
status = info->read_memory_func (memaddr, insn, 2, info);
if (status != 0)
{
info->memory_error_func (status, memaddr, info);
return -1;
}
if (info->endian == BFD_ENDIAN_LITTLE)
{
nibs[0] = (insn[1] >> 4) & 0xf;
nibs[1] = insn[1] & 0xf;
nibs[2] = (insn[0] >> 4) & 0xf;
nibs[3] = insn[0] & 0xf;
}
else
{
nibs[0] = (insn[0] >> 4) & 0xf;
nibs[1] = insn[0] & 0xf;
nibs[2] = (insn[1] >> 4) & 0xf;
nibs[3] = insn[1] & 0xf;
}
status = info->read_memory_func (memaddr + 2, insn + 2, 2, info);
if (status != 0)
allow_op32 = 0;
else
{
allow_op32 = 1;
if (info->endian == BFD_ENDIAN_LITTLE)
{
nibs[4] = (insn[3] >> 4) & 0xf;
nibs[5] = insn[3] & 0xf;
nibs[6] = (insn[2] >> 4) & 0xf;
nibs[7] = insn[2] & 0xf;
}
else
{
nibs[4] = (insn[2] >> 4) & 0xf;
nibs[5] = insn[2] & 0xf;
nibs[6] = (insn[3] >> 4) & 0xf;
nibs[7] = insn[3] & 0xf;
}
}
if (nibs[0] == 0xf && (nibs[1] & 4) == 0
&& SH_MERGE_ARCH_SET_VALID (target_arch, arch_sh_dsp_up))
{
if (nibs[1] & 8)
{
int field_b;
status = info->read_memory_func (memaddr + 2, insn, 2, info);
if (status != 0)
{
info->memory_error_func (status, memaddr + 2, info);
return -1;
}
if (info->endian == BFD_ENDIAN_LITTLE)
field_b = insn[1] << 8 | insn[0];
else
field_b = insn[0] << 8 | insn[1];
print_insn_ppi (field_b, info);
print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
return 4;
}
print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
return 2;
}
for (op = sh_table; op->name; op++)
{
int n;
int imm = 0;
int rn = 0;
int rm = 0;
int rb = 0;
int disp_pc;
bfd_vma disp_pc_addr = 0;
int disp = 0;
int has_disp = 0;
int max_n = SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 8 : 4;
if (!allow_op32
&& SH_MERGE_ARCH_SET (op->arch, arch_op32))
goto fail;
if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch))
goto fail;
for (n = 0; n < max_n; n++)
{
int i = op->nibbles[n];
if (i < 16)
{
if (nibs[n] == i)
continue;
goto fail;
}
switch (i)
{
case BRANCH_8:
imm = (nibs[2] << 4) | (nibs[3]);
if (imm & 0x80)
imm |= ~0xff;
imm = ((char) imm) * 2 + 4;
goto ok;
case BRANCH_12:
imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
if (imm & 0x800)
imm |= ~0xfff;
imm = imm * 2 + 4;
goto ok;
case IMM0_3c:
if (nibs[3] & 0x8)
goto fail;
imm = nibs[3] & 0x7;
break;
case IMM0_3s:
if (!(nibs[3] & 0x8))
goto fail;
imm = nibs[3] & 0x7;
break;
case IMM0_3Uc:
if (nibs[2] & 0x8)
goto fail;
imm = nibs[2] & 0x7;
break;
case IMM0_3Us:
if (!(nibs[2] & 0x8))
goto fail;
imm = nibs[2] & 0x7;
break;
case DISP0_12:
case DISP1_12:
disp = (nibs[5] << 8) | (nibs[6] << 4) | nibs[7];
has_disp = 1;
goto ok;
case DISP0_12BY2:
case DISP1_12BY2:
disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 1;
relmask = ~(bfd_vma) 1;
has_disp = 1;
goto ok;
case DISP0_12BY4:
case DISP1_12BY4:
disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 2;
relmask = ~(bfd_vma) 3;
has_disp = 1;
goto ok;
case DISP0_12BY8:
case DISP1_12BY8:
disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 3;
relmask = ~(bfd_vma) 7;
has_disp = 1;
goto ok;
case IMM0_20_4:
break;
case IMM0_20:
imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
| (nibs[6] << 4) | nibs[7]);
if (imm & 0x80000)
imm -= 0x100000;
goto ok;
case IMM0_20BY8:
imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
| (nibs[6] << 4) | nibs[7]);
imm <<= 8;
if (imm & 0x8000000)
imm -= 0x10000000;
goto ok;
case IMM0_4:
case IMM1_4:
imm = nibs[3];
goto ok;
case IMM0_4BY2:
case IMM1_4BY2:
imm = nibs[3] << 1;
goto ok;
case IMM0_4BY4:
case IMM1_4BY4:
imm = nibs[3] << 2;
goto ok;
case IMM0_8:
case IMM1_8:
imm = (nibs[2] << 4) | nibs[3];
disp = imm;
has_disp = 1;
if (imm & 0x80)
imm -= 0x100;
goto ok;
case PCRELIMM_8BY2:
imm = ((nibs[2] << 4) | nibs[3]) << 1;
relmask = ~(bfd_vma) 1;
goto ok;
case PCRELIMM_8BY4:
imm = ((nibs[2] << 4) | nibs[3]) << 2;
relmask = ~(bfd_vma) 3;
goto ok;
case IMM0_8BY2:
case IMM1_8BY2:
imm = ((nibs[2] << 4) | nibs[3]) << 1;
goto ok;
case IMM0_8BY4:
case IMM1_8BY4:
imm = ((nibs[2] << 4) | nibs[3]) << 2;
goto ok;
case REG_N_D:
if ((nibs[n] & 1) != 0)
goto fail;
- /* fall through */
+ fallthrough;
case REG_N:
rn = nibs[n];
break;
case REG_M:
rm = nibs[n];
break;
case REG_N_B01:
if ((nibs[n] & 0x3) != 1 /* binary 01 */)
goto fail;
rn = (nibs[n] & 0xc) >> 2;
break;
case REG_NM:
rn = (nibs[n] & 0xc) >> 2;
rm = (nibs[n] & 0x3);
break;
case REG_B:
rb = nibs[n] & 0x07;
break;
case SDT_REG_N:
/* sh-dsp: single data transfer. */
rn = nibs[n];
if ((rn & 0xc) != 4)
goto fail;
rn = rn & 0x3;
rn |= (!(rn & 2)) << 2;
break;
case PPI:
case REPEAT:
goto fail;
default:
abort ();
}
}
ok:
/* sh2a has D_REG but not X_REG. We don't know the pattern
doesn't match unless we check the output args to see if they
make sense. */
if (target_arch == arch_sh2a
&& ((op->arg[0] == DX_REG_M && (rm & 1) != 0)
|| (op->arg[1] == DX_REG_N && (rn & 1) != 0)))
goto fail;
fprintf_fn (stream, "%s\t", op->name);
disp_pc = 0;
for (n = 0; n < 3 && op->arg[n] != A_END; n++)
{
if (n && op->arg[1] != A_END)
fprintf_fn (stream, ",");
switch (op->arg[n])
{
case A_IMM:
fprintf_fn (stream, "#%d", imm);
break;
case A_R0:
fprintf_fn (stream, "r0");
break;
case A_REG_N:
fprintf_fn (stream, "r%d", rn);
break;
case A_INC_N:
case AS_INC_N:
fprintf_fn (stream, "@r%d+", rn);
break;
case A_DEC_N:
case AS_DEC_N:
fprintf_fn (stream, "@-r%d", rn);
break;
case A_IND_N:
case AS_IND_N:
fprintf_fn (stream, "@r%d", rn);
break;
case A_DISP_REG_N:
fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rn);
break;
case AS_PMOD_N:
fprintf_fn (stream, "@r%d+r8", rn);
break;
case A_REG_M:
fprintf_fn (stream, "r%d", rm);
break;
case A_INC_M:
fprintf_fn (stream, "@r%d+", rm);
break;
case A_DEC_M:
fprintf_fn (stream, "@-r%d", rm);
break;
case A_IND_M:
fprintf_fn (stream, "@r%d", rm);
break;
case A_DISP_REG_M:
fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rm);
break;
case A_REG_B:
fprintf_fn (stream, "r%d_bank", rb);
break;
case A_DISP_PC:
disp_pc = 1;
disp_pc_addr = imm + 4 + (memaddr & relmask);
(*info->print_address_func) (disp_pc_addr, info);
break;
case A_IND_R0_REG_N:
fprintf_fn (stream, "@(r0,r%d)", rn);
break;
case A_IND_R0_REG_M:
fprintf_fn (stream, "@(r0,r%d)", rm);
break;
case A_DISP_GBR:
fprintf_fn (stream, "@(%d,gbr)", has_disp?disp:imm);
break;
case A_TBR:
fprintf_fn (stream, "tbr");
break;
case A_DISP2_TBR:
fprintf_fn (stream, "@@(%d,tbr)", has_disp?disp:imm);
break;
case A_INC_R15:
fprintf_fn (stream, "@r15+");
break;
case A_DEC_R15:
fprintf_fn (stream, "@-r15");
break;
case A_R0_GBR:
fprintf_fn (stream, "@(r0,gbr)");
break;
case A_BDISP12:
case A_BDISP8:
{
bfd_vma addr;
addr = imm + memaddr;
(*info->print_address_func) (addr, info);
}
break;
case A_SR:
fprintf_fn (stream, "sr");
break;
case A_GBR:
fprintf_fn (stream, "gbr");
break;
case A_VBR:
fprintf_fn (stream, "vbr");
break;
case A_DSR:
fprintf_fn (stream, "dsr");
break;
case A_MOD:
fprintf_fn (stream, "mod");
break;
case A_RE:
fprintf_fn (stream, "re");
break;
case A_RS:
fprintf_fn (stream, "rs");
break;
case A_A0:
fprintf_fn (stream, "a0");
break;
case A_X0:
fprintf_fn (stream, "x0");
break;
case A_X1:
fprintf_fn (stream, "x1");
break;
case A_Y0:
fprintf_fn (stream, "y0");
break;
case A_Y1:
fprintf_fn (stream, "y1");
break;
case DSP_REG_M:
print_dsp_reg (rm, fprintf_fn, stream);
break;
case A_SSR:
fprintf_fn (stream, "ssr");
break;
case A_SPC:
fprintf_fn (stream, "spc");
break;
case A_MACH:
fprintf_fn (stream, "mach");
break;
case A_MACL:
fprintf_fn (stream, "macl");
break;
case A_PR:
fprintf_fn (stream, "pr");
break;
case A_SGR:
fprintf_fn (stream, "sgr");
break;
case A_DBR:
fprintf_fn (stream, "dbr");
break;
case F_REG_N:
fprintf_fn (stream, "fr%d", rn);
break;
case F_REG_M:
fprintf_fn (stream, "fr%d", rm);
break;
case DX_REG_N:
if (rn & 1)
{
fprintf_fn (stream, "xd%d", rn & ~1);
break;
}
/* fallthrough */
+ fallthrough;
case D_REG_N:
fprintf_fn (stream, "dr%d", rn);
break;
case DX_REG_M:
if (rm & 1)
{
fprintf_fn (stream, "xd%d", rm & ~1);
break;
}
/* fallthrough */
+ fallthrough;
case D_REG_M:
fprintf_fn (stream, "dr%d", rm);
break;
case FPSCR_M:
case FPSCR_N:
fprintf_fn (stream, "fpscr");
break;
case FPUL_M:
case FPUL_N:
fprintf_fn (stream, "fpul");
break;
case F_FR0:
fprintf_fn (stream, "fr0");
break;
case V_REG_N:
fprintf_fn (stream, "fv%d", rn * 4);
break;
case V_REG_M:
fprintf_fn (stream, "fv%d", rm * 4);
break;
case XMTRX_M4:
fprintf_fn (stream, "xmtrx");
break;
default:
abort ();
}
}
#if 0
/* This code prints instructions in delay slots on the same line
as the instruction which needs the delay slots. This can be
confusing, since other disassembler don't work this way, and
it means that the instructions are not all in a line. So I
disabled it. Ian. */
if (!(info->flags & 1)
&& (op->name[0] == 'j'
|| (op->name[0] == 'b'
&& (op->name[1] == 'r'
|| op->name[1] == 's'))
|| (op->name[0] == 'r' && op->name[1] == 't')
|| (op->name[0] == 'b' && op->name[2] == '.')))
{
info->flags |= 1;
fprintf_fn (stream, "\t(slot ");
print_insn_sh (memaddr + 2, info);
info->flags &= ~1;
fprintf_fn (stream, ")");
return 4;
}
#endif
if (disp_pc && strcmp (op->name, "mova") != 0)
{
int size;
bfd_byte bytes[4];
if (relmask == ~(bfd_vma) 1)
size = 2;
else
size = 4;
status = info->read_memory_func (disp_pc_addr, bytes, size, info);
if (status == 0)
{
unsigned int val;
if (size == 2)
{
if (info->endian == BFD_ENDIAN_LITTLE)
val = bfd_getl16 (bytes);
else
val = bfd_getb16 (bytes);
}
else
{
if (info->endian == BFD_ENDIAN_LITTLE)
val = bfd_getl32 (bytes);
else
val = bfd_getb32 (bytes);
}
if ((*info->symbol_at_address_func) (val, info))
{
fprintf_fn (stream, "\t! ");
(*info->print_address_func) (val, info);
}
else
fprintf_fn (stream, "\t! 0x%x", val);
}
}
return SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 4 : 2;
fail:
;
}
fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
return 2;
}
diff --git a/disas/sparc.c b/disas/sparc.c
index 5689533ce1..61139256b0 100644
--- a/disas/sparc.c
+++ b/disas/sparc.c
@@ -2667,570 +2667,570 @@ int
print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
{
FILE *stream = info->stream;
bfd_byte buffer[4];
unsigned long insn;
sparc_opcode_hash *op;
/* Nonzero of opcode table has been initialized. */
static int opcodes_initialized = 0;
/* bfd mach number of last call. */
static unsigned long current_mach = 0;
bfd_vma (*getword) (const unsigned char *);
if (!opcodes_initialized
|| info->mach != current_mach)
{
int i;
current_arch_mask = compute_arch_mask (info->mach);
if (!opcodes_initialized)
sorted_opcodes =
malloc (sparc_num_opcodes * sizeof (sparc_opcode *));
/* Reset the sorted table so we can resort it. */
for (i = 0; i < sparc_num_opcodes; ++i)
sorted_opcodes[i] = &sparc_opcodes[i];
qsort ((char *) sorted_opcodes, sparc_num_opcodes,
sizeof (sorted_opcodes[0]), compare_opcodes);
build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
current_mach = info->mach;
opcodes_initialized = 1;
}
{
int status =
(*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
}
/* On SPARClite variants such as DANlite (sparc86x), instructions
are always big-endian even when the machine is in little-endian mode. */
if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
getword = bfd_getb32;
else
getword = bfd_getl32;
insn = getword (buffer);
info->insn_info_valid = 1; /* We do return this info. */
info->insn_type = dis_nonbranch; /* Assume non branch insn. */
info->branch_delay_insns = 0; /* Assume no delay. */
info->target = 0; /* Assume no target known. */
for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
{
const sparc_opcode *opcode = op->opcode;
/* If the insn isn't supported by the current architecture, skip it. */
if (! (opcode->architecture & current_arch_mask))
continue;
if ((opcode->match & insn) == opcode->match
&& (opcode->lose & insn) == 0)
{
/* Nonzero means that we have found an instruction which has
the effect of adding or or'ing the imm13 field to rs1. */
int imm_added_to_rs1 = 0;
int imm_ored_to_rs1 = 0;
/* Nonzero means that we have found a plus sign in the args
field of the opcode table. */
int found_plus = 0;
/* Nonzero means we have an annulled branch. */
/* int is_annulled = 0; */ /* see FIXME below */
/* Do we have an `add' or `or' instruction combining an
immediate with rs1? */
if (opcode->match == 0x80102000) /* or */
imm_ored_to_rs1 = 1;
if (opcode->match == 0x80002000) /* add */
imm_added_to_rs1 = 1;
if (X_RS1 (insn) != X_RD (insn)
&& strchr (opcode->args, 'r') != NULL)
/* Can't do simple format if source and dest are different. */
continue;
if (X_RS2 (insn) != X_RD (insn)
&& strchr (opcode->args, 'O') != NULL)
/* Can't do simple format if source and dest are different. */
continue;
(*info->fprintf_func) (stream, "%s", opcode->name);
{
const char *s;
if (opcode->args[0] != ',')
(*info->fprintf_func) (stream, " ");
for (s = opcode->args; *s != '\0'; ++s)
{
while (*s == ',')
{
(*info->fprintf_func) (stream, ",");
++s;
switch (*s)
{
case 'a':
(*info->fprintf_func) (stream, "a");
/* is_annulled = 1; */ /* see FIXME below */
++s;
continue;
case 'N':
(*info->fprintf_func) (stream, "pn");
++s;
continue;
case 'T':
(*info->fprintf_func) (stream, "pt");
++s;
continue;
default:
break;
}
}
(*info->fprintf_func) (stream, " ");
switch (*s)
{
case '+':
found_plus = 1;
- /* Fall through. */
+ fallthrough;
default:
(*info->fprintf_func) (stream, "%c", *s);
break;
case '#':
(*info->fprintf_func) (stream, "0");
break;
#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
case '1':
case 'r':
reg (X_RS1 (insn));
break;
case '2':
case 'O':
reg (X_RS2 (insn));
break;
case 'd':
reg (X_RD (insn));
break;
#undef reg
#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
case 'e':
freg (X_RS1 (insn));
break;
case 'v': /* Double/even. */
case 'V': /* Quad/multiple of 4. */
fregx (X_RS1 (insn));
break;
case 'f':
freg (X_RS2 (insn));
break;
case 'B': /* Double/even. */
case 'R': /* Quad/multiple of 4. */
fregx (X_RS2 (insn));
break;
case 'g':
freg (X_RD (insn));
break;
case 'H': /* Double/even. */
case 'J': /* Quad/multiple of 4. */
fregx (X_RD (insn));
break;
#undef freg
#undef fregx
#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
case 'b':
creg (X_RS1 (insn));
break;
case 'c':
creg (X_RS2 (insn));
break;
case 'D':
creg (X_RD (insn));
break;
#undef creg
case 'h':
(*info->fprintf_func) (stream, "%%hi(%#x)",
((unsigned) 0xFFFFFFFF
& ((int) X_IMM22 (insn) << 10)));
break;
case 'i': /* 13 bit immediate. */
case 'I': /* 11 bit immediate. */
case 'j': /* 10 bit immediate. */
{
int imm;
if (*s == 'i')
imm = X_SIMM (insn, 13);
else if (*s == 'I')
imm = X_SIMM (insn, 11);
else
imm = X_SIMM (insn, 10);
/* Check to see whether we have a 1+i, and take
note of that fact.
Note: because of the way we sort the table,
we will be matching 1+i rather than i+1,
so it is OK to assume that i is after +,
not before it. */
if (found_plus)
imm_added_to_rs1 = 1;
if (imm <= 9)
(*info->fprintf_func) (stream, "%d", imm);
else
(*info->fprintf_func) (stream, "%#x", imm);
}
break;
case 'X': /* 5 bit unsigned immediate. */
case 'Y': /* 6 bit unsigned immediate. */
{
int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
if (imm <= 9)
(info->fprintf_func) (stream, "%d", imm);
else
(info->fprintf_func) (stream, "%#x", (unsigned) imm);
}
break;
case '3':
(info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
break;
case 'K':
{
int mask = X_MEMBAR (insn);
int bit = 0x40, printed_one = 0;
const char *name;
if (mask == 0)
(info->fprintf_func) (stream, "0");
else
while (bit)
{
if (mask & bit)
{
if (printed_one)
(info->fprintf_func) (stream, "|");
name = sparc_decode_membar (bit);
(info->fprintf_func) (stream, "%s", name);
printed_one = 1;
}
bit >>= 1;
}
break;
}
case 'k':
info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
(*info->print_address_func) (info->target, info);
break;
case 'G':
info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
(*info->print_address_func) (info->target, info);
break;
case '6':
case '7':
case '8':
case '9':
(*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
break;
case 'z':
(*info->fprintf_func) (stream, "%%icc");
break;
case 'Z':
(*info->fprintf_func) (stream, "%%xcc");
break;
case 'E':
(*info->fprintf_func) (stream, "%%ccr");
break;
case 's':
(*info->fprintf_func) (stream, "%%fprs");
break;
case 'o':
(*info->fprintf_func) (stream, "%%asi");
break;
case 'W':
(*info->fprintf_func) (stream, "%%tick");
break;
case 'P':
(*info->fprintf_func) (stream, "%%pc");
break;
case '?':
if (X_RS1 (insn) == 31)
(*info->fprintf_func) (stream, "%%ver");
else if ((unsigned) X_RS1 (insn) < 17)
(*info->fprintf_func) (stream, "%%%s",
v9_priv_reg_names[X_RS1 (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
case '!':
if ((unsigned) X_RD (insn) < 17)
(*info->fprintf_func) (stream, "%%%s",
v9_priv_reg_names[X_RD (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
case '$':
if ((unsigned) X_RS1 (insn) < 32)
(*info->fprintf_func) (stream, "%%%s",
v9_hpriv_reg_names[X_RS1 (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
case '%':
if ((unsigned) X_RD (insn) < 32)
(*info->fprintf_func) (stream, "%%%s",
v9_hpriv_reg_names[X_RD (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
case '/':
if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
(*info->fprintf_func) (stream, "%%reserved");
else
(*info->fprintf_func) (stream, "%%%s",
v9a_asr_reg_names[X_RS1 (insn)-16]);
break;
case '_':
if (X_RD (insn) < 16 || X_RD (insn) > 25)
(*info->fprintf_func) (stream, "%%reserved");
else
(*info->fprintf_func) (stream, "%%%s",
v9a_asr_reg_names[X_RD (insn)-16]);
break;
case '*':
{
const char *name = sparc_decode_prefetch (X_RD (insn));
if (name)
(*info->fprintf_func) (stream, "%s", name);
else
(*info->fprintf_func) (stream, "%ld", X_RD (insn));
break;
}
case 'M':
(*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
break;
case 'm':
(*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
break;
case 'L':
info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
(*info->print_address_func) (info->target, info);
break;
case 'n':
(*info->fprintf_func)
(stream, "%#x", SEX (X_DISP22 (insn), 22));
break;
case 'l':
info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
(*info->print_address_func) (info->target, info);
break;
case 'A':
{
const char *name;
if ((info->mach == bfd_mach_sparc_v8plusa) ||
((info->mach >= bfd_mach_sparc_v9) &&
(info->mach <= bfd_mach_sparc_v9b)))
name = sparc_decode_asi_v9 (X_ASI (insn));
else
name = sparc_decode_asi_v8 (X_ASI (insn));
if (name)
(*info->fprintf_func) (stream, "%s", name);
else
(*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
break;
}
case 'C':
(*info->fprintf_func) (stream, "%%csr");
break;
case 'F':
(*info->fprintf_func) (stream, "%%fsr");
break;
case 'p':
(*info->fprintf_func) (stream, "%%psr");
break;
case 'q':
(*info->fprintf_func) (stream, "%%fq");
break;
case 'Q':
(*info->fprintf_func) (stream, "%%cq");
break;
case 't':
(*info->fprintf_func) (stream, "%%tbr");
break;
case 'w':
(*info->fprintf_func) (stream, "%%wim");
break;
case 'x':
(*info->fprintf_func) (stream, "%ld",
((X_LDST_I (insn) << 8)
+ X_ASI (insn)));
break;
case 'y':
(*info->fprintf_func) (stream, "%%y");
break;
case 'u':
case 'U':
{
int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
const char *name = sparc_decode_sparclet_cpreg (val);
if (name)
(*info->fprintf_func) (stream, "%s", name);
else
(*info->fprintf_func) (stream, "%%cpreg(%d)", val);
break;
}
}
}
}
/* If we are adding or or'ing something to rs1, then
check to see whether the previous instruction was
a sethi to the same register as in the sethi.
If so, attempt to print the result of the add or
or (in this context add and or do the same thing)
and its symbolic value. */
if (imm_ored_to_rs1 || imm_added_to_rs1)
{
unsigned long prev_insn;
int errcode;
if (memaddr >= 4)
errcode =
(*info->read_memory_func)
(memaddr - 4, buffer, sizeof (buffer), info);
else
errcode = 1;
prev_insn = getword (buffer);
if (errcode == 0)
{
/* If it is a delayed branch, we need to look at the
instruction before the delayed branch. This handles
sequences such as:
sethi %o1, %hi(_foo), %o1
call _printf
or %o1, %lo(_foo), %o1 */
if (is_delayed_branch (prev_insn))
{
if (memaddr >= 8)
errcode = (*info->read_memory_func)
(memaddr - 8, buffer, sizeof (buffer), info);
else
errcode = 1;
prev_insn = getword (buffer);
}
}
/* If there was a problem reading memory, then assume
the previous instruction was not sethi. */
if (errcode == 0)
{
/* Is it sethi to the same register? */
if ((prev_insn & 0xc1c00000) == 0x01000000
&& X_RD (prev_insn) == X_RS1 (insn))
{
(*info->fprintf_func) (stream, "\t! ");
info->target =
((unsigned) 0xFFFFFFFF
& ((int) X_IMM22 (prev_insn) << 10));
if (imm_added_to_rs1)
info->target += X_SIMM (insn, 13);
else
info->target |= X_SIMM (insn, 13);
(*info->print_address_func) (info->target, info);
info->insn_type = dis_dref;
info->data_size = 4; /* FIXME!!! */
}
}
}
if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
{
/* FIXME -- check is_annulled flag. */
if (opcode->flags & F_UNBR)
info->insn_type = dis_branch;
if (opcode->flags & F_CONDBR)
info->insn_type = dis_condbranch;
if (opcode->flags & F_JSR)
info->insn_type = dis_jsr;
if (opcode->flags & F_DELAYED)
info->branch_delay_insns = 1;
}
return sizeof (buffer);
}
}
info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
(*info->fprintf_func) (stream, ".long %#08lx", insn);
return sizeof (buffer);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 46/75] contrib/rdmacm-mux: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (8 preceding siblings ...)
2023-10-13 7:47 ` [RFC PATCH 45/75] disas: " Emmanouil Pitsidianakis
@ 2023-10-13 7:47 ` Emmanouil Pitsidianakis
2023-10-13 7:48 ` [RFC PATCH 47/75] contrib/vhost-user-scsi: " Emmanouil Pitsidianakis
` (9 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:47 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block
Cc: Emmanouil Pitsidianakis, Yuval Shaia, Marcel Apfelbaum
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
contrib/rdmacm-mux/main.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/contrib/rdmacm-mux/main.c b/contrib/rdmacm-mux/main.c
index 771ca01e03..dda6917d58 100644
--- a/contrib/rdmacm-mux/main.c
+++ b/contrib/rdmacm-mux/main.c
@@ -303,72 +303,72 @@ static void hash_tbl_remove_fd_ifid_pair(int fd)
static int get_fd(const char *mad, int umad_len, int *fd, __be64 *gid_ifid)
{
struct umad_hdr *hdr = (struct umad_hdr *)mad;
char *data = (char *)hdr + sizeof(*hdr);
int32_t comm_id = 0;
uint16_t attr_id = be16toh(hdr->attr_id);
int rc = 0;
if (umad_len <= sizeof(*hdr)) {
rc = -EINVAL;
syslog(LOG_DEBUG, "Ignoring MAD packets with header only\n");
goto out;
}
switch (attr_id) {
case UMAD_CM_ATTR_REQ:
if (unlikely(umad_len < sizeof(*hdr) + CM_REQ_DGID_POS +
sizeof(*gid_ifid))) {
rc = -EINVAL;
syslog(LOG_WARNING,
"Invalid MAD packet size (%d) for attr_id 0x%x\n", umad_len,
attr_id);
goto out;
}
memcpy(gid_ifid, data + CM_REQ_DGID_POS, sizeof(*gid_ifid));
rc = hash_tbl_search_fd_by_ifid(fd, gid_ifid);
break;
case UMAD_CM_ATTR_SIDR_REQ:
if (unlikely(umad_len < sizeof(*hdr) + CM_SIDR_REQ_DGID_POS +
sizeof(*gid_ifid))) {
rc = -EINVAL;
syslog(LOG_WARNING,
"Invalid MAD packet size (%d) for attr_id 0x%x\n", umad_len,
attr_id);
goto out;
}
memcpy(gid_ifid, data + CM_SIDR_REQ_DGID_POS, sizeof(*gid_ifid));
rc = hash_tbl_search_fd_by_ifid(fd, gid_ifid);
break;
case UMAD_CM_ATTR_REP:
- /* Fall through */
+ fallthrough;
case UMAD_CM_ATTR_REJ:
- /* Fall through */
+ fallthrough;
case UMAD_CM_ATTR_DREQ:
- /* Fall through */
+ fallthrough;
case UMAD_CM_ATTR_DREP:
- /* Fall through */
+ fallthrough;
case UMAD_CM_ATTR_RTU:
data += sizeof(comm_id);
- /* Fall through */
+ fallthrough;
case UMAD_CM_ATTR_SIDR_REP:
if (unlikely(umad_len < sizeof(*hdr) + sizeof(comm_id))) {
rc = -EINVAL;
syslog(LOG_WARNING,
"Invalid MAD packet size (%d) for attr_id 0x%x\n", umad_len,
attr_id);
goto out;
}
memcpy(&comm_id, data, sizeof(comm_id));
if (comm_id) {
rc = hash_tbl_search_fd_by_comm_id(comm_id, fd, gid_ifid);
}
break;
default:
rc = -EINVAL;
syslog(LOG_WARNING, "Unsupported attr_id 0x%x\n", attr_id);
}
syslog(LOG_DEBUG, "mad_to_vm: %d 0x%x 0x%x\n", *fd, attr_id, comm_id);
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 47/75] contrib/vhost-user-scsi: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (9 preceding siblings ...)
2023-10-13 7:47 ` [RFC PATCH 46/75] contrib/rdmacm-mux: " Emmanouil Pitsidianakis
@ 2023-10-13 7:48 ` Emmanouil Pitsidianakis
2023-10-23 9:31 ` Raphael Norwitz
2023-10-13 7:48 ` [RFC PATCH 48/75] hw/arm: " Emmanouil Pitsidianakis
` (8 subsequent siblings)
19 siblings, 1 reply; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block
Cc: Emmanouil Pitsidianakis, Michael S. Tsirkin, Raphael Norwitz
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
contrib/vhost-user-scsi/vhost-user-scsi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/contrib/vhost-user-scsi/vhost-user-scsi.c b/contrib/vhost-user-scsi/vhost-user-scsi.c
index 9ef61cf5a7..71076f579b 100644
--- a/contrib/vhost-user-scsi/vhost-user-scsi.c
+++ b/contrib/vhost-user-scsi/vhost-user-scsi.c
@@ -109,14 +109,15 @@ static struct scsi_task *scsi_task_new(int cdb_len, uint8_t *cdb, int dir,
static int get_cdb_len(uint8_t *cdb)
{
assert(cdb);
switch (cdb[0] >> 5) {
case 0: return 6;
- case 1: /* fall through */
+ case 1:
+ fallthrough;
case 2: return 10;
case 4: return 16;
case 5: return 12;
}
g_warning("Unable to determine cdb len (0x%02hhX)", (uint8_t)(cdb[0] >> 5));
return -1;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [RFC PATCH 47/75] contrib/vhost-user-scsi: add fallthrough pseudo-keyword
2023-10-13 7:48 ` [RFC PATCH 47/75] contrib/vhost-user-scsi: " Emmanouil Pitsidianakis
@ 2023-10-23 9:31 ` Raphael Norwitz
0 siblings, 0 replies; 22+ messages in thread
From: Raphael Norwitz @ 2023-10-23 9:31 UTC (permalink / raw)
To: Emmanouil Pitsidianakis
Cc: open list:All patches CC here, qemu-arm@nongnu.org,
qemu-block@nongnu.org, Michael S. Tsirkin
> On Oct 13, 2023, at 3:48 AM, Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org> wrote:
>
> Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
> ---
> contrib/vhost-user-scsi/vhost-user-scsi.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/contrib/vhost-user-scsi/vhost-user-scsi.c b/contrib/vhost-user-scsi/vhost-user-scsi.c
> index 9ef61cf5a7..71076f579b 100644
> --- a/contrib/vhost-user-scsi/vhost-user-scsi.c
> +++ b/contrib/vhost-user-scsi/vhost-user-scsi.c
> @@ -109,14 +109,15 @@ static struct scsi_task *scsi_task_new(int cdb_len, uint8_t *cdb, int dir,
> static int get_cdb_len(uint8_t *cdb)
> {
> assert(cdb);
>
> switch (cdb[0] >> 5) {
> case 0: return 6;
> - case 1: /* fall through */
> + case 1:
> + fallthrough;
> case 2: return 10;
> case 4: return 16;
> case 5: return 12;
> }
> g_warning("Unable to determine cdb len (0x%02hhX)", (uint8_t)(cdb[0] >> 5));
> return -1;
> }
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [RFC PATCH 48/75] hw/arm: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (10 preceding siblings ...)
2023-10-13 7:48 ` [RFC PATCH 47/75] contrib/vhost-user-scsi: " Emmanouil Pitsidianakis
@ 2023-10-13 7:48 ` Emmanouil Pitsidianakis
2023-10-13 7:48 ` [RFC PATCH 49/75] hw/audio: " Emmanouil Pitsidianakis
` (7 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block; +Cc: Emmanouil Pitsidianakis, Peter Maydell
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/arm/omap1.c | 8 ++++----
hw/arm/pxa2xx.c | 5 +++--
hw/arm/stellaris.c | 1 +
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index d5438156ee..c54a4ec553 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -531,46 +531,46 @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
/* Ultra Low-Power Device Module */
static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = opaque;
uint16_t ret;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x14: /* IT_STATUS */
ret = s->ulpd_pm_regs[addr >> 2];
s->ulpd_pm_regs[addr >> 2] = 0;
qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
return ret;
case 0x18: /* Reserved */
case 0x1c: /* Reserved */
case 0x20: /* Reserved */
case 0x28: /* Reserved */
case 0x2c: /* Reserved */
OMAP_BAD_REG(addr);
- /* fall through */
+ fallthrough;
case 0x00: /* COUNTER_32_LSB */
case 0x04: /* COUNTER_32_MSB */
case 0x08: /* COUNTER_HIGH_FREQ_LSB */
case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
case 0x10: /* GAUGING_CTRL */
case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
case 0x30: /* CLOCK_CTRL */
case 0x34: /* SOFT_REQ */
case 0x38: /* COUNTER_32_FIQ */
case 0x3c: /* DPLL_CTRL */
case 0x40: /* STATUS_REQ */
/* XXX: check clk::usecount state for every clock */
case 0x48: /* LOCL_TIME */
case 0x4c: /* APLL_CTRL */
case 0x50: /* POWER_CTRL */
return s->ulpd_pm_regs[addr >> 2];
}
OMAP_BAD_REG(addr);
return 0;
}
@@ -600,120 +600,120 @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = opaque;
int64_t now, ticks;
int div, mult;
static const int bypass_div[4] = { 1, 2, 4, 4 };
uint16_t diff;
if (size != 2) {
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
case 0x00: /* COUNTER_32_LSB */
case 0x04: /* COUNTER_32_MSB */
case 0x08: /* COUNTER_HIGH_FREQ_LSB */
case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
case 0x14: /* IT_STATUS */
case 0x40: /* STATUS_REQ */
OMAP_RO_REG(addr);
break;
case 0x10: /* GAUGING_CTRL */
/* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (value & 1)
s->ulpd_gauge_start = now;
else {
now -= s->ulpd_gauge_start;
/* 32-kHz ticks */
ticks = muldiv64(now, 32768, NANOSECONDS_PER_SECOND);
s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
if (ticks >> 32) /* OVERFLOW_32K */
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
/* High frequency ticks */
ticks = muldiv64(now, 12000000, NANOSECONDS_PER_SECOND);
s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
if (ticks >> 32) /* OVERFLOW_HI_FREQ */
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
}
}
s->ulpd_pm_regs[addr >> 2] = value;
break;
case 0x18: /* Reserved */
case 0x1c: /* Reserved */
case 0x20: /* Reserved */
case 0x28: /* Reserved */
case 0x2c: /* Reserved */
OMAP_BAD_REG(addr);
- /* fall through */
+ fallthrough;
case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
case 0x38: /* COUNTER_32_FIQ */
case 0x48: /* LOCL_TIME */
case 0x50: /* POWER_CTRL */
s->ulpd_pm_regs[addr >> 2] = value;
break;
case 0x30: /* CLOCK_CTRL */
diff = s->ulpd_pm_regs[addr >> 2] ^ value;
s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
omap_ulpd_clk_update(s, diff, value);
break;
case 0x34: /* SOFT_REQ */
diff = s->ulpd_pm_regs[addr >> 2] ^ value;
s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
omap_ulpd_req_update(s, diff, value);
break;
case 0x3c: /* DPLL_CTRL */
/* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
* omitted altogether, probably a typo. */
/* This register has identical semantics with DPLL(1:3) control
* registers, see omap_dpll_write() */
diff = s->ulpd_pm_regs[addr >> 2] & value;
s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
if (diff & (0x3ff << 2)) {
if (value & (1 << 4)) { /* PLL_ENABLE */
div = ((value >> 5) & 3) + 1; /* PLL_DIV */
mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
} else {
div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
mult = 1;
}
omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
}
/* Enter the desired mode. */
s->ulpd_pm_regs[addr >> 2] =
(s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
/* Act as if the lock is restored. */
s->ulpd_pm_regs[addr >> 2] |= 2;
break;
case 0x4c: /* APLL_CTRL */
diff = s->ulpd_pm_regs[addr >> 2] & value;
s->ulpd_pm_regs[addr >> 2] = value & 0xf;
if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
(value & (1 << 0)) ? "apll" : "dpll4"));
break;
default:
OMAP_BAD_REG(addr);
}
}
@@ -3169,97 +3169,97 @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mcbsp_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (offset) {
case 0x00: /* DRR2 */
if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
return 0x0000;
- /* Fall through. */
+ fallthrough;
case 0x02: /* DRR1 */
if (s->rx_req < 2) {
printf("%s: Rx FIFO underrun\n", __func__);
omap_mcbsp_rx_done(s);
} else {
s->tx_req -= 2;
if (s->codec && s->codec->in.len >= 2) {
ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
ret |= s->codec->in.fifo[s->codec->in.start ++];
s->codec->in.len -= 2;
} else
ret = 0x0000;
if (!s->tx_req)
omap_mcbsp_rx_done(s);
return ret;
}
return 0x0000;
case 0x04: /* DXR2 */
case 0x06: /* DXR1 */
return 0x0000;
case 0x08: /* SPCR2 */
return s->spcr[1];
case 0x0a: /* SPCR1 */
return s->spcr[0];
case 0x0c: /* RCR2 */
return s->rcr[1];
case 0x0e: /* RCR1 */
return s->rcr[0];
case 0x10: /* XCR2 */
return s->xcr[1];
case 0x12: /* XCR1 */
return s->xcr[0];
case 0x14: /* SRGR2 */
return s->srgr[1];
case 0x16: /* SRGR1 */
return s->srgr[0];
case 0x18: /* MCR2 */
return s->mcr[1];
case 0x1a: /* MCR1 */
return s->mcr[0];
case 0x1c: /* RCERA */
return s->rcer[0];
case 0x1e: /* RCERB */
return s->rcer[1];
case 0x20: /* XCERA */
return s->xcer[0];
case 0x22: /* XCERB */
return s->xcer[1];
case 0x24: /* PCR0 */
return s->pcr;
case 0x26: /* RCERC */
return s->rcer[2];
case 0x28: /* RCERD */
return s->rcer[3];
case 0x2a: /* XCERC */
return s->xcer[2];
case 0x2c: /* XCERD */
return s->xcer[3];
case 0x2e: /* RCERE */
return s->rcer[4];
case 0x30: /* RCERF */
return s->rcer[5];
case 0x32: /* XCERE */
return s->xcer[4];
case 0x34: /* XCERF */
return s->xcer[5];
case 0x36: /* RCERG */
return s->rcer[6];
case 0x38: /* RCERH */
return s->rcer[7];
case 0x3a: /* XCERG */
return s->xcer[6];
case 0x3c: /* XCERH */
return s->xcer[7];
}
OMAP_BAD_REG(addr);
return 0;
}
@@ -3267,135 +3267,135 @@ static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_mcbsp_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x00: /* DRR2 */
case 0x02: /* DRR1 */
OMAP_RO_REG(addr);
return;
case 0x04: /* DXR2 */
if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
return;
- /* Fall through. */
+ fallthrough;
case 0x06: /* DXR1 */
if (s->tx_req > 1) {
s->tx_req -= 2;
if (s->codec && s->codec->cts) {
s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
}
if (s->tx_req < 2)
omap_mcbsp_tx_done(s);
} else
printf("%s: Tx FIFO overrun\n", __func__);
return;
case 0x08: /* SPCR2 */
s->spcr[1] &= 0x0002;
s->spcr[1] |= 0x03f9 & value;
s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
if (~value & 1) /* XRST */
s->spcr[1] &= ~6;
omap_mcbsp_req_update(s);
return;
case 0x0a: /* SPCR1 */
s->spcr[0] &= 0x0006;
s->spcr[0] |= 0xf8f9 & value;
if (value & (1 << 15)) /* DLB */
printf("%s: Digital Loopback mode enable attempt\n", __func__);
if (~value & 1) { /* RRST */
s->spcr[0] &= ~6;
s->rx_req = 0;
omap_mcbsp_rx_done(s);
}
omap_mcbsp_req_update(s);
return;
case 0x0c: /* RCR2 */
s->rcr[1] = value & 0xffff;
return;
case 0x0e: /* RCR1 */
s->rcr[0] = value & 0x7fe0;
return;
case 0x10: /* XCR2 */
s->xcr[1] = value & 0xffff;
return;
case 0x12: /* XCR1 */
s->xcr[0] = value & 0x7fe0;
return;
case 0x14: /* SRGR2 */
s->srgr[1] = value & 0xffff;
omap_mcbsp_req_update(s);
return;
case 0x16: /* SRGR1 */
s->srgr[0] = value & 0xffff;
omap_mcbsp_req_update(s);
return;
case 0x18: /* MCR2 */
s->mcr[1] = value & 0x03e3;
if (value & 3) /* XMCM */
printf("%s: Tx channel selection mode enable attempt\n", __func__);
return;
case 0x1a: /* MCR1 */
s->mcr[0] = value & 0x03e1;
if (value & 1) /* RMCM */
printf("%s: Rx channel selection mode enable attempt\n", __func__);
return;
case 0x1c: /* RCERA */
s->rcer[0] = value & 0xffff;
return;
case 0x1e: /* RCERB */
s->rcer[1] = value & 0xffff;
return;
case 0x20: /* XCERA */
s->xcer[0] = value & 0xffff;
return;
case 0x22: /* XCERB */
s->xcer[1] = value & 0xffff;
return;
case 0x24: /* PCR0 */
s->pcr = value & 0x7faf;
return;
case 0x26: /* RCERC */
s->rcer[2] = value & 0xffff;
return;
case 0x28: /* RCERD */
s->rcer[3] = value & 0xffff;
return;
case 0x2a: /* XCERC */
s->xcer[2] = value & 0xffff;
return;
case 0x2c: /* XCERD */
s->xcer[3] = value & 0xffff;
return;
case 0x2e: /* RCERE */
s->rcer[4] = value & 0xffff;
return;
case 0x30: /* RCERF */
s->rcer[5] = value & 0xffff;
return;
case 0x32: /* XCERE */
s->xcer[4] = value & 0xffff;
return;
case 0x34: /* XCERF */
s->xcer[5] = value & 0xffff;
return;
case 0x36: /* RCERG */
s->rcer[6] = value & 0xffff;
return;
case 0x38: /* RCERH */
s->rcer[7] = value & 0xffff;
return;
case 0x3a: /* XCERG */
s->xcer[6] = value & 0xffff;
return;
case 0x3c: /* XCERH */
s->xcer[7] = value & 0xffff;
return;
}
OMAP_BAD_REG(addr);
}
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 07d5dd8691..ee2b3ef719 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -265,68 +265,68 @@ static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
static const char *pwrmode[8] = {
"Normal", "Idle", "Deep-idle", "Standby",
"Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
};
if (value & 8) {
printf("%s: CPU voltage change attempt\n", __func__);
}
switch (value & 7) {
case 0:
/* Do nothing */
break;
case 1:
/* Idle */
if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
break;
}
- /* Fall through. */
+ fallthrough;
case 2:
/* Deep-Idle */
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
goto message;
case 3:
s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC;
s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;
s->cpu->env.cp15.sctlr_ns = 0;
s->cpu->env.cp15.cpacr_el1 = 0;
s->cpu->env.cp15.ttbr0_el[1] = 0;
s->cpu->env.cp15.dacr_ns = 0;
s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
/*
* The scratch-pad register is almost universally used
* for storing the return address on suspend. For the
* lack of a resuming bootloader, perform a jump
* directly to that address.
*/
memset(s->cpu->env.regs, 0, 4 * 15);
s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
#if 0
buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
cpu_physical_memory_write(0, &buffer, 4);
buffer = s->pm_regs[PSPR >> 2];
cpu_physical_memory_write(8, &buffer, 4);
#endif
/* Suspend */
cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
goto message;
default:
message:
printf("%s: machine entered %s mode\n", __func__,
pwrmode[value & 7]);
}
}
@@ -419,18 +419,18 @@ static void pxa2xx_setup_cp14(PXA2xxState *s)
static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case MDCNFG ... SA1110:
if ((addr & 3) == 0)
return s->mm_regs[addr >> 2];
- /* fall through */
+ fallthrough;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
return 0;
}
@@ -438,19 +438,20 @@ static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
static void pxa2xx_mm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case MDCNFG ... SA1110:
if ((addr & 3) == 0) {
s->mm_regs[addr >> 2] = value;
break;
}
/* fallthrough */
+ fallthrough;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, addr);
break;
}
}
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index aa5b0ddfaa..d68602ab71 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -147,20 +147,21 @@ static uint32_t pllcfg_fury[16] = {
static int ssys_board_class(const ssys_state *s)
{
uint32_t did0 = s->did0;
switch (did0 & DID0_VER_MASK) {
case DID0_VER_0:
return DID0_CLASS_SANDSTORM;
case DID0_VER_1:
switch (did0 & DID0_CLASS_MASK) {
case DID0_CLASS_SANDSTORM:
case DID0_CLASS_FURY:
return did0 & DID0_CLASS_MASK;
}
/* for unknown classes, fall through */
+ fallthrough;
default:
/* This can only happen if the hardwired constant did0 value
* in this board's stellaris_board_info struct is wrong.
*/
g_assert_not_reached();
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 49/75] hw/audio: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (11 preceding siblings ...)
2023-10-13 7:48 ` [RFC PATCH 48/75] hw/arm: " Emmanouil Pitsidianakis
@ 2023-10-13 7:48 ` Emmanouil Pitsidianakis
2023-10-13 7:48 ` [RFC PATCH 50/75] chardev: " Emmanouil Pitsidianakis
` (6 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block; +Cc: Emmanouil Pitsidianakis, Gerd Hoffmann
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/audio/cs4231a.c | 2 +-
hw/audio/gusemu_hal.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/audio/cs4231a.c b/hw/audio/cs4231a.c
index 3aa105748d..3bf0116c68 100644
--- a/hw/audio/cs4231a.c
+++ b/hw/audio/cs4231a.c
@@ -272,90 +272,90 @@ static void cs_audio_callback (void *opaque, int free)
static void cs_reset_voices (CSState *s, uint32_t val)
{
int xtal;
struct audsettings as;
IsaDmaClass *k = ISADMA_GET_CLASS(s->isa_dma);
#ifdef DEBUG_XLAW
if (val == 0 || val == 32)
val = (1 << 4) | (1 << 5);
#endif
xtal = val & 1;
as.freq = freqs[xtal][(val >> 1) & 7];
if (as.freq == -1) {
lerr ("unsupported frequency (val=%#x)\n", val);
goto error;
}
as.nchannels = (val & (1 << 4)) ? 2 : 1;
as.endianness = 0;
s->tab = NULL;
switch ((val >> 5) & ((s->dregs[MODE_And_ID] & MODE2) ? 7 : 3)) {
case 0:
as.fmt = AUDIO_FORMAT_U8;
s->shift = as.nchannels == 2;
break;
case 1:
s->tab = MuLawDecompressTable;
goto x_law;
case 3:
s->tab = ALawDecompressTable;
x_law:
as.fmt = AUDIO_FORMAT_S16;
as.endianness = AUDIO_HOST_ENDIANNESS;
s->shift = as.nchannels == 2;
break;
case 6:
as.endianness = 1;
- /* fall through */
+ fallthrough;
case 2:
as.fmt = AUDIO_FORMAT_S16;
s->shift = as.nchannels;
break;
case 7:
case 4:
lerr ("attempt to use reserved format value (%#x)\n", val);
goto error;
case 5:
lerr ("ADPCM 4 bit IMA compatible format is not supported\n");
goto error;
}
s->voice = AUD_open_out (
&s->card,
s->voice,
"cs4231a",
s,
cs_audio_callback,
&as
);
if (s->dregs[Interface_Configuration] & PEN) {
if (!s->dma_running) {
k->hold_DREQ(s->isa_dma, s->dma);
AUD_set_active_out (s->voice, 1);
s->transferred = 0;
}
s->dma_running = 1;
}
else {
if (s->dma_running) {
k->release_DREQ(s->isa_dma, s->dma);
AUD_set_active_out (s->voice, 0);
}
s->dma_running = 0;
}
return;
error:
if (s->dma_running) {
k->release_DREQ(s->isa_dma, s->dma);
AUD_set_active_out (s->voice, 0);
}
}
diff --git a/hw/audio/gusemu_hal.c b/hw/audio/gusemu_hal.c
index f159978b49..76dd906ea1 100644
--- a/hw/audio/gusemu_hal.c
+++ b/hw/audio/gusemu_hal.c
@@ -190,311 +190,311 @@ unsigned int gus_read(GUSEmuState * state, int port, int size)
void gus_write(GUSEmuState * state, int port, int size, unsigned int data)
{
uint8_t *gusptr;
gusptr = state->gusdatapos;
GUSregd(portaccesses)++;
switch (port & 0xff0f)
{
case 0x200: /* MixerCtrlReg */
GUSregb(MixerCtrlReg2x0) = (uint8_t) data;
break;
case 0x206: /* IRQstatReg / SB2x6IRQ */
if (GUSregb(GUS45TimerCtrl) & 0x20) /* SB IRQ enabled? -> set 2x6IRQ bit */
{
GUSregb(TimerStatus2x8) |= 0x08;
GUSregb(IRQStatReg2x6) = 0x10;
GUS_irqrequest(state, state->gusirq, 1);
}
break;
case 0x308: /* AdLib 388h */
case 0x208: /* AdLibCommandReg */
GUSregb(AdLibCommand2xA) = (uint8_t) data;
break;
case 0x309: /* AdLib 389h */
case 0x209: /* AdLibDataReg */
if ((GUSregb(AdLibCommand2xA) == 0x04) && (!(GUSregb(GUS45TimerCtrl) & 1))) /* GUS auto timer mode enabled? */
{
if (data & 0x80)
GUSregb(TimerStatus2x8) &= 0x1f; /* AdLib IRQ reset? -> clear maskable adl. timer int regs */
else
GUSregb(TimerDataReg2x9) = (uint8_t) data;
}
else
{
GUSregb(AdLibData2x9) = (uint8_t) data;
if (GUSregb(GUS45TimerCtrl) & 0x02)
{
GUSregb(TimerStatus2x8) |= 0x01;
GUSregb(IRQStatReg2x6) = 0x10;
GUS_irqrequest(state, state->gusirq, 1);
}
}
break;
case 0x20A:
GUSregb(AdLibStatus2x8) = (uint8_t) data;
break; /* AdLibStatus2x8 */
case 0x20B: /* GUS hidden registers */
switch (GUSregb(RegCtrl_2xF) & 0x7)
{
case 0:
if (GUSregb(MixerCtrlReg2x0) & 0x40)
GUSregb(IRQ_2xB) = (uint8_t) data; /* control register select bit */
else
GUSregb(DMA_2xB) = (uint8_t) data;
break;
/* case 1-4: general purpose emulation regs */
case 5: /* clear stat reg 2xF */
GUSregb(StatRead_2xF) = 0; /* ToDo: is this identical with GUS classic? */
if (!GUSregb(IRQStatReg2x6))
GUS_irqclear(state, state->gusirq);
break;
case 6: /* Jumper reg (Joystick/MIDI enable) */
GUSregb(Jumper_2xB) = (uint8_t) data;
break;
default:;
}
break;
case 0x20C: /* SB2xCd */
if (GUSregb(GUS45TimerCtrl) & 0x20)
{
GUSregb(TimerStatus2x8) |= 0x10; /* SB IRQ enabled? -> set 2xCIRQ bit */
GUSregb(IRQStatReg2x6) = 0x10;
GUS_irqrequest(state, state->gusirq, 1);
}
- /* fall through */
+ fallthrough;
case 0x20D: /* SB2xCd no IRQ */
GUSregb(SB2xCd) = (uint8_t) data;
break;
case 0x20E: /* SB2xE */
GUSregb(SB2xE) = (uint8_t) data;
break;
case 0x20F:
GUSregb(RegCtrl_2xF) = (uint8_t) data;
break; /* CtrlReg2xF */
case 0x302: /* VoiceSelReg */
GUSregb(VoiceSelReg3x2) = (uint8_t) data;
break;
case 0x303: /* FunkSelReg */
GUSregb(FunkSelReg3x3) = (uint8_t) data;
if ((uint8_t) data == 0x8f) /* set irqstatreg, get voicereg and clear IRQ */
{
int voice;
if (GUSregd(voicewavetableirq)) /* WavetableIRQ */
{
for (voice = 0; voice < 31; voice++)
{
if (GUSregd(voicewavetableirq) & (1 << voice))
{
GUSregd(voicewavetableirq) ^= (1 << voice); /* clear IRQ bit */
GUSregb(voice << 5) &= 0x7f; /* clear voice reg irq bit */
if (!GUSregd(voicewavetableirq))
GUSregb(IRQStatReg2x6) &= 0xdf;
if (!GUSregb(IRQStatReg2x6))
GUS_irqclear(state, state->gusirq);
GUSregb(SynVoiceIRQ8f) = voice | 0x60; /* (bit==0 => IRQ wartend) */
return;
}
}
}
else if (GUSregd(voicevolrampirq)) /* VolRamp IRQ */
{
for (voice = 0; voice < 31; voice++)
{
if (GUSregd(voicevolrampirq) & (1 << voice))
{
GUSregd(voicevolrampirq) ^= (1 << voice); /* clear IRQ bit */
GUSregb((voice << 5) + VSRVolRampControl) &= 0x7f; /* clear voice volume reg irq bit */
if (!GUSregd(voicevolrampirq))
GUSregb(IRQStatReg2x6) &= 0xbf;
if (!GUSregb(IRQStatReg2x6))
GUS_irqclear(state, state->gusirq);
GUSregb(SynVoiceIRQ8f) = voice | 0x80; /* (bit==0 => IRQ wartend) */
return;
}
}
}
GUSregb(SynVoiceIRQ8f) = 0xe8; /* kein IRQ wartet */
}
break;
case 0x304:
case 0x305:
{
uint16_t writedata = (uint16_t) data;
uint16_t readmask = 0x0000;
if (size == 1)
{
readmask = 0xff00;
writedata &= 0xff;
if ((port & 0xff0f) == 0x305)
{
writedata = (uint16_t) (writedata << 8);
readmask = 0x00ff;
}
}
switch (GUSregb(FunkSelReg3x3))
{
/* voice specific functions */
case 0x00:
case 0x01:
case 0x02:
case 0x03:
case 0x04:
case 0x05:
case 0x06:
case 0x07:
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x0c:
case 0x0d:
{
int offset;
if (!(GUSregb(GUS4cReset) & 0x01))
break; /* reset flag active? */
offset = 2 * (GUSregb(FunkSelReg3x3) & 0x0f);
offset += (GUSregb(VoiceSelReg3x2) & 0x1f) << 5; /* = Voice*32 + Function*2 */
GUSregw(offset) = (uint16_t) ((GUSregw(offset) & readmask) | writedata);
}
break;
/* voice unspecific functions */
case 0x0e: /* NumVoices */
GUSregb(NumVoices) = (uint8_t) data;
break;
/* case 0x0f: */ /* read only */
/* common functions */
case 0x41: /* DramDMAContrReg */
GUSregb(GUS41DMACtrl) = (uint8_t) data;
if (data & 0x01)
GUS_dmarequest(state);
break;
case 0x42: /* DramDMAmemPosReg */
GUSregw(GUS42DMAStart) = (GUSregw(GUS42DMAStart) & readmask) | writedata;
GUSregb(GUS50DMAHigh) &= 0xf; /* compatibility stuff... */
break;
case 0x43: /* DRAMaddrLo */
GUSregd(GUSDRAMPOS24bit) =
(GUSregd(GUSDRAMPOS24bit) & (readmask | 0xff0000)) | writedata;
break;
case 0x44: /* DRAMaddrHi */
GUSregd(GUSDRAMPOS24bit) =
(GUSregd(GUSDRAMPOS24bit) & 0xffff) | ((data & 0x0f) << 16);
break;
case 0x45: /* TCtrlReg */
GUSregb(GUS45TimerCtrl) = (uint8_t) data;
if (!(data & 0x20))
GUSregb(TimerStatus2x8) &= 0xe7; /* sb IRQ dis? -> clear 2x8/2xC sb IRQ flags */
if (!(data & 0x02))
GUSregb(TimerStatus2x8) &= 0xfe; /* adlib data IRQ dis? -> clear 2x8 adlib IRQ flag */
if (!(GUSregb(TimerStatus2x8) & 0x19))
GUSregb(IRQStatReg2x6) &= 0xef; /* 0xe6; $$clear IRQ if both IRQ bits are inactive or cleared */
/* catch up delayed timer IRQs: */
if ((GUSregw(TimerIRQs) > 1) && (GUSregb(TimerDataReg2x9) & 3))
{
if (GUSregb(TimerDataReg2x9) & 1) /* start timer 1 (80us decrement rate) */
{
if (!(GUSregb(TimerDataReg2x9) & 0x40))
GUSregb(TimerStatus2x8) |= 0xc0; /* maskable bits */
if (data & 4) /* timer1 irq enable */
{
GUSregb(TimerStatus2x8) |= 4; /* nonmaskable bit */
GUSregb(IRQStatReg2x6) |= 4; /* timer 1 irq pending */
}
}
if (GUSregb(TimerDataReg2x9) & 2) /* start timer 2 (320us decrement rate) */
{
if (!(GUSregb(TimerDataReg2x9) & 0x20))
GUSregb(TimerStatus2x8) |= 0xa0; /* maskable bits */
if (data & 8) /* timer2 irq enable */
{
GUSregb(TimerStatus2x8) |= 2; /* nonmaskable bit */
GUSregb(IRQStatReg2x6) |= 8; /* timer 2 irq pending */
}
}
GUSregw(TimerIRQs)--;
if (GUSregw(BusyTimerIRQs) > 1)
GUSregw(BusyTimerIRQs)--;
else
GUSregw(BusyTimerIRQs) =
GUS_irqrequest(state, state->gusirq, GUSregw(TimerIRQs));
}
else
GUSregw(TimerIRQs) = 0;
if (!(data & 0x04))
{
GUSregb(TimerStatus2x8) &= 0xfb; /* clear non-maskable timer1 bit */
GUSregb(IRQStatReg2x6) &= 0xfb;
}
if (!(data & 0x08))
{
GUSregb(TimerStatus2x8) &= 0xfd; /* clear non-maskable timer2 bit */
GUSregb(IRQStatReg2x6) &= 0xf7;
}
if (!GUSregb(IRQStatReg2x6))
GUS_irqclear(state, state->gusirq);
break;
case 0x46: /* Counter1 */
GUSregb(GUS46Counter1) = (uint8_t) data;
break;
case 0x47: /* Counter2 */
GUSregb(GUS47Counter2) = (uint8_t) data;
break;
/* case 0x48: */ /* sampling freq reg not emulated (same as interwave) */
case 0x49: /* SampCtrlReg */
GUSregb(GUS49SampCtrl) = (uint8_t) data;
break;
/* case 0x4b: */ /* joystick trim not emulated */
case 0x4c: /* GUSreset */
GUSregb(GUS4cReset) = (uint8_t) data;
if (!(GUSregb(GUS4cReset) & 1)) /* reset... */
{
GUSregd(voicewavetableirq) = 0;
GUSregd(voicevolrampirq) = 0;
GUSregw(TimerIRQs) = 0;
GUSregw(BusyTimerIRQs) = 0;
GUSregb(NumVoices) = 0xcd;
GUSregb(IRQStatReg2x6) = 0;
GUSregb(TimerStatus2x8) = 0;
GUSregb(AdLibData2x9) = 0;
GUSregb(TimerDataReg2x9) = 0;
GUSregb(GUS41DMACtrl) = 0;
GUSregb(GUS45TimerCtrl) = 0;
GUSregb(GUS49SampCtrl) = 0;
GUSregb(GUS4cReset) &= 0xf9; /* clear IRQ and DAC enable bits */
GUS_irqclear(state, state->gusirq);
}
/* IRQ enable bit checked elsewhere */
/* EnableDAC bit may be used by external callers */
break;
}
}
break;
case 0x307: /* DRAMaccess */
{
uint8_t *adr;
adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);
*adr = (uint8_t) data;
}
break;
}
}
/* Attention when breaking up a single DMA transfer to multiple ones:
* it may lead to multiple terminal count interrupts and broken transfers:
*
* 1. Whenever you transfer a piece of data, the gusemu callback is invoked
* 2. The callback may generate a TC irq (if the register was set up to do so)
* 3. The irq may result in the program using the GUS to reprogram the GUS
*
* Some programs also decide to upload by just checking if TC occurs
* (via interrupt or a cleared GUS dma flag)
* and then start the next transfer, without checking DMA state
*
* Thus: Always make sure to set the TC flag correctly!
*
* Note that the genuine GUS had a granularity of 16 bytes/words for low/high DMA
* while later cards had atomic granularity provided by an additional GUS50DMAHigh register
* GUSemu also uses this register to support byte-granular transfers for better compatibility
* with emulators other than GUSemu32
*/
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 50/75] chardev: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (12 preceding siblings ...)
2023-10-13 7:48 ` [RFC PATCH 49/75] hw/audio: " Emmanouil Pitsidianakis
@ 2023-10-13 7:48 ` Emmanouil Pitsidianakis
2023-10-13 7:48 ` [RFC PATCH 51/75] hw/char: " Emmanouil Pitsidianakis
` (5 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block
Cc: Emmanouil Pitsidianakis, Marc-André Lureau, Paolo Bonzini
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
chardev/char-socket.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/chardev/char-socket.c b/chardev/char-socket.c
index 73947da188..1562e066a4 100644
--- a/chardev/char-socket.c
+++ b/chardev/char-socket.c
@@ -549,34 +549,34 @@ static int tcp_chr_sync_read(Chardev *chr, const uint8_t *buf, int len)
static char *qemu_chr_compute_filename(SocketChardev *s)
{
struct sockaddr_storage *ss = &s->sioc->localAddr;
struct sockaddr_storage *ps = &s->sioc->remoteAddr;
socklen_t ss_len = s->sioc->localAddrLen;
socklen_t ps_len = s->sioc->remoteAddrLen;
char shost[NI_MAXHOST], sserv[NI_MAXSERV];
char phost[NI_MAXHOST], pserv[NI_MAXSERV];
const char *left = "", *right = "";
switch (ss->ss_family) {
case AF_UNIX:
return g_strdup_printf("unix:%s%s",
((struct sockaddr_un *)(ss))->sun_path,
s->is_listen ? ",server=on" : "");
case AF_INET6:
left = "[";
right = "]";
- /* fall through */
+ fallthrough;
case AF_INET:
getnameinfo((struct sockaddr *) ss, ss_len, shost, sizeof(shost),
sserv, sizeof(sserv), NI_NUMERICHOST | NI_NUMERICSERV);
getnameinfo((struct sockaddr *) ps, ps_len, phost, sizeof(phost),
pserv, sizeof(pserv), NI_NUMERICHOST | NI_NUMERICSERV);
return g_strdup_printf("%s:%s%s%s:%s%s <-> %s%s%s:%s",
qemu_chr_socket_protocol(s),
left, shost, right, sserv,
s->is_listen ? ",server=on" : "",
left, phost, right, pserv);
default:
return g_strdup_printf("unknown");
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 51/75] hw/char: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (13 preceding siblings ...)
2023-10-13 7:48 ` [RFC PATCH 50/75] chardev: " Emmanouil Pitsidianakis
@ 2023-10-13 7:48 ` Emmanouil Pitsidianakis
2023-10-13 7:48 ` [RFC PATCH 52/75] nbd: " Emmanouil Pitsidianakis
` (4 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block
Cc: Emmanouil Pitsidianakis, Joel Stanley, Peter Maydell,
Marc-André Lureau, Paolo Bonzini
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/char/nrf51_uart.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c
index dfe2276d71..3e2b35c7ad 100644
--- a/hw/char/nrf51_uart.c
+++ b/hw/char/nrf51_uart.c
@@ -113,79 +113,79 @@ static void uart_cancel_transmit(NRF51UARTState *s)
static void uart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned int size)
{
NRF51UARTState *s = NRF51_UART(opaque);
trace_nrf51_uart_write(addr, value, size);
if (!s->enabled && (addr != A_UART_ENABLE)) {
return;
}
switch (addr) {
case A_UART_TXD:
if (!s->pending_tx_byte && s->tx_started) {
s->reg[R_UART_TXD] = value;
s->pending_tx_byte = true;
uart_transmit(NULL, G_IO_OUT, s);
}
break;
case A_UART_INTEN:
s->reg[R_UART_INTEN] = value;
break;
case A_UART_INTENSET:
s->reg[R_UART_INTEN] |= value;
break;
case A_UART_INTENCLR:
s->reg[R_UART_INTEN] &= ~value;
break;
case A_UART_TXDRDY ... A_UART_RXTO:
s->reg[addr / 4] = value;
break;
case A_UART_ERRORSRC:
s->reg[addr / 4] &= ~value;
break;
case A_UART_RXD:
break;
case A_UART_RXDRDY:
if (value == 0) {
s->reg[R_UART_RXDRDY] = 0;
}
break;
case A_UART_STARTTX:
if (value == 1) {
s->tx_started = true;
}
break;
case A_UART_STARTRX:
if (value == 1) {
s->rx_started = true;
}
break;
case A_UART_ENABLE:
if (value) {
if (value == 4) {
s->enabled = true;
}
break;
}
s->enabled = false;
value = 1;
- /* fall through */
+ fallthrough;
case A_UART_SUSPEND:
case A_UART_STOPTX:
if (value == 1) {
s->tx_started = false;
}
- /* fall through */
+ fallthrough;
case A_UART_STOPRX:
if (addr != A_UART_STOPTX && value == 1) {
s->rx_started = false;
s->reg[R_UART_RXTO] = 1;
}
break;
default:
s->reg[addr / 4] = value;
break;
}
nrf51_uart_update_irq(s);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 52/75] nbd: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (14 preceding siblings ...)
2023-10-13 7:48 ` [RFC PATCH 51/75] hw/char: " Emmanouil Pitsidianakis
@ 2023-10-13 7:48 ` Emmanouil Pitsidianakis
2023-10-13 7:48 ` [RFC PATCH 53/75] hw/core: " Emmanouil Pitsidianakis
` (3 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block
Cc: Emmanouil Pitsidianakis, Eric Blake, Vladimir Sementsov-Ogievskiy
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
nbd/client.c | 4 ++--
nbd/common.c | 2 +-
qemu-nbd.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/nbd/client.c b/nbd/client.c
index 29ffc609a4..04507249b2 100644
--- a/nbd/client.c
+++ b/nbd/client.c
@@ -1014,102 +1014,102 @@ static int nbd_negotiate_finish_oldstyle(QIOChannel *ioc, NBDExportInfo *info,
/*
* nbd_receive_negotiate:
* Connect to server, complete negotiation, and move into transmission phase.
* Returns: negative errno: failure talking to server
* 0: server is connected
*/
int nbd_receive_negotiate(QIOChannel *ioc, QCryptoTLSCreds *tlscreds,
const char *hostname, QIOChannel **outioc,
NBDExportInfo *info, Error **errp)
{
ERRP_GUARD();
int result;
bool zeroes;
bool base_allocation = info->base_allocation;
assert(info->name && strlen(info->name) <= NBD_MAX_STRING_SIZE);
trace_nbd_receive_negotiate_name(info->name);
result = nbd_start_negotiate(ioc, tlscreds, hostname, outioc,
info->mode, &zeroes, errp);
if (result < 0) {
return result;
}
info->mode = result;
info->base_allocation = false;
if (tlscreds && *outioc) {
ioc = *outioc;
}
switch (info->mode) {
case NBD_MODE_EXTENDED:
case NBD_MODE_STRUCTURED:
if (base_allocation) {
result = nbd_negotiate_simple_meta_context(ioc, info, errp);
if (result < 0) {
return -EINVAL;
}
info->base_allocation = result == 1;
}
- /* fall through */
+ fallthrough;
case NBD_MODE_SIMPLE:
/* Try NBD_OPT_GO first - if it works, we are done (it
* also gives us a good message if the server requires
* TLS). If it is not available, fall back to
* NBD_OPT_LIST for nicer error messages about a missing
* export, then use NBD_OPT_EXPORT_NAME. */
result = nbd_opt_info_or_go(ioc, NBD_OPT_GO, info, errp);
if (result < 0) {
return -EINVAL;
}
if (result > 0) {
return 0;
}
/* Check our desired export is present in the
* server export list. Since NBD_OPT_EXPORT_NAME
* cannot return an error message, running this
* query gives us better error reporting if the
* export name is not available.
*/
if (nbd_receive_query_exports(ioc, info->name, errp) < 0) {
return -EINVAL;
}
- /* fall through */
+ fallthrough;
case NBD_MODE_EXPORT_NAME:
/* write the export name request */
if (nbd_send_option_request(ioc, NBD_OPT_EXPORT_NAME, -1, info->name,
errp) < 0) {
return -EINVAL;
}
/* Read the response */
if (nbd_read64(ioc, &info->size, "export length", errp) < 0) {
return -EINVAL;
}
if (nbd_read16(ioc, &info->flags, "export flags", errp) < 0) {
return -EINVAL;
}
break;
case NBD_MODE_OLDSTYLE:
if (*info->name) {
error_setg(errp, "Server does not support non-empty export names");
return -EINVAL;
}
if (nbd_negotiate_finish_oldstyle(ioc, info, errp) < 0) {
return -EINVAL;
}
break;
default:
g_assert_not_reached();
}
trace_nbd_receive_negotiate_size_flags(info->size, info->flags);
if (zeroes && nbd_drop(ioc, 124, errp) < 0) {
error_prepend(errp, "Failed to read reserved block: ");
return -EINVAL;
}
return 0;
}
/* Clean up result of nbd_receive_export_list */
diff --git a/nbd/common.c b/nbd/common.c
index 3247c1d618..1140ea0888 100644
--- a/nbd/common.c
+++ b/nbd/common.c
@@ -222,37 +222,37 @@ const char *nbd_err_lookup(int err)
int nbd_errno_to_system_errno(int err)
{
int ret;
switch (err) {
case NBD_SUCCESS:
ret = 0;
break;
case NBD_EPERM:
ret = EPERM;
break;
case NBD_EIO:
ret = EIO;
break;
case NBD_ENOMEM:
ret = ENOMEM;
break;
case NBD_ENOSPC:
ret = ENOSPC;
break;
case NBD_EOVERFLOW:
ret = EOVERFLOW;
break;
case NBD_ENOTSUP:
ret = ENOTSUP;
break;
case NBD_ESHUTDOWN:
ret = ESHUTDOWN;
break;
default:
trace_nbd_unknown_error(err);
- /* fallthrough */
+ fallthrough;
case NBD_EINVAL:
ret = EINVAL;
break;
}
return ret;
}
diff --git a/qemu-nbd.c b/qemu-nbd.c
index 186e6468b1..41e50208a5 100644
--- a/qemu-nbd.c
+++ b/qemu-nbd.c
@@ -528,704 +528,704 @@ static void qemu_nbd_shutdown(void)
int main(int argc, char **argv)
{
BlockBackend *blk;
BlockDriverState *bs;
uint64_t dev_offset = 0;
bool readonly = false;
bool disconnect = false;
const char *bindto = NULL;
const char *port = NULL;
char *sockpath = NULL;
QemuOpts *sn_opts = NULL;
const char *sn_id_or_name = NULL;
const char *sopt = "hVb:o:p:rsnc:dvk:e:f:tl:x:T:D:AB:L";
struct option lopt[] = {
{ "help", no_argument, NULL, 'h' },
{ "version", no_argument, NULL, 'V' },
{ "bind", required_argument, NULL, 'b' },
{ "port", required_argument, NULL, 'p' },
{ "socket", required_argument, NULL, 'k' },
{ "offset", required_argument, NULL, 'o' },
{ "read-only", no_argument, NULL, 'r' },
{ "allocation-depth", no_argument, NULL, 'A' },
{ "bitmap", required_argument, NULL, 'B' },
{ "connect", required_argument, NULL, 'c' },
{ "disconnect", no_argument, NULL, 'd' },
{ "list", no_argument, NULL, 'L' },
{ "snapshot", no_argument, NULL, 's' },
{ "load-snapshot", required_argument, NULL, 'l' },
{ "nocache", no_argument, NULL, 'n' },
{ "cache", required_argument, NULL, QEMU_NBD_OPT_CACHE },
{ "aio", required_argument, NULL, QEMU_NBD_OPT_AIO },
{ "discard", required_argument, NULL, QEMU_NBD_OPT_DISCARD },
{ "detect-zeroes", required_argument, NULL,
QEMU_NBD_OPT_DETECT_ZEROES },
{ "shared", required_argument, NULL, 'e' },
{ "format", required_argument, NULL, 'f' },
{ "persistent", no_argument, NULL, 't' },
{ "verbose", no_argument, NULL, 'v' },
{ "object", required_argument, NULL, QEMU_NBD_OPT_OBJECT },
{ "export-name", required_argument, NULL, 'x' },
{ "description", required_argument, NULL, 'D' },
{ "tls-creds", required_argument, NULL, QEMU_NBD_OPT_TLSCREDS },
{ "tls-hostname", required_argument, NULL, QEMU_NBD_OPT_TLSHOSTNAME },
{ "tls-authz", required_argument, NULL, QEMU_NBD_OPT_TLSAUTHZ },
{ "image-opts", no_argument, NULL, QEMU_NBD_OPT_IMAGE_OPTS },
{ "trace", required_argument, NULL, 'T' },
{ "fork", no_argument, NULL, QEMU_NBD_OPT_FORK },
{ "pid-file", required_argument, NULL, QEMU_NBD_OPT_PID_FILE },
{ "selinux-label", required_argument, NULL,
QEMU_NBD_OPT_SELINUX_LABEL },
{ NULL, 0, NULL, 0 }
};
int ch;
int opt_ind = 0;
int flags = BDRV_O_RDWR;
int ret = 0;
bool seen_cache = false;
bool seen_discard = false;
bool seen_aio = false;
pthread_t client_thread;
const char *fmt = NULL;
Error *local_err = NULL;
BlockdevDetectZeroesOptions detect_zeroes = BLOCKDEV_DETECT_ZEROES_OPTIONS_OFF;
QDict *options = NULL;
const char *export_name = NULL; /* defaults to "" later for server mode */
const char *export_description = NULL;
BlockDirtyBitmapOrStrList *bitmaps = NULL;
bool alloc_depth = false;
const char *tlscredsid = NULL;
const char *tlshostname = NULL;
bool imageOpts = false;
bool writethrough = false; /* Client will flush as needed. */
bool list = false;
unsigned socket_activation;
const char *pid_file_name = NULL;
const char *selinux_label = NULL;
BlockExportOptions *export_opts;
struct NbdClientOpts opts = {
.fork_process = false,
.verbose = false,
.device = NULL,
.srcpath = NULL,
.saddr = NULL,
.old_stderr = STDOUT_FILENO,
};
#ifdef CONFIG_POSIX
os_setup_early_signal_handling();
os_setup_signal_handling();
#endif
socket_init();
error_init(argv[0]);
module_call_init(MODULE_INIT_TRACE);
qcrypto_init(&error_fatal);
module_call_init(MODULE_INIT_QOM);
qemu_add_opts(&qemu_trace_opts);
qemu_init_exec_dir(argv[0]);
while ((ch = getopt_long(argc, argv, sopt, lopt, &opt_ind)) != -1) {
switch (ch) {
case 's':
flags |= BDRV_O_SNAPSHOT;
break;
case 'n':
optarg = (char *) "none";
- /* fallthrough */
+ fallthrough;
case QEMU_NBD_OPT_CACHE:
if (seen_cache) {
error_report("-n and --cache can only be specified once");
exit(EXIT_FAILURE);
}
seen_cache = true;
if (bdrv_parse_cache_mode(optarg, &flags, &writethrough) == -1) {
error_report("Invalid cache mode `%s'", optarg);
exit(EXIT_FAILURE);
}
break;
case QEMU_NBD_OPT_AIO:
if (seen_aio) {
error_report("--aio can only be specified once");
exit(EXIT_FAILURE);
}
seen_aio = true;
if (bdrv_parse_aio(optarg, &flags) < 0) {
error_report("Invalid aio mode '%s'", optarg);
exit(EXIT_FAILURE);
}
break;
case QEMU_NBD_OPT_DISCARD:
if (seen_discard) {
error_report("--discard can only be specified once");
exit(EXIT_FAILURE);
}
seen_discard = true;
if (bdrv_parse_discard_flags(optarg, &flags) == -1) {
error_report("Invalid discard mode `%s'", optarg);
exit(EXIT_FAILURE);
}
break;
case QEMU_NBD_OPT_DETECT_ZEROES:
detect_zeroes =
qapi_enum_parse(&BlockdevDetectZeroesOptions_lookup,
optarg,
BLOCKDEV_DETECT_ZEROES_OPTIONS_OFF,
&local_err);
if (local_err) {
error_reportf_err(local_err,
"Failed to parse detect_zeroes mode: ");
exit(EXIT_FAILURE);
}
if (detect_zeroes == BLOCKDEV_DETECT_ZEROES_OPTIONS_UNMAP &&
!(flags & BDRV_O_UNMAP)) {
error_report("setting detect-zeroes to unmap is not allowed "
"without setting discard operation to unmap");
exit(EXIT_FAILURE);
}
break;
case 'b':
bindto = optarg;
break;
case 'p':
port = optarg;
break;
case 'o':
if (qemu_strtou64(optarg, NULL, 0, &dev_offset) < 0) {
error_report("Invalid offset '%s'", optarg);
exit(EXIT_FAILURE);
}
break;
case 'l':
if (strstart(optarg, SNAPSHOT_OPT_BASE, NULL)) {
sn_opts = qemu_opts_parse_noisily(&internal_snapshot_opts,
optarg, false);
if (!sn_opts) {
error_report("Failed in parsing snapshot param `%s'",
optarg);
exit(EXIT_FAILURE);
}
} else {
sn_id_or_name = optarg;
}
- /* fall through */
+ fallthrough;
case 'r':
readonly = true;
flags &= ~BDRV_O_RDWR;
break;
case 'A':
alloc_depth = true;
break;
case 'B':
{
BlockDirtyBitmapOrStr *el = g_new(BlockDirtyBitmapOrStr, 1);
*el = (BlockDirtyBitmapOrStr) {
.type = QTYPE_QSTRING,
.u.local = g_strdup(optarg),
};
QAPI_LIST_PREPEND(bitmaps, el);
}
break;
case 'k':
sockpath = optarg;
if (sockpath[0] != '/') {
error_report("socket path must be absolute");
exit(EXIT_FAILURE);
}
break;
case 'd':
disconnect = true;
break;
case 'c':
opts.device = optarg;
break;
case 'e':
if (qemu_strtoi(optarg, NULL, 0, &shared) < 0 ||
shared < 0) {
error_report("Invalid shared device number '%s'", optarg);
exit(EXIT_FAILURE);
}
break;
case 'f':
fmt = optarg;
break;
case 't':
persistent = 1;
break;
case 'x':
export_name = optarg;
if (strlen(export_name) > NBD_MAX_STRING_SIZE) {
error_report("export name '%s' too long", export_name);
exit(EXIT_FAILURE);
}
break;
case 'D':
export_description = optarg;
if (strlen(export_description) > NBD_MAX_STRING_SIZE) {
error_report("export description '%s' too long",
export_description);
exit(EXIT_FAILURE);
}
break;
case 'v':
opts.verbose = true;
break;
case 'V':
version(argv[0]);
exit(0);
break;
case 'h':
usage(argv[0]);
exit(0);
break;
case '?':
error_report("Try `%s --help' for more information.", argv[0]);
exit(EXIT_FAILURE);
case QEMU_NBD_OPT_OBJECT:
user_creatable_process_cmdline(optarg);
break;
case QEMU_NBD_OPT_TLSCREDS:
tlscredsid = optarg;
break;
case QEMU_NBD_OPT_TLSHOSTNAME:
tlshostname = optarg;
break;
case QEMU_NBD_OPT_IMAGE_OPTS:
imageOpts = true;
break;
case 'T':
trace_opt_parse(optarg);
break;
case QEMU_NBD_OPT_TLSAUTHZ:
tlsauthz = optarg;
break;
case QEMU_NBD_OPT_FORK:
opts.fork_process = true;
break;
case 'L':
list = true;
break;
case QEMU_NBD_OPT_PID_FILE:
pid_file_name = optarg;
break;
case QEMU_NBD_OPT_SELINUX_LABEL:
selinux_label = optarg;
break;
}
}
if (list) {
if (argc != optind) {
error_report("List mode is incompatible with a file name");
exit(EXIT_FAILURE);
}
if (export_name || export_description || dev_offset ||
opts.device || disconnect || fmt || sn_id_or_name || bitmaps ||
alloc_depth || seen_aio || seen_discard || seen_cache) {
error_report("List mode is incompatible with per-device settings");
exit(EXIT_FAILURE);
}
if (opts.fork_process) {
error_report("List mode is incompatible with forking");
exit(EXIT_FAILURE);
}
} else if ((argc - optind) != 1) {
error_report("Invalid number of arguments");
error_printf("Try `%s --help' for more information.\n", argv[0]);
exit(EXIT_FAILURE);
} else if (!export_name) {
export_name = "";
}
if (!trace_init_backends()) {
exit(1);
}
trace_init_file();
qemu_set_log(LOG_TRACE, &error_fatal);
socket_activation = check_socket_activation();
if (socket_activation == 0) {
if (!sockpath) {
setup_address_and_port(&bindto, &port);
}
} else {
/* Using socket activation - check user didn't use -p etc. */
const char *err_msg = socket_activation_validate_opts(opts.device,
sockpath,
bindto, port,
selinux_label,
list);
if (err_msg != NULL) {
error_report("%s", err_msg);
exit(EXIT_FAILURE);
}
/* qemu-nbd can only listen on a single socket. */
if (socket_activation > 1) {
error_report("qemu-nbd does not support socket activation with %s > 1",
"LISTEN_FDS");
exit(EXIT_FAILURE);
}
}
if (tlscredsid) {
if (opts.device) {
error_report("TLS is not supported with a host device");
exit(EXIT_FAILURE);
}
if (tlsauthz && list) {
error_report("TLS authorization is incompatible with export list");
exit(EXIT_FAILURE);
}
if (tlshostname && !list) {
error_report("TLS hostname is only supported with export list");
exit(EXIT_FAILURE);
}
tlscreds = nbd_get_tls_creds(tlscredsid, list, &local_err);
if (local_err) {
error_reportf_err(local_err, "Failed to get TLS creds: ");
exit(EXIT_FAILURE);
}
} else {
if (tlsauthz) {
error_report("--tls-authz is not permitted without --tls-creds");
exit(EXIT_FAILURE);
}
if (tlshostname) {
error_report("--tls-hostname is not permitted without --tls-creds");
exit(EXIT_FAILURE);
}
}
if (selinux_label) {
#ifdef CONFIG_SELINUX
if (sockpath == NULL && opts.device == NULL) {
error_report("--selinux-label is not permitted without --socket");
exit(EXIT_FAILURE);
}
#else
error_report("SELinux support not enabled in this binary");
exit(EXIT_FAILURE);
#endif
}
if (list) {
opts.saddr = nbd_build_socket_address(sockpath, bindto, port);
return qemu_nbd_client_list(opts.saddr, tlscreds,
tlshostname ? tlshostname : bindto);
}
#if !HAVE_NBD_DEVICE
if (disconnect || opts.device) {
error_report("Kernel /dev/nbdN support not available");
exit(EXIT_FAILURE);
}
#else /* HAVE_NBD_DEVICE */
if (disconnect) {
int nbdfd = open(argv[optind], O_RDWR);
if (nbdfd < 0) {
error_report("Cannot open %s: %s", argv[optind],
strerror(errno));
exit(EXIT_FAILURE);
}
nbd_disconnect(nbdfd);
close(nbdfd);
printf("%s disconnected\n", argv[optind]);
return 0;
}
#endif
if ((opts.device && !opts.verbose) || opts.fork_process) {
#ifndef WIN32
g_autoptr(GError) err = NULL;
int stderr_fd[2];
pid_t pid;
if (!g_unix_open_pipe(stderr_fd, FD_CLOEXEC, &err)) {
error_report("Error setting up communication pipe: %s",
err->message);
exit(EXIT_FAILURE);
}
/* Now daemonize, but keep a communication channel open to
* print errors and exit with the proper status code.
*/
pid = fork();
if (pid < 0) {
error_report("Failed to fork: %s", strerror(errno));
exit(EXIT_FAILURE);
} else if (pid == 0) {
int saved_errno;
close(stderr_fd[0]);
/* Remember parent's stderr if we will be restoring it. */
if (opts.verbose /* fork_process is set */) {
opts.old_stderr = dup(STDERR_FILENO);
if (opts.old_stderr < 0) {
error_report("Could not dup original stderr: %s",
strerror(errno));
exit(EXIT_FAILURE);
}
}
ret = qemu_daemon(1, 0);
saved_errno = errno; /* dup2 will overwrite error below */
/* Temporarily redirect stderr to the parent's pipe... */
if (dup2(stderr_fd[1], STDERR_FILENO) < 0) {
char str[256];
snprintf(str, sizeof(str),
"%s: Failed to link stderr to the pipe: %s\n",
g_get_prgname(), strerror(errno));
/*
* We are unable to use error_report() here as we need to get
* stderr pointed to the parent's pipe. Write to that pipe
* manually.
*/
ret = write(stderr_fd[1], str, strlen(str));
exit(EXIT_FAILURE);
}
if (ret < 0) {
error_report("Failed to daemonize: %s", strerror(saved_errno));
exit(EXIT_FAILURE);
}
/* ... close the descriptor we inherited and go on. */
close(stderr_fd[1]);
} else {
bool errors = false;
char *buf;
/* In the parent. Print error messages from the child until
* it closes the pipe.
*/
close(stderr_fd[1]);
buf = g_malloc(1024);
while ((ret = read(stderr_fd[0], buf, 1024)) > 0) {
errors = true;
ret = qemu_write_full(STDERR_FILENO, buf, ret);
if (ret < 0) {
exit(EXIT_FAILURE);
}
}
if (ret < 0) {
error_report("Cannot read from daemon: %s",
strerror(errno));
exit(EXIT_FAILURE);
}
/* Usually the daemon should not print any message.
* Exit with zero status in that case.
*/
exit(errors);
}
#else /* WIN32 */
error_report("Unable to fork into background on Windows hosts");
exit(EXIT_FAILURE);
#endif /* WIN32 */
}
if (opts.device != NULL && sockpath == NULL) {
sockpath = g_malloc(128);
snprintf(sockpath, 128, SOCKET_PATH, basename(opts.device));
}
server = qio_net_listener_new();
if (socket_activation == 0) {
int backlog;
if (persistent || shared == 0) {
backlog = SOMAXCONN;
} else {
backlog = MIN(shared, SOMAXCONN);
}
#ifdef CONFIG_SELINUX
if (selinux_label && setsockcreatecon_raw(selinux_label) == -1) {
error_report("Cannot set SELinux socket create context to %s: %s",
selinux_label, strerror(errno));
exit(EXIT_FAILURE);
}
#endif
opts.saddr = nbd_build_socket_address(sockpath, bindto, port);
if (qio_net_listener_open_sync(server, opts.saddr, backlog,
&local_err) < 0) {
object_unref(OBJECT(server));
error_report_err(local_err);
exit(EXIT_FAILURE);
}
#ifdef CONFIG_SELINUX
if (selinux_label && setsockcreatecon_raw(NULL) == -1) {
error_report("Cannot clear SELinux socket create context: %s",
strerror(errno));
exit(EXIT_FAILURE);
}
#endif
} else {
size_t i;
/* See comment in check_socket_activation above. */
for (i = 0; i < socket_activation; i++) {
QIOChannelSocket *sioc;
sioc = qio_channel_socket_new_fd(FIRST_SOCKET_ACTIVATION_FD + i,
&local_err);
if (sioc == NULL) {
object_unref(OBJECT(server));
error_reportf_err(local_err,
"Failed to use socket activation: ");
exit(EXIT_FAILURE);
}
qio_net_listener_add(server, sioc);
object_unref(OBJECT(sioc));
}
}
qemu_init_main_loop(&error_fatal);
bdrv_init();
atexit(qemu_nbd_shutdown);
opts.srcpath = argv[optind];
if (imageOpts) {
QemuOpts *o;
if (fmt) {
error_report("--image-opts and -f are mutually exclusive");
exit(EXIT_FAILURE);
}
o = qemu_opts_parse_noisily(&file_opts, opts.srcpath, true);
if (!o) {
qemu_opts_reset(&file_opts);
exit(EXIT_FAILURE);
}
options = qemu_opts_to_qdict(o, NULL);
qemu_opts_reset(&file_opts);
blk = blk_new_open(NULL, NULL, options, flags, &local_err);
} else {
if (fmt) {
options = qdict_new();
qdict_put_str(options, "driver", fmt);
}
blk = blk_new_open(opts.srcpath, NULL, options, flags, &local_err);
}
if (!blk) {
error_reportf_err(local_err, "Failed to blk_new_open '%s': ",
argv[optind]);
exit(EXIT_FAILURE);
}
bs = blk_bs(blk);
if (dev_offset) {
QDict *raw_opts = qdict_new();
qdict_put_str(raw_opts, "driver", "raw");
qdict_put_str(raw_opts, "file", bs->node_name);
qdict_put_int(raw_opts, "offset", dev_offset);
aio_context_acquire(qemu_get_aio_context());
bs = bdrv_open(NULL, NULL, raw_opts, flags, &error_fatal);
aio_context_release(qemu_get_aio_context());
blk_remove_bs(blk);
blk_insert_bs(blk, bs, &error_fatal);
bdrv_unref(bs);
}
blk_set_enable_write_cache(blk, !writethrough);
if (sn_opts) {
ret = bdrv_snapshot_load_tmp(bs,
qemu_opt_get(sn_opts, SNAPSHOT_OPT_ID),
qemu_opt_get(sn_opts, SNAPSHOT_OPT_NAME),
&local_err);
} else if (sn_id_or_name) {
ret = bdrv_snapshot_load_tmp_by_id_or_name(bs, sn_id_or_name,
&local_err);
}
if (ret < 0) {
error_reportf_err(local_err, "Failed to load snapshot: ");
exit(EXIT_FAILURE);
}
bs->detect_zeroes = detect_zeroes;
nbd_server_is_qemu_nbd(shared);
export_opts = g_new(BlockExportOptions, 1);
*export_opts = (BlockExportOptions) {
.type = BLOCK_EXPORT_TYPE_NBD,
.id = g_strdup("qemu-nbd-export"),
.node_name = g_strdup(bdrv_get_node_name(bs)),
.has_writethrough = true,
.writethrough = writethrough,
.has_writable = true,
.writable = !readonly,
.u.nbd = {
.name = g_strdup(export_name),
.description = g_strdup(export_description),
.has_bitmaps = !!bitmaps,
.bitmaps = bitmaps,
.has_allocation_depth = alloc_depth,
.allocation_depth = alloc_depth,
},
};
blk_exp_add(export_opts, &error_fatal);
qapi_free_BlockExportOptions(export_opts);
if (opts.device) {
#if HAVE_NBD_DEVICE
ret = pthread_create(&client_thread, NULL, nbd_client_thread, &opts);
if (ret != 0) {
error_report("Failed to create client thread: %s", strerror(ret));
exit(EXIT_FAILURE);
}
#endif
} else {
/* Shut up GCC warnings. */
memset(&client_thread, 0, sizeof(client_thread));
}
nbd_update_server_watch();
if (pid_file_name) {
qemu_write_pidfile(pid_file_name, &error_fatal);
}
/* now when the initialization is (almost) complete, chdir("/")
* to free any busy filesystems */
if (chdir("/") < 0) {
error_report("Could not chdir to root directory: %s",
strerror(errno));
exit(EXIT_FAILURE);
}
if (opts.fork_process) {
nbd_client_release_pipe(opts.old_stderr);
}
state = RUNNING;
do {
main_loop_wait(false);
if (state == TERMINATE) {
blk_exp_close_all();
state = TERMINATED;
}
} while (state != TERMINATED);
blk_unref(blk);
if (sockpath) {
unlink(sockpath);
}
qemu_opts_del(sn_opts);
if (opts.device) {
void *result;
pthread_join(client_thread, &result);
ret = (intptr_t)result;
exit(ret);
} else {
exit(EXIT_SUCCESS);
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 53/75] hw/core: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (15 preceding siblings ...)
2023-10-13 7:48 ` [RFC PATCH 52/75] nbd: " Emmanouil Pitsidianakis
@ 2023-10-13 7:48 ` Emmanouil Pitsidianakis
2023-10-13 7:48 ` [RFC PATCH 54/75] hw/display: " Emmanouil Pitsidianakis
` (2 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block; +Cc: Emmanouil Pitsidianakis
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/core/loader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 4dd5a71fb7..559d63a1e2 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -625,138 +625,138 @@ toosmall:
/* Load a U-Boot image. */
static ssize_t load_uboot_image(const char *filename, hwaddr *ep,
hwaddr *loadaddr, int *is_linux,
uint8_t image_type,
uint64_t (*translate_fn)(void *, uint64_t),
void *translate_opaque, AddressSpace *as)
{
int fd;
ssize_t size;
hwaddr address;
uboot_image_header_t h;
uboot_image_header_t *hdr = &h;
uint8_t *data = NULL;
int ret = -1;
int do_uncompress = 0;
fd = open(filename, O_RDONLY | O_BINARY);
if (fd < 0)
return -1;
size = read(fd, hdr, sizeof(uboot_image_header_t));
if (size < sizeof(uboot_image_header_t)) {
goto out;
}
bswap_uboot_header(hdr);
if (hdr->ih_magic != IH_MAGIC)
goto out;
if (hdr->ih_type != image_type) {
if (!(image_type == IH_TYPE_KERNEL &&
hdr->ih_type == IH_TYPE_KERNEL_NOLOAD)) {
fprintf(stderr, "Wrong image type %d, expected %d\n", hdr->ih_type,
image_type);
goto out;
}
}
/* TODO: Implement other image types. */
switch (hdr->ih_type) {
case IH_TYPE_KERNEL_NOLOAD:
if (!loadaddr || *loadaddr == LOAD_UIMAGE_LOADADDR_INVALID) {
fprintf(stderr, "this image format (kernel_noload) cannot be "
"loaded on this machine type");
goto out;
}
hdr->ih_load = *loadaddr + sizeof(*hdr);
hdr->ih_ep += hdr->ih_load;
- /* fall through */
+ fallthrough;
case IH_TYPE_KERNEL:
address = hdr->ih_load;
if (translate_fn) {
address = translate_fn(translate_opaque, address);
}
if (loadaddr) {
*loadaddr = hdr->ih_load;
}
switch (hdr->ih_comp) {
case IH_COMP_NONE:
break;
case IH_COMP_GZIP:
do_uncompress = 1;
break;
default:
fprintf(stderr,
"Unable to load u-boot images with compression type %d\n",
hdr->ih_comp);
goto out;
}
if (ep) {
*ep = hdr->ih_ep;
}
/* TODO: Check CPU type. */
if (is_linux) {
if (hdr->ih_os == IH_OS_LINUX) {
*is_linux = 1;
} else if (hdr->ih_os == IH_OS_VXWORKS) {
/*
* VxWorks 7 uses the same boot interface as the Linux kernel
* on Arm (64-bit only), PowerPC and RISC-V architectures.
*/
switch (hdr->ih_arch) {
case IH_ARCH_ARM64:
case IH_ARCH_PPC:
case IH_ARCH_RISCV:
*is_linux = 1;
break;
default:
*is_linux = 0;
break;
}
} else {
*is_linux = 0;
}
}
break;
case IH_TYPE_RAMDISK:
address = *loadaddr;
break;
default:
fprintf(stderr, "Unsupported u-boot image type %d\n", hdr->ih_type);
goto out;
}
data = g_malloc(hdr->ih_size);
if (read(fd, data, hdr->ih_size) != hdr->ih_size) {
fprintf(stderr, "Error reading file\n");
goto out;
}
if (do_uncompress) {
uint8_t *compressed_data;
size_t max_bytes;
ssize_t bytes;
compressed_data = data;
max_bytes = UBOOT_MAX_GUNZIP_BYTES;
data = g_malloc(max_bytes);
bytes = gunzip(data, max_bytes, compressed_data, hdr->ih_size);
g_free(compressed_data);
if (bytes < 0) {
fprintf(stderr, "Unable to decompress gzipped image!\n");
goto out;
}
hdr->ih_size = bytes;
}
rom_add_blob_fixed_as(filename, data, hdr->ih_size, address, as);
ret = hdr->ih_size;
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 54/75] hw/display: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (16 preceding siblings ...)
2023-10-13 7:48 ` [RFC PATCH 53/75] hw/core: " Emmanouil Pitsidianakis
@ 2023-10-13 7:48 ` Emmanouil Pitsidianakis
2023-10-13 7:48 ` [RFC PATCH 55/75] hw/input: " Emmanouil Pitsidianakis
2023-10-13 7:48 ` [RFC PATCH 56/75] hw/net: " Emmanouil Pitsidianakis
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block
Cc: Emmanouil Pitsidianakis, Mark Cave-Ayland, Gerd Hoffmann
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/display/cg3.c | 2 +-
hw/display/cirrus_vga.c | 2 +-
hw/display/tcx.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/display/cg3.c b/hw/display/cg3.c
index 2e9656ae1c..53eb9831b2 100644
--- a/hw/display/cg3.c
+++ b/hw/display/cg3.c
@@ -199,65 +199,65 @@ static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
CG3State *s = opaque;
uint8_t regval;
int i;
trace_cg3_write(addr, val, size);
switch (addr) {
case CG3_REG_BT458_ADDR:
s->dac_index = val;
s->dac_state = 0;
break;
case CG3_REG_BT458_COLMAP:
/* This register can be written to as either a long word or a byte */
if (size == 1) {
val <<= 24;
}
for (i = 0; i < size; i++) {
regval = val >> 24;
switch (s->dac_state) {
case 0:
s->r[s->dac_index] = regval;
s->dac_state++;
break;
case 1:
s->g[s->dac_index] = regval;
s->dac_state++;
break;
case 2:
s->b[s->dac_index] = regval;
/* Index autoincrement */
s->dac_index = (s->dac_index + 1) & 0xff;
- /* fall through */
+ fallthrough;
default:
s->dac_state = 0;
break;
}
val <<= 8;
}
s->full_update = 1;
break;
case CG3_REG_FBC_CTRL:
s->regs[0] = val;
break;
case CG3_REG_FBC_STATUS:
if (s->regs[1] & CG3_SR_PENDING_INT) {
/* clear interrupt */
s->regs[1] &= ~CG3_SR_PENDING_INT;
qemu_irq_lower(s->irq);
}
break;
case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
s->regs[addr - 0x10] = val;
break;
default:
qemu_log_mask(LOG_UNIMP,
"cg3: Unimplemented register write "
"reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
addr, size, val);
break;
}
}
diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c
index b80f98b6c4..f1513a084c 100644
--- a/hw/display/cirrus_vga.c
+++ b/hw/display/cirrus_vga.c
@@ -1319,97 +1319,97 @@ static int cirrus_vga_read_sr(CirrusVGAState * s)
static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
{
switch (s->vga.sr_index) {
case 0x00: // Standard VGA
case 0x01: // Standard VGA
case 0x02: // Standard VGA
case 0x03: // Standard VGA
case 0x04: // Standard VGA
s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
if (s->vga.sr_index == 1)
s->vga.update_retrace_info(&s->vga);
break;
case 0x06: // Unlock Cirrus extensions
val &= 0x17;
if (val == 0x12) {
s->vga.sr[s->vga.sr_index] = 0x12;
} else {
s->vga.sr[s->vga.sr_index] = 0x0f;
}
break;
case 0x10:
case 0x30:
case 0x50:
case 0x70: // Graphics Cursor X
case 0x90:
case 0xb0:
case 0xd0:
case 0xf0: // Graphics Cursor X
s->vga.sr[0x10] = val;
s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
break;
case 0x11:
case 0x31:
case 0x51:
case 0x71: // Graphics Cursor Y
case 0x91:
case 0xb1:
case 0xd1:
case 0xf1: // Graphics Cursor Y
s->vga.sr[0x11] = val;
s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
break;
case 0x07: // Extended Sequencer Mode
cirrus_update_memory_access(s);
- /* fall through */
+ fallthrough;
case 0x08: // EEPROM Control
case 0x09: // Scratch Register 0
case 0x0a: // Scratch Register 1
case 0x0b: // VCLK 0
case 0x0c: // VCLK 1
case 0x0d: // VCLK 2
case 0x0e: // VCLK 3
case 0x0f: // DRAM Control
case 0x13: // Graphics Cursor Pattern Address
case 0x14: // Scratch Register 2
case 0x15: // Scratch Register 3
case 0x16: // Performance Tuning Register
case 0x18: // Signature Generator Control
case 0x19: // Signature Generator Result
case 0x1a: // Signature Generator Result
case 0x1b: // VCLK 0 Denominator & Post
case 0x1c: // VCLK 1 Denominator & Post
case 0x1d: // VCLK 2 Denominator & Post
case 0x1e: // VCLK 3 Denominator & Post
case 0x1f: // BIOS Write Enable and MCLK select
s->vga.sr[s->vga.sr_index] = val;
#ifdef DEBUG_CIRRUS
printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
s->vga.sr_index, val);
#endif
break;
case 0x12: // Graphics Cursor Attribute
s->vga.sr[0x12] = val;
s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW);
#ifdef DEBUG_CIRRUS
printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n",
val, s->vga.force_shadow);
#endif
break;
case 0x17: // Configuration Readback and Extended Control
s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
| (val & 0xc7);
cirrus_update_memory_access(s);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"cirrus: outport sr_index 0x%02x, sr_value 0x%02x\n",
s->vga.sr_index, val);
break;
}
}
/***************************************
*
* I/O access at 0x3c6
*
***************************************/
diff --git a/hw/display/tcx.c b/hw/display/tcx.c
index 1b27b64f6d..e21450d726 100644
--- a/hw/display/tcx.c
+++ b/hw/display/tcx.c
@@ -381,26 +381,26 @@ static void tcx_reset(DeviceState *d)
static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
unsigned size)
{
TCXState *s = opaque;
uint32_t val = 0;
switch (s->dac_state) {
case 0:
val = s->r[s->dac_index] << 24;
s->dac_state++;
break;
case 1:
val = s->g[s->dac_index] << 24;
s->dac_state++;
break;
case 2:
val = s->b[s->dac_index] << 24;
s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
- /* fall through */
+ fallthrough;
default:
s->dac_state = 0;
break;
}
return val;
}
@@ -408,43 +408,43 @@ static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
TCXState *s = opaque;
unsigned index;
switch (addr) {
case 0: /* Address */
s->dac_index = val >> 24;
s->dac_state = 0;
break;
case 4: /* Pixel colours */
case 12: /* Overlay (cursor) colours */
if (addr & 8) {
index = (s->dac_index & 3) + 256;
} else {
index = s->dac_index;
}
switch (s->dac_state) {
case 0:
s->r[index] = val >> 24;
update_palette_entries(s, index, index + 1);
s->dac_state++;
break;
case 1:
s->g[index] = val >> 24;
update_palette_entries(s, index, index + 1);
s->dac_state++;
break;
case 2:
s->b[index] = val >> 24;
update_palette_entries(s, index, index + 1);
s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
- /* fall through */
+ fallthrough;
default:
s->dac_state = 0;
break;
}
break;
default: /* Control registers */
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 55/75] hw/input: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (17 preceding siblings ...)
2023-10-13 7:48 ` [RFC PATCH 54/75] hw/display: " Emmanouil Pitsidianakis
@ 2023-10-13 7:48 ` Emmanouil Pitsidianakis
2023-10-13 7:48 ` [RFC PATCH 56/75] hw/net: " Emmanouil Pitsidianakis
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block; +Cc: Emmanouil Pitsidianakis, Peter Maydell
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/input/hid.c | 3 ++-
hw/input/tsc2005.c | 4 ++--
hw/input/tsc210x.c | 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/input/hid.c b/hw/input/hid.c
index a9c7dd1ce1..15fffc5dfb 100644
--- a/hw/input/hid.c
+++ b/hw/input/hid.c
@@ -250,88 +250,89 @@ static void hid_keyboard_event(DeviceState *dev, QemuConsole *src,
static void hid_keyboard_process_keycode(HIDState *hs)
{
uint8_t hid_code, index, key;
int i, keycode, slot;
if (hs->n == 0) {
return;
}
slot = hs->head & QUEUE_MASK; QUEUE_INCR(hs->head); hs->n--;
keycode = hs->kbd.keycodes[slot];
if (!hs->n) {
trace_hid_kbd_queue_empty();
}
key = keycode & 0x7f;
index = key | ((hs->kbd.modifiers & (1 << 8)) >> 1);
hid_code = hid_usage_keys[index];
hs->kbd.modifiers &= ~(1 << 8);
switch (hid_code) {
case 0x00:
return;
case 0xe0:
assert(key == 0x1d);
if (hs->kbd.modifiers & (1 << 9)) {
/* The hid_codes for the 0xe1/0x1d scancode sequence are 0xe9/0xe0.
* Here we're processing the second hid_code. By dropping bit 9
* and setting bit 8, the scancode after 0x1d will access the
* second half of the table.
*/
hs->kbd.modifiers ^= (1 << 8) | (1 << 9);
return;
}
/* fall through to process Ctrl_L */
+ fallthrough;
case 0xe1 ... 0xe7:
/* Ctrl_L/Ctrl_R, Shift_L/Shift_R, Alt_L/Alt_R, Win_L/Win_R.
* Handle releases here, or fall through to process presses.
*/
if (keycode & (1 << 7)) {
hs->kbd.modifiers &= ~(1 << (hid_code & 0x0f));
return;
}
- /* fall through */
+ fallthrough;
case 0xe8 ... 0xe9:
/* USB modifiers are just 1 byte long. Bits 8 and 9 of
* hs->kbd.modifiers implement a state machine that detects the
* 0xe0 and 0xe1/0x1d sequences. These bits do not follow the
* usual rules where bit 7 marks released keys; they are cleared
* elsewhere in the function as the state machine dictates.
*/
hs->kbd.modifiers |= 1 << (hid_code & 0x0f);
return;
case 0xea ... 0xef:
abort();
default:
break;
}
if (keycode & (1 << 7)) {
for (i = hs->kbd.keys - 1; i >= 0; i--) {
if (hs->kbd.key[i] == hid_code) {
hs->kbd.key[i] = hs->kbd.key[-- hs->kbd.keys];
hs->kbd.key[hs->kbd.keys] = 0x00;
break;
}
}
if (i < 0) {
return;
}
} else {
for (i = hs->kbd.keys - 1; i >= 0; i--) {
if (hs->kbd.key[i] == hid_code) {
break;
}
}
if (i < 0) {
if (hs->kbd.keys < sizeof(hs->kbd.key)) {
hs->kbd.key[hs->kbd.keys++] = hid_code;
}
} else {
return;
}
}
}
diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c
index db2b80e35f..4f3f1d9d12 100644
--- a/hw/input/tsc2005.c
+++ b/hw/input/tsc2005.c
@@ -234,70 +234,70 @@ static void tsc2005_write(TSC2005State *s, int reg, uint16_t data)
/* This handles most of the chip's logic. */
static void tsc2005_pin_update(TSC2005State *s)
{
int64_t expires;
bool pin_state;
switch (s->pin_func) {
case 0:
pin_state = !s->pressure && !!s->dav;
break;
case 1:
case 3:
default:
pin_state = !s->dav;
break;
case 2:
pin_state = !s->pressure;
}
if (pin_state != s->irq) {
s->irq = pin_state;
qemu_set_irq(s->pint, s->irq);
}
switch (s->nextfunction) {
case TSC_MODE_XYZ_SCAN:
case TSC_MODE_XY_SCAN:
if (!s->host_mode && s->dav)
s->enabled = false;
if (!s->pressure)
return;
- /* Fall through */
+ fallthrough;
case TSC_MODE_AUX_SCAN:
break;
case TSC_MODE_X:
case TSC_MODE_Y:
case TSC_MODE_Z:
if (!s->pressure)
return;
- /* Fall through */
+ fallthrough;
case TSC_MODE_AUX:
case TSC_MODE_TEMP1:
case TSC_MODE_TEMP2:
case TSC_MODE_X_TEST:
case TSC_MODE_Y_TEST:
case TSC_MODE_TS_TEST:
if (s->dav)
s->enabled = false;
break;
case TSC_MODE_RESERVED:
case TSC_MODE_XX_DRV:
case TSC_MODE_YY_DRV:
case TSC_MODE_YX_DRV:
default:
return;
}
if (!s->enabled || s->busy)
return;
s->busy = true;
s->precision = s->nextprecision;
s->function = s->nextfunction;
s->pdst = !s->pnd0; /* Synchronised on internal clock */
expires = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(NANOSECONDS_PER_SECOND >> 7);
timer_mod(s->timer, expires);
}
diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c
index 950506fb38..9ae426e1a6 100644
--- a/hw/input/tsc210x.c
+++ b/hw/input/tsc210x.c
@@ -774,70 +774,70 @@ static void tsc2102_audio_register_write(
/* This handles most of the chip logic. */
static void tsc210x_pin_update(TSC210xState *s)
{
int64_t expires;
bool pin_state;
switch (s->pin_func) {
case 0:
pin_state = s->pressure;
break;
case 1:
pin_state = !!s->dav;
break;
case 2:
default:
pin_state = s->pressure && !s->dav;
}
if (!s->enabled)
pin_state = false;
if (pin_state != s->irq) {
s->irq = pin_state;
qemu_set_irq(s->pint, !s->irq);
}
switch (s->nextfunction) {
case TSC_MODE_XY_SCAN:
case TSC_MODE_XYZ_SCAN:
if (!s->pressure)
return;
break;
case TSC_MODE_X:
case TSC_MODE_Y:
case TSC_MODE_Z:
if (!s->pressure)
return;
- /* Fall through */
+ fallthrough;
case TSC_MODE_BAT1:
case TSC_MODE_BAT2:
case TSC_MODE_AUX:
case TSC_MODE_TEMP1:
case TSC_MODE_TEMP2:
if (s->dav)
s->enabled = false;
break;
case TSC_MODE_AUX_SCAN:
case TSC_MODE_PORT_SCAN:
break;
case TSC_MODE_NO_SCAN:
case TSC_MODE_XX_DRV:
case TSC_MODE_YY_DRV:
case TSC_MODE_YX_DRV:
default:
return;
}
if (!s->enabled || s->busy || s->dav)
return;
s->busy = true;
s->precision = s->nextprecision;
s->function = s->nextfunction;
expires = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(NANOSECONDS_PER_SECOND >> 10);
timer_mod(s->timer, expires);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 56/75] hw/net: add fallthrough pseudo-keyword
[not found] <cover.1697034504.git.manos.pitsidianakis@linaro.org>
` (18 preceding siblings ...)
2023-10-13 7:48 ` [RFC PATCH 55/75] hw/input: " Emmanouil Pitsidianakis
@ 2023-10-13 7:48 ` Emmanouil Pitsidianakis
19 siblings, 0 replies; 22+ messages in thread
From: Emmanouil Pitsidianakis @ 2023-10-13 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-arm, qemu-block
Cc: Emmanouil Pitsidianakis, Edgar E. Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Pavel Pisa, Vikram Garhwal,
Akihiko Odaki, Sriram Yagnaraman, Dmitry Fleytman
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
---
hw/net/cadence_gem.c | 4 ++--
hw/net/can/can_sja1000.c | 4 ++--
hw/net/igb_core.c | 2 +-
hw/net/igbvf.c | 2 +-
hw/net/imx_fec.c | 2 +-
hw/net/net_rx_pkt.c | 2 +-
hw/net/pcnet.c | 2 +-
hw/net/rtl8139.c | 6 ++++--
hw/net/xilinx_ethlite.c | 2 +-
9 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index f445d8bb5e..a59991af5b 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -748,119 +748,119 @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
/* Figure out which queue the received data should be sent to */
static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
unsigned rxbufsize)
{
uint32_t reg;
bool matched, mismatched;
int i, j;
for (i = 0; i < s->num_type1_screeners; i++) {
reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i];
matched = false;
mismatched = false;
/* Screening is based on UDP Port */
if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
matched = true;
} else {
mismatched = true;
}
}
/* Screening is based on DS/TC */
if (reg & GEM_ST1R_DSTC_ENABLE) {
uint8_t dscp = rxbuf_ptr[14 + 1];
if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
GEM_ST1R_DSTC_MATCH_WIDTH)) {
matched = true;
} else {
mismatched = true;
}
}
if (matched && !mismatched) {
return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
}
}
for (i = 0; i < s->num_type2_screeners; i++) {
reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i];
matched = false;
mismatched = false;
if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
if (et_idx > s->num_type2_screeners) {
qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
"register index: %d\n", et_idx);
}
if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 +
et_idx]) {
matched = true;
} else {
mismatched = true;
}
}
/* Compare A, B, C */
for (j = 0; j < 3; j++) {
uint32_t cr0, cr1, mask;
uint16_t rx_cmp;
int offset;
int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6,
GEM_ST2R_COMPARE_WIDTH);
if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) {
continue;
}
if (cr_idx > s->num_type2_screeners) {
qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
"register index: %d\n", cr_idx);
}
cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
GEM_T2CW1_OFFSET_VALUE_WIDTH);
switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
case 3: /* Skip UDP header */
qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
"unimplemented - assuming UDP\n");
offset += 8;
- /* Fallthrough */
+ fallthrough;
case 2: /* skip the IP header */
offset += 20;
- /* Fallthrough */
+ fallthrough;
case 1: /* Count from after the ethertype */
offset += 14;
break;
case 0:
/* Offset from start of frame */
break;
}
rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
mask = extract32(cr0, 0, 16);
if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
matched = true;
} else {
mismatched = true;
}
}
if (matched && !mismatched) {
return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH);
}
}
/* We made it here, assume it's queue 0 */
return 0;
}
diff --git a/hw/net/can/can_sja1000.c b/hw/net/can/can_sja1000.c
index 73201f9139..14052b2700 100644
--- a/hw/net/can/can_sja1000.c
+++ b/hw/net/can/can_sja1000.c
@@ -422,235 +422,235 @@ static void can_sja_update_bas_irq(CanSJA1000State *s)
void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val,
unsigned size)
{
qemu_can_frame frame;
uint32_t tmp;
uint8_t tmp8, count;
DPRINTF("write 0x%02llx addr 0x%02x\n",
(unsigned long long)val, (unsigned int)addr);
if (addr > CAN_SJA_MEM_SIZE) {
return;
}
if (s->clock & 0x80) { /* PeliCAN Mode */
switch (addr) {
case SJA_MOD: /* Mode register */
s->mode = 0x1f & val;
if ((s->mode & 0x01) && ((val & 0x01) == 0)) {
/* Go to operation mode from reset mode. */
if (s->mode & (1 << 3)) { /* Single mode. */
/* For EFF */
can_sja_single_filter(&s->filter[0],
s->code_mask + 0, s->code_mask + 4, 1);
/* For SFF */
can_sja_single_filter(&s->filter[1],
s->code_mask + 0, s->code_mask + 4, 0);
can_bus_client_set_filters(&s->bus_client, s->filter, 2);
} else { /* Dual mode */
/* For EFF */
can_sja_dual_filter(&s->filter[0],
s->code_mask + 0, s->code_mask + 4, 1);
can_sja_dual_filter(&s->filter[1],
s->code_mask + 2, s->code_mask + 6, 1);
/* For SFF */
can_sja_dual_filter(&s->filter[2],
s->code_mask + 0, s->code_mask + 4, 0);
can_sja_dual_filter(&s->filter[3],
s->code_mask + 2, s->code_mask + 6, 0);
can_bus_client_set_filters(&s->bus_client, s->filter, 4);
}
s->rxmsg_cnt = 0;
s->rx_cnt = 0;
}
break;
case SJA_CMR: /* Command register. */
if (0x01 & val) { /* Send transmission request. */
buff2frame_pel(s->tx_buff, &frame);
if (DEBUG_FILTER) {
can_display_msg("[cansja]: Tx request " , &frame);
}
/*
* Clear transmission complete status,
* and Transmit Buffer Status.
* write to the backends.
*/
s->status_pel &= ~(3 << 2);
can_bus_client_send(&s->bus_client, &frame, 1);
/*
* Set transmission complete status
* and Transmit Buffer Status.
*/
s->status_pel |= (3 << 2);
/* Clear transmit status. */
s->status_pel &= ~(1 << 5);
s->interrupt_pel |= 0x02;
can_sja_update_pel_irq(s);
}
if (0x04 & val) { /* Release Receive Buffer */
if (s->rxmsg_cnt <= 0) {
break;
}
tmp8 = s->rx_buff[s->rxbuf_start]; count = 0;
if (tmp8 & (1 << 7)) { /* EFF */
count += 2;
}
count += 3;
if (!(tmp8 & (1 << 6))) { /* DATA */
count += (tmp8 & 0x0f);
}
if (DEBUG_FILTER) {
qemu_log("[cansja]: message released from "
"Rx FIFO cnt=%d, count=%d\n", s->rx_cnt, count);
}
s->rxbuf_start += count;
s->rxbuf_start %= SJA_RCV_BUF_LEN;
s->rx_cnt -= count;
s->rxmsg_cnt--;
if (s->rxmsg_cnt == 0) {
s->status_pel &= ~(1 << 0);
s->interrupt_pel &= ~(1 << 0);
can_sja_update_pel_irq(s);
}
}
if (0x08 & val) { /* Clear data overrun */
s->status_pel &= ~(1 << 1);
s->interrupt_pel &= ~(1 << 3);
can_sja_update_pel_irq(s);
}
break;
case SJA_SR: /* Status register */
case SJA_IR: /* Interrupt register */
break; /* Do nothing */
case SJA_IER: /* Interrupt enable register */
s->interrupt_en = val;
break;
case 16: /* RX frame information addr16-28. */
s->status_pel |= (1 << 5); /* Set transmit status. */
- /* fallthrough */
+ fallthrough;
case 17 ... 28:
if (s->mode & 0x01) { /* Reset mode */
if (addr < 24) {
s->code_mask[addr - 16] = val;
}
} else { /* Operation mode */
s->tx_buff[addr - 16] = val; /* Store to TX buffer directly. */
}
break;
case SJA_CDR:
s->clock = val;
break;
}
} else { /* Basic Mode */
switch (addr) {
case SJA_BCAN_CTR: /* Control register, addr 0 */
if ((s->control & 0x01) && ((val & 0x01) == 0)) {
/* Go to operation mode from reset mode. */
s->filter[0].can_id = (s->code << 3) & (0xff << 3);
tmp = (~(s->mask << 3)) & (0xff << 3);
tmp |= QEMU_CAN_EFF_FLAG; /* Only Basic CAN Frame. */
s->filter[0].can_mask = tmp;
can_bus_client_set_filters(&s->bus_client, s->filter, 1);
s->rxmsg_cnt = 0;
s->rx_cnt = 0;
} else if (!(s->control & 0x01) && !(val & 0x01)) {
can_sja_software_reset(s);
}
s->control = 0x1f & val;
break;
case SJA_BCAN_CMR: /* Command register, addr 1 */
if (0x01 & val) { /* Send transmission request. */
buff2frame_bas(s->tx_buff, &frame);
if (DEBUG_FILTER) {
can_display_msg("[cansja]: Tx request " , &frame);
}
/*
* Clear transmission complete status,
* and Transmit Buffer Status.
*/
s->status_bas &= ~(3 << 2);
/* write to the backends. */
can_bus_client_send(&s->bus_client, &frame, 1);
/*
* Set transmission complete status,
* and Transmit Buffer Status.
*/
s->status_bas |= (3 << 2);
/* Clear transmit status. */
s->status_bas &= ~(1 << 5);
s->interrupt_bas |= 0x02;
can_sja_update_bas_irq(s);
}
if (0x04 & val) { /* Release Receive Buffer */
if (s->rxmsg_cnt <= 0) {
break;
}
tmp8 = s->rx_buff[(s->rxbuf_start + 1) % SJA_RCV_BUF_LEN];
count = 2 + (tmp8 & 0x0f);
if (DEBUG_FILTER) {
qemu_log("[cansja]: message released from "
"Rx FIFO cnt=%d, count=%d\n", s->rx_cnt, count);
}
s->rxbuf_start += count;
s->rxbuf_start %= SJA_RCV_BUF_LEN;
s->rx_cnt -= count;
s->rxmsg_cnt--;
if (s->rxmsg_cnt == 0) {
s->status_bas &= ~(1 << 0);
s->interrupt_bas &= ~(1 << 0);
can_sja_update_bas_irq(s);
}
}
if (0x08 & val) { /* Clear data overrun */
s->status_bas &= ~(1 << 1);
s->interrupt_bas &= ~(1 << 3);
can_sja_update_bas_irq(s);
}
break;
case 4:
s->code = val;
break;
case 5:
s->mask = val;
break;
case 10:
s->status_bas |= (1 << 5); /* Set transmit status. */
- /* fallthrough */
+ fallthrough;
case 11 ... 19:
if ((s->control & 0x01) == 0) { /* Operation mode */
s->tx_buff[addr - 10] = val; /* Store to TX buffer directly. */
}
break;
case SJA_CDR:
s->clock = val;
break;
}
}
}
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index f6a5e2327b..1117f7cb59 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -1362,75 +1362,75 @@ static void
igb_build_rx_metadata_common(IGBCore *core,
struct NetRxPkt *pkt,
bool is_eop,
uint32_t *status_flags,
uint16_t *vlan_tag)
{
struct virtio_net_hdr *vhdr;
bool hasip4, hasip6, csum_valid;
EthL4HdrProto l4hdr_proto;
*status_flags = E1000_RXD_STAT_DD;
/* No additional metadata needed for non-EOP descriptors */
if (!is_eop) {
goto func_exit;
}
*status_flags |= E1000_RXD_STAT_EOP;
net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto);
/* VLAN state */
if (net_rx_pkt_is_vlan_stripped(pkt)) {
*status_flags |= E1000_RXD_STAT_VP;
*vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
trace_e1000e_rx_metadata_vlan(*vlan_tag);
}
/* RX CSO information */
if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
trace_e1000e_rx_metadata_ipv6_sum_disabled();
goto func_exit;
}
vhdr = net_rx_pkt_get_vhdr(pkt);
if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
!(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
trace_e1000e_rx_metadata_virthdr_no_csum_info();
igb_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto);
goto func_exit;
}
if (igb_rx_l3_cso_enabled(core)) {
*status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0;
} else {
trace_e1000e_rx_metadata_l3_cso_disabled();
}
if (igb_rx_l4_cso_enabled(core)) {
switch (l4hdr_proto) {
case ETH_L4_HDR_PROTO_SCTP:
if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
trace_e1000e_rx_metadata_l4_csum_validation_failed();
goto func_exit;
}
if (!csum_valid) {
*status_flags |= E1000_RXDEXT_STATERR_TCPE;
}
- /* fall through */
+ fallthrough;
case ETH_L4_HDR_PROTO_TCP:
*status_flags |= E1000_RXD_STAT_TCPCS;
break;
case ETH_L4_HDR_PROTO_UDP:
*status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
break;
default:
break;
}
} else {
trace_e1000e_rx_metadata_l4_cso_disabled();
}
diff --git a/hw/net/igbvf.c b/hw/net/igbvf.c
index d55e1e8a6a..ff68a4f3c5 100644
--- a/hw/net/igbvf.c
+++ b/hw/net/igbvf.c
@@ -62,139 +62,139 @@ struct IgbVfState {
static hwaddr vf_to_pf_addr(hwaddr addr, uint16_t vfn, bool write)
{
switch (addr) {
case E1000_CTRL:
case E1000_CTRL_DUP:
return E1000_PVTCTRL(vfn);
case E1000_EICS:
return E1000_PVTEICS(vfn);
case E1000_EIMS:
return E1000_PVTEIMS(vfn);
case E1000_EIMC:
return E1000_PVTEIMC(vfn);
case E1000_EIAC:
return E1000_PVTEIAC(vfn);
case E1000_EIAM:
return E1000_PVTEIAM(vfn);
case E1000_EICR:
return E1000_PVTEICR(vfn);
case E1000_EITR(0):
case E1000_EITR(1):
case E1000_EITR(2):
return E1000_EITR(22) + (addr - E1000_EITR(0)) - vfn * 0xC;
case E1000_IVAR0:
return E1000_VTIVAR + vfn * 4;
case E1000_IVAR_MISC:
return E1000_VTIVAR_MISC + vfn * 4;
case 0x0F04: /* PBACL */
return E1000_PBACLR;
case 0x0F0C: /* PSRTYPE */
return E1000_PSRTYPE(vfn);
case E1000_V2PMAILBOX(0):
return E1000_V2PMAILBOX(vfn);
case E1000_VMBMEM(0) ... E1000_VMBMEM(0) + 0x3F:
return addr + vfn * 0x40;
case E1000_RDBAL_A(0):
return E1000_RDBAL(vfn);
case E1000_RDBAL_A(1):
return E1000_RDBAL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RDBAH_A(0):
return E1000_RDBAH(vfn);
case E1000_RDBAH_A(1):
return E1000_RDBAH(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RDLEN_A(0):
return E1000_RDLEN(vfn);
case E1000_RDLEN_A(1):
return E1000_RDLEN(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_SRRCTL_A(0):
return E1000_SRRCTL(vfn);
case E1000_SRRCTL_A(1):
return E1000_SRRCTL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RDH_A(0):
return E1000_RDH(vfn);
case E1000_RDH_A(1):
return E1000_RDH(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RXCTL_A(0):
return E1000_RXCTL(vfn);
case E1000_RXCTL_A(1):
return E1000_RXCTL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RDT_A(0):
return E1000_RDT(vfn);
case E1000_RDT_A(1):
return E1000_RDT(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RXDCTL_A(0):
return E1000_RXDCTL(vfn);
case E1000_RXDCTL_A(1):
return E1000_RXDCTL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_RQDPC_A(0):
return E1000_RQDPC(vfn);
case E1000_RQDPC_A(1):
return E1000_RQDPC(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDBAL_A(0):
return E1000_TDBAL(vfn);
case E1000_TDBAL_A(1):
return E1000_TDBAL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDBAH_A(0):
return E1000_TDBAH(vfn);
case E1000_TDBAH_A(1):
return E1000_TDBAH(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDLEN_A(0):
return E1000_TDLEN(vfn);
case E1000_TDLEN_A(1):
return E1000_TDLEN(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDH_A(0):
return E1000_TDH(vfn);
case E1000_TDH_A(1):
return E1000_TDH(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TXCTL_A(0):
return E1000_TXCTL(vfn);
case E1000_TXCTL_A(1):
return E1000_TXCTL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDT_A(0):
return E1000_TDT(vfn);
case E1000_TDT_A(1):
return E1000_TDT(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TXDCTL_A(0):
return E1000_TXDCTL(vfn);
case E1000_TXDCTL_A(1):
return E1000_TXDCTL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDWBAL_A(0):
return E1000_TDWBAL(vfn);
case E1000_TDWBAL_A(1):
return E1000_TDWBAL(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_TDWBAH_A(0):
return E1000_TDWBAH(vfn);
case E1000_TDWBAH_A(1):
return E1000_TDWBAH(vfn + IGB_MAX_VF_FUNCTIONS);
case E1000_VFGPRC:
return E1000_PVFGPRC(vfn);
case E1000_VFGPTC:
return E1000_PVFGPTC(vfn);
case E1000_VFGORC:
return E1000_PVFGORC(vfn);
case E1000_VFGOTC:
return E1000_PVFGOTC(vfn);
case E1000_VFMPRC:
return E1000_PVFMPRC(vfn);
case E1000_VFGPRLBC:
return E1000_PVFGPRLBC(vfn);
case E1000_VFGPTLBC:
return E1000_PVFGPTLBC(vfn);
case E1000_VFGORLBC:
return E1000_PVFGORLBC(vfn);
case E1000_VFGOTLBC:
return E1000_PVFGOTLBC(vfn);
case E1000_STATUS:
case E1000_FRTIMER:
if (write) {
return HWADDR_MAX;
}
- /* fallthrough */
+ fallthrough;
case 0x34E8: /* PBTWAC */
case 0x24E8: /* PBRWAC */
return addr;
}
trace_igbvf_wrn_io_addr_unknown(addr);
return HWADDR_MAX;
}
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 5d1f1f104c..a7e8b06d48 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -888,170 +888,170 @@ static void imx_enet_write(IMXFECState *s, uint32_t index, uint32_t value)
static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
IMXFECState *s = IMX_FEC(opaque);
const bool single_tx_ring = !imx_eth_is_multi_tx_ring(s);
uint32_t index = offset >> 2;
trace_imx_eth_write(index, imx_eth_reg_name(s, index), value);
switch (index) {
case ENET_EIR:
s->regs[index] &= ~value;
break;
case ENET_EIMR:
s->regs[index] = value;
break;
case ENET_RDAR:
if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) {
if (!s->regs[index]) {
imx_eth_enable_rx(s, true);
}
} else {
s->regs[index] = 0;
}
break;
case ENET_TDAR1:
case ENET_TDAR2:
if (unlikely(single_tx_ring)) {
qemu_log_mask(LOG_GUEST_ERROR,
"[%s]%s: trying to access TDAR2 or TDAR1\n",
TYPE_IMX_FEC, __func__);
return;
}
- /* fall through */
+ fallthrough;
case ENET_TDAR:
if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) {
s->regs[index] = ENET_TDAR_TDAR;
imx_eth_do_tx(s, index);
}
s->regs[index] = 0;
break;
case ENET_ECR:
if (value & ENET_ECR_RESET) {
return imx_eth_reset(DEVICE(s));
}
s->regs[index] = value;
if ((s->regs[index] & ENET_ECR_ETHEREN) == 0) {
s->regs[ENET_RDAR] = 0;
s->rx_descriptor = s->regs[ENET_RDSR];
s->regs[ENET_TDAR] = 0;
s->regs[ENET_TDAR1] = 0;
s->regs[ENET_TDAR2] = 0;
s->tx_descriptor[0] = s->regs[ENET_TDSR];
s->tx_descriptor[1] = s->regs[ENET_TDSR1];
s->tx_descriptor[2] = s->regs[ENET_TDSR2];
}
break;
case ENET_MMFR:
s->regs[index] = value;
if (extract32(value, 29, 1)) {
/* This is a read operation */
s->regs[ENET_MMFR] = deposit32(s->regs[ENET_MMFR], 0, 16,
imx_phy_read(s,
extract32(value,
18, 10)));
} else {
/* This is a write operation */
imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
}
/* raise the interrupt as the PHY operation is done */
s->regs[ENET_EIR] |= ENET_INT_MII;
break;
case ENET_MSCR:
s->regs[index] = value & 0xfe;
break;
case ENET_MIBC:
/* TODO: Implement MIB. */
s->regs[index] = (value & 0x80000000) ? 0xc0000000 : 0;
break;
case ENET_RCR:
s->regs[index] = value & 0x07ff003f;
/* TODO: Implement LOOP mode. */
break;
case ENET_TCR:
/* We transmit immediately, so raise GRA immediately. */
s->regs[index] = value;
if (value & 1) {
s->regs[ENET_EIR] |= ENET_INT_GRA;
}
break;
case ENET_PALR:
s->regs[index] = value;
s->conf.macaddr.a[0] = value >> 24;
s->conf.macaddr.a[1] = value >> 16;
s->conf.macaddr.a[2] = value >> 8;
s->conf.macaddr.a[3] = value;
break;
case ENET_PAUR:
s->regs[index] = (value | 0x0000ffff) & 0xffff8808;
s->conf.macaddr.a[4] = value >> 24;
s->conf.macaddr.a[5] = value >> 16;
break;
case ENET_OPD:
s->regs[index] = (value & 0x0000ffff) | 0x00010000;
break;
case ENET_IAUR:
case ENET_IALR:
case ENET_GAUR:
case ENET_GALR:
/* TODO: implement MAC hash filtering. */
break;
case ENET_TFWR:
if (s->is_fec) {
s->regs[index] = value & 0x3;
} else {
s->regs[index] = value & 0x13f;
}
break;
case ENET_RDSR:
if (s->is_fec) {
s->regs[index] = value & ~3;
} else {
s->regs[index] = value & ~7;
}
s->rx_descriptor = s->regs[index];
break;
case ENET_TDSR:
if (s->is_fec) {
s->regs[index] = value & ~3;
} else {
s->regs[index] = value & ~7;
}
s->tx_descriptor[0] = s->regs[index];
break;
case ENET_TDSR1:
if (unlikely(single_tx_ring)) {
qemu_log_mask(LOG_GUEST_ERROR,
"[%s]%s: trying to access TDSR1\n",
TYPE_IMX_FEC, __func__);
return;
}
s->regs[index] = value & ~7;
s->tx_descriptor[1] = s->regs[index];
break;
case ENET_TDSR2:
if (unlikely(single_tx_ring)) {
qemu_log_mask(LOG_GUEST_ERROR,
"[%s]%s: trying to access TDSR2\n",
TYPE_IMX_FEC, __func__);
return;
}
s->regs[index] = value & ~7;
s->tx_descriptor[2] = s->regs[index];
break;
case ENET_MRBR:
s->regs[index] = value & 0x00003ff0;
break;
default:
if (s->is_fec) {
imx_fec_write(s, index, value);
} else {
imx_enet_write(s, index, value);
}
return;
}
imx_eth_update(s);
}
diff --git a/hw/net/net_rx_pkt.c b/hw/net/net_rx_pkt.c
index 32e5f3f9cf..52e2432c9b 100644
--- a/hw/net/net_rx_pkt.c
+++ b/hw/net/net_rx_pkt.c
@@ -591,36 +591,36 @@ _net_rx_pkt_validate_sctp_sum(struct NetRxPkt *pkt)
bool net_rx_pkt_validate_l4_csum(struct NetRxPkt *pkt, bool *csum_valid)
{
uint32_t csum;
trace_net_rx_pkt_l4_csum_validate_entry();
if (pkt->hasip4 && pkt->ip4hdr_info.fragment) {
trace_net_rx_pkt_l4_csum_validate_ip4_fragment();
return false;
}
switch (pkt->l4hdr_info.proto) {
case ETH_L4_HDR_PROTO_UDP:
if (pkt->l4hdr_info.hdr.udp.uh_sum == 0) {
trace_net_rx_pkt_l4_csum_validate_udp_with_no_checksum();
return false;
}
- /* fall through */
+ fallthrough;
case ETH_L4_HDR_PROTO_TCP:
csum = _net_rx_pkt_calc_l4_csum(pkt);
*csum_valid = ((csum == 0) || (csum == 0xFFFF));
break;
case ETH_L4_HDR_PROTO_SCTP:
*csum_valid = _net_rx_pkt_validate_sctp_sum(pkt);
break;
default:
trace_net_rx_pkt_l4_csum_validate_not_xxp();
return false;
}
trace_net_rx_pkt_l4_csum_validate_csum(*csum_valid);
return true;
}
diff --git a/hw/net/pcnet.c b/hw/net/pcnet.c
index 02828ae716..a32174ef93 100644
--- a/hw/net/pcnet.c
+++ b/hw/net/pcnet.c
@@ -1474,47 +1474,47 @@ static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap)
static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val)
{
rap &= 127;
#ifdef PCNET_DEBUG_BCR
printf("pcnet_bcr_writew rap=%d val=0x%04x\n", rap, val);
#endif
switch (rap) {
case BCR_SWS:
if (!(CSR_STOP(s) || CSR_SPND(s)))
return;
val &= ~0x0300;
switch (val & 0x00ff) {
case 0:
val |= 0x0200;
break;
case 1:
val |= 0x0100;
break;
case 2:
case 3:
val |= 0x0300;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "pcnet: Bad SWSTYLE=0x%02x\n",
val & 0xff);
val = 0x0200;
break;
}
#ifdef PCNET_DEBUG
printf("BCR_SWS=0x%04x\n", val);
#endif
- /* fall through */
+ fallthrough;
case BCR_LNKST:
case BCR_LED1:
case BCR_LED2:
case BCR_LED3:
case BCR_MC:
case BCR_FDC:
case BCR_BSBC:
case BCR_EECAS:
case BCR_PLAT:
s->bcr[rap] = val;
break;
default:
break;
}
}
diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c
index 4525fda383..42f19618b1 100644
--- a/hw/net/rtl8139.c
+++ b/hw/net/rtl8139.c
@@ -2435,29 +2435,31 @@ static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32
static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
uint32_t base, uint8_t addr,
int size)
{
uint32_t reg = (addr - base) / 4;
uint32_t offset = addr & 0x3;
uint32_t ret = 0;
if (addr & (size - 1)) {
DPRINTF("not implemented read for TxStatus/TxAddr "
"addr=0x%x size=0x%x\n", addr, size);
return ret;
}
switch (size) {
- case 1: /* fall through */
- case 2: /* fall through */
+ case 1:
+ fallthrough;
+ case 2:
+ fallthrough;
case 4:
ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1);
DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
reg, addr, size, ret);
break;
default:
DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
break;
}
return ret;
}
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index 89f4f3b254..5ae4032ec2 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -113,55 +113,55 @@ static void
eth_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_ethlite *s = opaque;
unsigned int base = 0;
uint32_t value = val64;
addr >>= 2;
switch (addr)
{
case R_TX_CTRL0:
case R_TX_CTRL1:
if (addr == R_TX_CTRL1)
base = 0x800 / 4;
D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
__func__, addr * 4, value));
if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
qemu_send_packet(qemu_get_queue(s->nic),
(void *) &s->regs[base],
s->regs[base + R_TX_LEN0]);
D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
} else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
}
/* We are fast and get ready pretty much immediately so
we actually never flip the S nor P bits to one. */
s->regs[addr] = value & ~(CTRL_P | CTRL_S);
break;
/* Keep these native. */
case R_RX_CTRL0:
case R_RX_CTRL1:
if (!(value & CTRL_S)) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
- /* fall through */
+ fallthrough;
case R_TX_LEN0:
case R_TX_LEN1:
case R_TX_GIE0:
D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
__func__, addr * 4, value));
s->regs[addr] = value;
break;
default:
s->regs[addr] = tswap32(value);
break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 22+ messages in thread