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Wed, 14 May 2025 14:27:31 +0000 (GMT) Message-ID: Date: Wed, 14 May 2025 09:27:30 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 03/50] ppc/xive2: Fix calculation of END queue sizes To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?UTF-8?B?RnLDqWTDqXJpYyBCYXJyYXQ=?= , Glenn Miles , Michael Kowal , Caleb Schlossin References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-4-npiggin@gmail.com> Content-Language: en-US From: Caleb Schlossin In-Reply-To: <20250512031100.439842-4-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: H7llsEZk7VqpJzSvtVTs4AGO23_scLZr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDEyNSBTYWx0ZWRfXwBZhedEK085n ggOfKNV4XaohjH9GGz/RnUKOZ/pjou/dgKVd+lp1LmCALLUd0IhImHTLXJCvyGH16HxLIVsmN1q WR0WveBmNc7j4IVj1SeSE6biJIPwOLTYjS7waMVCgrJNASGSEOJ776zAFoNCcPyo02GO6dVsU4Y vU/XF0Sby9yEx+IDMNOLnFa/dPp2HZfgGmoWrrKwiTNHWmbFwke41UoBcjPonXqTe0k2qhm70Vb PINEdnuycHhrA+4kWUnVGU2Mlmxd+BKODo2p+DVFVPIJx4FlJxTKERSks8JsQfj/GPVrdUqORG+ YN0Eg1OLDw6b5xOiR3188xe5hcAEY+qrUGJbps4L6nlq8h2qjPdPupkcvcr4lHyuxGeBcLN76XA 3JnDXXdi3lLkXUszhHdtS/Ec9HywPUhVuhyFWMFP0VuqLqP+Bb6iMWvD/NEq4hIfCjvi2MwU X-Proofpoint-GUID: A11kr9w19GXD8Rmjve6zu2yQLl5fjtJs X-Authority-Analysis: v=2.4 cv=QOxoRhLL c=1 sm=1 tr=0 ts=6824a855 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=ywi1dbFa605tUpZk3tQA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 clxscore=1011 mlxscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505140125 Received-SPF: pass client-ip=148.163.156.1; envelope-from=calebs@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 14 May 2025 11:10:33 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Looks good. Reviewed-by: Caleb Schlossin On 5/11/25 10:10 PM, Nicholas Piggin wrote: > From: Glenn Miles > > The queue size of an Event Notification Descriptor (END) > is determined by the 'cl' and QsZ fields of the END. > If the cl field is 1, then the queue size (in bytes) will > be the size of a cache line 128B * 2^QsZ and QsZ is limited > to 4. Otherwise, it will be 4096B * 2^QsZ with QsZ limited > to 12. > > Fixes: f8a233dedf2 ("ppc/xive2: Introduce a XIVE2 core framework") > Signed-off-by: Glenn Miles > --- > hw/intc/xive2.c | 25 +++++++++++++++++++------ > include/hw/ppc/xive2_regs.h | 1 + > 2 files changed, 20 insertions(+), 6 deletions(-) > > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index 7d584dfafa..790152a2a6 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -188,12 +188,27 @@ void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf) > (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); > } > > +#define XIVE2_QSIZE_CHUNK_CL 128 > +#define XIVE2_QSIZE_CHUNK_4k 4096 > +/* Calculate max number of queue entries for an END */ > +static uint32_t xive2_end_get_qentries(Xive2End *end) > +{ > + uint32_t w3 = end->w3; > + uint32_t qsize = xive_get_field32(END2_W3_QSIZE, w3); > + if (xive_get_field32(END2_W3_CL, w3)) { > + g_assert(qsize <= 4); > + return (XIVE2_QSIZE_CHUNK_CL << qsize) / sizeof(uint32_t); > + } else { > + g_assert(qsize <= 12); > + return (XIVE2_QSIZE_CHUNK_4k << qsize) / sizeof(uint32_t); > + } > +} > + > void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf) > { > uint64_t qaddr_base = xive2_end_qaddr(end); > - uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); > uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); > - uint32_t qentries = 1 << (qsize + 10); > + uint32_t qentries = xive2_end_get_qentries(end); > int i; > > /* > @@ -223,8 +238,7 @@ void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf) > uint64_t qaddr_base = xive2_end_qaddr(end); > uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); > uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); > - uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); > - uint32_t qentries = 1 << (qsize + 10); > + uint32_t qentries = xive2_end_get_qentries(end); > > uint32_t nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); > uint32_t nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); > @@ -341,13 +355,12 @@ void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx, GString *buf) > static void xive2_end_enqueue(Xive2End *end, uint32_t data) > { > uint64_t qaddr_base = xive2_end_qaddr(end); > - uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); > uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); > uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); > > uint64_t qaddr = qaddr_base + (qindex << 2); > uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); > - uint32_t qentries = 1 << (qsize + 10); > + uint32_t qentries = xive2_end_get_qentries(end); > > if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata), > MEMTXATTRS_UNSPECIFIED)) { > diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h > index b11395c563..3c28de8a30 100644 > --- a/include/hw/ppc/xive2_regs.h > +++ b/include/hw/ppc/xive2_regs.h > @@ -87,6 +87,7 @@ typedef struct Xive2End { > #define END2_W2_EQ_ADDR_HI PPC_BITMASK32(8, 31) > uint32_t w3; > #define END2_W3_EQ_ADDR_LO PPC_BITMASK32(0, 24) > +#define END2_W3_CL PPC_BIT32(27) > #define END2_W3_QSIZE PPC_BITMASK32(28, 31) > uint32_t w4; > #define END2_W4_END_BLOCK PPC_BITMASK32(4, 7)