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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbde1dc1dsm1220023f8f.87.2025.02.06.01.42.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Feb 2025 01:42:52 -0800 (PST) Message-ID: Date: Thu, 6 Feb 2025 10:42:50 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 RESEND 1/5] hw/core/machine: Reject thread level cache To: Zhao Liu , Paolo Bonzini , =?UTF-8?Q?Daniel_P_=2E_Berrang=C3=A9?= , Markus Armbruster , Igor Mammedov , "Michael S . Tsirkin" , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org References: <20250110145115.1574345-1-zhao1.liu@intel.com> <20250110145115.1574345-2-zhao1.liu@intel.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250110145115.1574345-2-zhao1.liu@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/1/25 15:51, Zhao Liu wrote: > Currently, neither i386 nor ARM have real hardware support for per- > thread cache, and there is no clear demand for this specific cache > topology. > > Additionally, since ARM even can't support this special cache topology > in device tree, it is unnecessary to support it at this moment, even > though per-thread cache might have potential scheduling benefits for > VMs without CPU affinity. > > Therefore, disable thread-level cache topology in the general machine > part. At present, i386 has not enabled SMP cache, so disabling the > thread parameter does not pose compatibility issues. > > In the future, if there is a clear demand for this feature, the correct > approach would be to add a new control field in MachineClass.smp_props > and enable it only for the machines that require it. > > Signed-off-by: Zhao Liu > --- > Changes since Patch v6: > * New commit to reject "thread" parameter when parse smp-cache. > --- > hw/core/machine-smp.c | 7 +++++++ > 1 file changed, 7 insertions(+) Reviewed-by: Philippe Mathieu-Daudé