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[2001:44b8:2176:c800:8228:b676:fb42:ee07]) by smtp.gmail.com with ESMTPSA id a11-20020aa7970b000000b00560cdb3784bsm2461490pfg.60.2022.11.11.21.17.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Nov 2022 21:17:50 -0800 (PST) Message-ID: Date: Sat, 12 Nov 2022 15:17:44 +1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v5 02/20] target/arm: ensure TCG IO accesses set appropriate MemTxAttrs Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org, Peter Maydell , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Cc: "open list:ARM TCG CPUs" References: <20221111182535.64844-1-alex.bennee@linaro.org> <20221111182535.64844-3-alex.bennee@linaro.org> From: Richard Henderson In-Reply-To: <20221111182535.64844-3-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/12/22 04:25, Alex Bennée wrote: > diff --git a/target/arm/ptw.c b/target/arm/ptw.c > index 3745ac9723..4b6683f90d 100644 > --- a/target/arm/ptw.c > +++ b/target/arm/ptw.c > @@ -2634,6 +2634,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, > s1_lgpgsz = result->f.lg_page_size; > cacheattrs1 = result->cacheattrs; > memset(result, 0, sizeof(*result)); > + result->f.attrs = MEMTXATTRS_CPU(env_cpu(env)); Ouch. This means that f.secure has been reset too, which would break Secure EL1 running under Secure EL2. I'll prepare a fix for 7.2... Anyway, Reviewed-by: Richard Henderson r~ > > ret = get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result, fi); > fi->s2addr = ipa; > @@ -2872,7 +2873,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, > .in_secure = arm_is_secure(env), > .in_debug = true, > }; > - GetPhysAddrResult res = {}; > + GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) }; > ARMMMUFaultInfo fi = {}; > bool ret; > > diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c > index 0f4f4fc809..5960269421 100644 > --- a/target/arm/tlb_helper.c > +++ b/target/arm/tlb_helper.c > @@ -208,7 +208,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > bool probe, uintptr_t retaddr) > { > ARMCPU *cpu = ARM_CPU(cs); > - GetPhysAddrResult res = {}; > + GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) }; > ARMMMUFaultInfo local_fi, *fi; > int ret; >