From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
alistair23@gmail.com, chihmin.chao@sifive.com,
palmer@dabbelt.com
Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org, wxy194768@alibaba-inc.com
Subject: Re: [PATCH v4 4/4] target/riscv: add vector configure instruction
Date: Wed, 12 Feb 2020 11:28:28 -0800 [thread overview]
Message-ID: <ae088484-c0ac-6e69-0b50-1d2e1455a591@linaro.org> (raw)
In-Reply-To: <bb1f595d-fbe8-93a2-c67c-25be7996aec3@c-sky.com>
On 2/12/20 12:09 AM, LIU Zhiwei wrote:
>
>
> On 2020/2/12 0:56, Richard Henderson wrote:
>> On 2/10/20 8:12 AM, LIU Zhiwei wrote:
>>> static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>>> - target_ulong *cs_base, uint32_t
>>> *flags)
>>> + target_ulong *cs_base, uint32_t
>>> *pflags)
>>> {
>>> + uint32_t flags = 0;
>>> + uint32_t vlmax;
>>> + uint8_t vl_eq_vlmax;
>> bool.
> OK.
>
> Is it clearer to use "bool" here? Or it's wrong to use "uint8_t "?
It is clearer. Using uint8_t makes me wonder what else you were going to put
in that variable, but the answer from the code below is nothing.
>>> + if (sew > cpu->cfg.elen) { /* only set vill bit. */
>>> + env->vext.vtype = FIELD_DP64(0, VTYPE, VILL, 1);
>>> + env->vext.vl = 0;
>>> + env->vext.vstart = 0;
>>> + return 0;
>>> + }
>> You're missing checks against EDIV, VILL and the RESERVED field == 0.
> This implementation does not support "Zvediv" . So I did not check it. I'm not
> sure if I should check(ediv==0).
>
> I missed check "VILL" filed. Fix up it next patch.
>
> I'm not quite sure if I should set VILL if the RESERVED field != 0.
The manual says
# If the vtype setting is not supported by the implementation,
# then the vill bit is set in vtype, the remaining bits in
# vtype are set to zero, and the vl register is also set
# to zero.
So yes, you most certainly have to check ediv == 0.
By extension, I believe the entire RESERVED field should be checked.
Otherwise, we don't get the same forward compatible behaviour for the next
vector extension beyond Zvediv.
r~
prev parent reply other threads:[~2020-02-12 19:29 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-10 8:12 [PATCH v4 0/4]target-riscv: support vector extension part 1 LIU Zhiwei
2020-02-10 8:12 ` [PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-02-11 15:53 ` Richard Henderson
2020-02-12 7:17 ` LIU Zhiwei
2020-02-10 8:12 ` [PATCH v4 2/4] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-02-11 15:56 ` Richard Henderson
2020-02-12 7:19 ` LIU Zhiwei
2020-02-18 22:34 ` Alistair Francis
2020-02-19 0:46 ` LIU Zhiwei
2020-02-19 1:05 ` Alistair Francis
2020-02-10 8:12 ` [PATCH v4 3/4] target/riscv: support vector extension csr LIU Zhiwei
2020-02-11 16:11 ` Richard Henderson
2020-02-12 7:23 ` LIU Zhiwei
2020-02-10 8:12 ` [PATCH v4 4/4] target/riscv: add vector configure instruction LIU Zhiwei
2020-02-11 16:56 ` Richard Henderson
2020-02-12 8:09 ` LIU Zhiwei
2020-02-12 19:28 ` Richard Henderson [this message]
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