From: Stefan Markovic <smarkovic@wavecomp.com>
To: Aleksandar Markovic <amarkovic@wavecomp.com>,
Aleksandar Markovic <aleksandar.markovic@rt-rk.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "aurelien@aurel32.net" <aurelien@aurel32.net>,
"richard.henderson@linaro.org" <richard.henderson@linaro.org>,
"jancraig@amazon.com" <jancraig@amazon.com>,
Petar Jovanovic <pjovanovic@wavecomp.com>
Subject: Re: [Qemu-devel] [PATCH v7 04/20] target/mips: Add and integrate MXU decoding engine placeholder
Date: Mon, 29 Oct 2018 10:09:55 +0000 [thread overview]
Message-ID: <ae0a75e1-4e9e-2ddc-c492-69d4a95b6d9c@wavecomp.com> (raw)
In-Reply-To: <BN6PR2201MB1251F15F9A76D3183A2ACBEAC6F20@BN6PR2201MB1251.namprd22.prod.outlook.com>
In that case, I guess this should be OK for now, as MXU support is
initiated by Craig and this will be
an easy add-on when he provide necessary information.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
On 28.10.18. 19:39, Aleksandar Markovic wrote:
>> Subject: Re: [PATCH v7 04/20] target/mips: Add and integrate MXU decoding engine > placeholder
>>
>>> Is the best way to implement this to include processing of MUL, CLZ,
>>> CLO, SDBBP instructions into decode_opc_mxu as their encodings aren't
>>> overlaid by MXU instructions considering MIPS SPECIAL2 instruction
>>> pool and MXU Instruction Set?
>> The problem is that we don't have the documentation for Ingenic's base
>> instruction set. My understanding is that Craig established necessity of
>> including non-MXU MUL into decode_opc_mxu() by experimentation,
>> or by looking at Ingenic's toolchain source code.
>>
>> Note that CLZ, CLO, SDBBP are moved from SPECIAL2 to another
>> place in opcode space in MIPS R6.
>>
>> Craig, can you offer any insight on CLZ, CLO, SDBBP in Ingenic's base
>> instruction set? They are in SPECIAL2 opcode space for MIPS pre-R6.
>>
>> Worse come to worst, I recommend adding "TODO" comment to an
>> appropriate place in decode_opc_mxu(), and go forward without handling
>> CLZ, CLO, SDBBP - given that all changes in this series are just the first
>> phase of implementing MXU support - they won't affect any production
>> code at this moment.
>>
> I think this comment should be added to the decode_opc_mxu(), within patch 11:
>
> /*
> * TODO: Investigate necessity of including handling of
> * CLZ, CLO, SDBB in this function, as they belong to
> * SPECIAL2 opcode space for regular pre-R6 MIPS ISAs.
> */
>
> Thanks,
> Aleksandar
next prev parent reply other threads:[~2018-10-29 10:10 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-24 12:18 [Qemu-devel] [PATCH v7 00/20] target/mips: Add limited support for Ingenic's MXU ASE Aleksandar Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 01/20] target/mips: Introduce MXU registers Aleksandar Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 02/20] target/mips: Define a bit for MXU in insn_flags Aleksandar Markovic
2018-10-28 18:05 ` Aleksandar Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 03/20] target/mips: Amend MXU instruction opcodes Aleksandar Markovic
2018-10-25 8:31 ` Stefan Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 04/20] target/mips: Add and integrate MXU decoding engine placeholder Aleksandar Markovic
2018-10-26 9:10 ` Stefan Markovic
2018-10-28 17:57 ` Aleksandar Markovic
2018-10-28 18:39 ` Aleksandar Markovic
2018-10-29 10:09 ` Stefan Markovic [this message]
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 05/20] target/mips: Add MXU decoding engine Aleksandar Markovic
2018-10-26 9:13 ` Stefan Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 06/20] target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1' Aleksandar Markovic
2018-10-26 9:16 ` Stefan Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 07/20] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2' Aleksandar Markovic
2018-10-28 17:37 ` Aleksandar Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 08/20] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2' Aleksandar Markovic
2018-10-26 9:17 ` Stefan Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 09/20] target/mips: Add bit encoding for MXU operand getting pattern 'optn2' Aleksandar Markovic
2018-10-28 17:36 ` Aleksandar Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 10/20] target/mips: Add bit encoding for MXU operand getting pattern 'optn3' Aleksandar Markovic
2018-10-28 17:35 ` Aleksandar Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 11/20] target/mips: Add emulation of non-MXU MULL within MXU decoding engine Aleksandar Markovic
2018-10-28 18:20 ` Aleksandar Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 12/20] target/mips: Add emulation of MXU instructions S32I2M and S32M2I Aleksandar Markovic
2018-10-28 18:19 ` Aleksandar Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 13/20] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch Aleksandar Markovic
2018-10-26 9:45 ` Stefan Markovic
2018-10-29 10:12 ` Stefan Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 14/20] target/mips: Add emulation of MXU instruction S8LDD Aleksandar Markovic
2018-10-25 8:08 ` Aleksandar Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 15/20] target/mips: Add emulation of MXU instruction D16MUL Aleksandar Markovic
2018-10-25 8:06 ` Aleksandar Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 16/20] target/mips: Add emulation of MXU instruction D16MAC Aleksandar Markovic
2018-10-25 8:07 ` Aleksandar Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 17/20] target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU Aleksandar Markovic
2018-10-25 8:09 ` Aleksandar Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 18/20] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR Aleksandar Markovic
2018-10-25 8:08 ` Aleksandar Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 19/20] target/mips: Move MXU_EN check one level higher Aleksandar Markovic
2018-10-26 9:53 ` Stefan Markovic
2018-10-24 12:18 ` [Qemu-devel] [PATCH v7 20/20] target/mips: Amend MXU ASE overview note Aleksandar Markovic
2018-10-26 9:56 ` Stefan Markovic
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