From: Paolo Bonzini <pbonzini@redhat.com>
To: Sebastian Andrzej Siewior <bigeasy@linutronix.de>, qemu-devel@nongnu.org
Cc: Eduardo Habkost <ehabkost@redhat.com>,
Richard Henderson <rth@twiddle.net>
Subject: Re: [PATCH] i386: Add CPUID bit for CLZERO and XSAVEERPTR
Date: Thu, 26 Sep 2019 13:06:34 +0200 [thread overview]
Message-ID: <ae0c4623-5b1f-ae6b-2062-12b13ecc7a77@redhat.com> (raw)
In-Reply-To: <20190925214948.22212-1-bigeasy@linutronix.de>
On 25/09/19 23:49, Sebastian Andrzej Siewior wrote:
> #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
>
> +#define CPUD_800_008_EBX_CLZERO (1U << 0) /* CLZERO instruction */
> +#define CPUD_800_008_EBX_XSAVEERPTR (1U << 2) /* Always save/restore FP error pointers */
> #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and
Well, there are obvious typos here but I can fix them for you.
Which processors have these?
Paolo
next prev parent reply other threads:[~2019-09-26 11:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-25 21:49 [PATCH] i386: Add CPUID bit for CLZERO and XSAVEERPTR Sebastian Andrzej Siewior
2019-09-26 11:05 ` Paolo Bonzini
2019-09-26 11:06 ` Paolo Bonzini [this message]
2019-09-26 11:21 ` Sebastian Andrzej Siewior
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