From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: Re: [PATCH v1 08/15] tcg/riscv: Add support for basic vector opcodes
Date: Wed, 14 Aug 2024 19:13:51 +1000 [thread overview]
Message-ID: <ae44194c-776a-48aa-8567-c56b5e7c4167@linaro.org> (raw)
In-Reply-To: <20240813113436.831-9-zhiwei_liu@linux.alibaba.com>
On 8/13/24 21:34, LIU Zhiwei wrote:
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
> tcg/riscv/tcg-target-con-set.h | 1 +
> tcg/riscv/tcg-target.c.inc | 33 +++++++++++++++++++++++++++++++++
> 2 files changed, 34 insertions(+)
>
> diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
> index d73a62b0f2..8a0de18257 100644
> --- a/tcg/riscv/tcg-target-con-set.h
> +++ b/tcg/riscv/tcg-target-con-set.h
> @@ -23,3 +23,4 @@ C_O1_I4(r, r, rI, rM, rM)
> C_O2_I4(r, r, rZ, rZ, rM, rM)
> C_O0_I2(v, r)
> C_O1_I1(v, r)
> +C_O1_I2(v, v, v)
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index f60913e805..650b5eff1a 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -289,6 +289,12 @@ typedef enum {
> OPC_VSE32_V = 0x6027 | V_SUMOP,
> OPC_VSE64_V = 0x7027 | V_SUMOP,
>
> + OPC_VADD_VV = 0x57 | V_OPIVV,
> + OPC_VSUB_VV = 0x8000057 | V_OPIVV,
> + OPC_VAND_VV = 0x24000057 | V_OPIVV,
> + OPC_VOR_VV = 0x28000057 | V_OPIVV,
> + OPC_VXOR_VV = 0x2c000057 | V_OPIVV,
> +
> OPC_VMV_V_V = 0x5e000057 | V_OPIVV,
> OPC_VMV_V_I = 0x5e000057 | V_OPIVI,
> OPC_VMV_V_X = 0x5e000057 | V_OPIVX,
> @@ -2158,6 +2164,21 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
> case INDEX_op_st_vec:
> tcg_out_st(s, type, a0, a1, a2);
> break;
> + case INDEX_op_add_vec:
> + tcg_out_opc_vv(s, OPC_VADD_VV, a0, a1, a2, true);
> + break;
> + case INDEX_op_sub_vec:
> + tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2, true);
> + break;
> + case INDEX_op_and_vec:
> + tcg_out_opc_vv(s, OPC_VAND_VV, a0, a1, a2, true);
> + break;
> + case INDEX_op_or_vec:
> + tcg_out_opc_vv(s, OPC_VOR_VV, a0, a1, a2, true);
> + break;
> + case INDEX_op_xor_vec:
> + tcg_out_opc_vv(s, OPC_VXOR_VV, a0, a1, a2, true);
> + break;
As with load/store/move, and/or/xor can avoid changing element type.
Thus I think the vtype setup before the switch is premature.
r~
next prev parent reply other threads:[~2024-08-14 9:14 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-13 11:34 [PATCH v1 00/15] tcg/riscv: Add support for vector LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 01/15] util: Add RISC-V vector extension probe in cpuinfo LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 02/15] tcg/op-gvec: Fix iteration step in 32-bit operation LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 03/15] tcg: Fix register allocation constraints LIU Zhiwei
2024-08-13 11:52 ` Richard Henderson
2024-08-14 0:58 ` LIU Zhiwei
2024-08-14 2:04 ` Richard Henderson
2024-08-14 2:27 ` LIU Zhiwei
2024-08-14 3:08 ` Richard Henderson
2024-08-14 3:30 ` LIU Zhiwei
2024-08-14 4:18 ` Richard Henderson
2024-08-14 7:47 ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 04/15] tcg/riscv: Add basic support for vector LIU Zhiwei
2024-08-13 12:19 ` Richard Henderson
2024-08-13 11:34 ` [PATCH v1 05/15] tcg/riscv: Add riscv vset{i}vli support LIU Zhiwei
2024-08-14 8:24 ` Richard Henderson
2024-08-19 1:34 ` LIU Zhiwei
2024-08-19 2:35 ` Richard Henderson
2024-08-19 2:53 ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 06/15] tcg/riscv: Implement vector load/store LIU Zhiwei
2024-08-14 9:01 ` Richard Henderson
2024-08-19 1:41 ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 07/15] tcg/riscv: Implement vector mov/dup{m/i} LIU Zhiwei
2024-08-14 9:11 ` Richard Henderson
2024-08-15 10:49 ` LIU Zhiwei
2024-08-20 9:00 ` Richard Henderson
2024-08-20 9:26 ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 08/15] tcg/riscv: Add support for basic vector opcodes LIU Zhiwei
2024-08-14 9:13 ` Richard Henderson [this message]
2024-08-20 1:56 ` LIU Zhiwei
2024-08-14 9:17 ` Richard Henderson
2024-08-20 1:57 ` LIU Zhiwei
2024-08-20 5:14 ` Richard Henderson
2024-08-13 11:34 ` [PATCH v1 09/15] tcg/riscv: Implement vector cmp ops LIU Zhiwei
2024-08-14 9:39 ` Richard Henderson
2024-08-27 7:50 ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 10/15] tcg/riscv: Implement vector not/neg ops LIU Zhiwei
2024-08-14 9:45 ` Richard Henderson
2024-08-27 7:55 ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 11/15] tcg/riscv: Implement vector sat/mul ops LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 12/15] tcg/riscv: Implement vector min/max ops LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 13/15] tcg/riscv: Implement vector shs/v ops LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 14/15] tcg/riscv: Implement vector roti/v/x shi ops LIU Zhiwei
2024-08-14 9:55 ` Richard Henderson
2024-08-27 7:57 ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 15/15] tcg/riscv: Enable vector TCG host-native LIU Zhiwei
2024-08-14 10:15 ` Richard Henderson
2024-08-27 8:31 ` LIU Zhiwei
2024-08-28 23:35 ` Richard Henderson
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