* [PATCH] RISC-V: XTheadMemPair: Remove register restrictions for store-pair
@ 2023-02-20 9:56 Christoph Muellner
2023-02-20 10:54 ` LIU Zhiwei
2023-03-02 1:09 ` Palmer Dabbelt
0 siblings, 2 replies; 3+ messages in thread
From: Christoph Muellner @ 2023-02-20 9:56 UTC (permalink / raw)
To: qemu-riscv, qemu-devel, Alistair Francis, Bin Meng,
Philipp Tomsich, Manolis Tsamis, Palmer Dabbelt,
Richard Henderson, Cooper Qu, Lifang Xia, Yunhai Shang,
Zhiwei Liu
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
The XTheadMemPair does not define any restrictions for store-pair
instructions (th.sdd or th.swd). However, the current code enforces
the restrictions that are required for load-pair instructions.
Let's fix this by removing this code.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
target/riscv/insn_trans/trans_xthead.c.inc | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
index be87c34f56..cf1731b08d 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -980,10 +980,6 @@ static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a)
static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
int shamt)
{
- if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
- return false;
- }
-
TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE);
TCGv addr1 = tcg_temp_new();
--
2.39.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: XTheadMemPair: Remove register restrictions for store-pair
2023-02-20 9:56 [PATCH] RISC-V: XTheadMemPair: Remove register restrictions for store-pair Christoph Muellner
@ 2023-02-20 10:54 ` LIU Zhiwei
2023-03-02 1:09 ` Palmer Dabbelt
1 sibling, 0 replies; 3+ messages in thread
From: LIU Zhiwei @ 2023-02-20 10:54 UTC (permalink / raw)
To: Christoph Muellner, qemu-riscv, qemu-devel, Alistair Francis,
Bin Meng, Philipp Tomsich, Manolis Tsamis, Palmer Dabbelt,
Richard Henderson, Cooper Qu, Lifang Xia, Yunhai Shang
On 2023/2/20 17:56, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> The XTheadMemPair does not define any restrictions for store-pair
> instructions (th.sdd or th.swd). However, the current code enforces
> the restrictions that are required for load-pair instructions.
> Let's fix this by removing this code.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> target/riscv/insn_trans/trans_xthead.c.inc | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
> index be87c34f56..cf1731b08d 100644
> --- a/target/riscv/insn_trans/trans_xthead.c.inc
> +++ b/target/riscv/insn_trans/trans_xthead.c.inc
> @@ -980,10 +980,6 @@ static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a)
> static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
> int shamt)
> {
> - if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
> - return false;
> - }
> -
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
> TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE);
> TCGv addr1 = tcg_temp_new();
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: XTheadMemPair: Remove register restrictions for store-pair
2023-02-20 9:56 [PATCH] RISC-V: XTheadMemPair: Remove register restrictions for store-pair Christoph Muellner
2023-02-20 10:54 ` LIU Zhiwei
@ 2023-03-02 1:09 ` Palmer Dabbelt
1 sibling, 0 replies; 3+ messages in thread
From: Palmer Dabbelt @ 2023-03-02 1:09 UTC (permalink / raw)
To: christoph.muellner
Cc: qemu-riscv, qemu-devel, Alistair Francis, bin.meng,
philipp.tomsich, manolis.tsamis, Richard Henderson, cooper.qu,
lifang_xia, yunhai, zhiwei_liu, christoph.muellner
On Mon, 20 Feb 2023 01:56:12 PST (-0800), christoph.muellner@vrull.eu wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> The XTheadMemPair does not define any restrictions for store-pair
> instructions (th.sdd or th.swd). However, the current code enforces
> the restrictions that are required for load-pair instructions.
> Let's fix this by removing this code.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> target/riscv/insn_trans/trans_xthead.c.inc | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
> index be87c34f56..cf1731b08d 100644
> --- a/target/riscv/insn_trans/trans_xthead.c.inc
> +++ b/target/riscv/insn_trans/trans_xthead.c.inc
> @@ -980,10 +980,6 @@ static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a)
> static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
> int shamt)
> {
> - if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
> - return false;
> - }
> -
> TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
> TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE);
> TCGv addr1 = tcg_temp_new();
Thanks, this is queued in riscv-to-apply.next .
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-02-20 9:56 [PATCH] RISC-V: XTheadMemPair: Remove register restrictions for store-pair Christoph Muellner
2023-02-20 10:54 ` LIU Zhiwei
2023-03-02 1:09 ` Palmer Dabbelt
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