From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: david@redhat.com
Subject: Re: [Qemu-devel] [PATCH 03/38] tcg: Return bool success from tcg_out_mov
Date: Sat, 20 Apr 2019 12:56:11 +0200 [thread overview]
Message-ID: <ae76140a-b8cb-744f-58c7-43cb9ec1621a@redhat.com> (raw)
In-Reply-To: <20190420073442.7488-4-richard.henderson@linaro.org>
On 4/20/19 9:34 AM, Richard Henderson wrote:
> This patch merely changes the interface, aborting on all failures,
> of which there are currently none.
>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> tcg/aarch64/tcg-target.inc.c | 5 +++--
> tcg/arm/tcg-target.inc.c | 7 +++++--
> tcg/i386/tcg-target.inc.c | 5 +++--
> tcg/mips/tcg-target.inc.c | 3 ++-
> tcg/ppc/tcg-target.inc.c | 3 ++-
> tcg/riscv/tcg-target.inc.c | 5 +++--
> tcg/s390/tcg-target.inc.c | 3 ++-
> tcg/sparc/tcg-target.inc.c | 3 ++-
> tcg/tcg.c | 14 ++++++++++----
> tcg/tci/tcg-target.inc.c | 3 ++-
> 10 files changed, 34 insertions(+), 17 deletions(-)
>
> diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
> index 8b93598bce..b2d3f9c0a5 100644
> --- a/tcg/aarch64/tcg-target.inc.c
> +++ b/tcg/aarch64/tcg-target.inc.c
> @@ -938,10 +938,10 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,
> tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP);
> }
>
> -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> {
> if (ret == arg) {
> - return;
> + return true;
> }
> switch (type) {
> case TCG_TYPE_I32:
> @@ -970,6 +970,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> default:
> g_assert_not_reached();
> }
> + return true;
> }
>
> static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
> diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
> index 6873b0cf95..34e6652142 100644
> --- a/tcg/arm/tcg-target.inc.c
> +++ b/tcg/arm/tcg-target.inc.c
> @@ -2275,10 +2275,13 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
> return false;
> }
>
> -static inline void tcg_out_mov(TCGContext *s, TCGType type,
> +static inline bool tcg_out_mov(TCGContext *s, TCGType type,
> TCGReg ret, TCGReg arg)
> {
> - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
> + if (ret != arg) {
> + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
> + }
> + return true;
> }
>
> static inline void tcg_out_movi(TCGContext *s, TCGType type,
> diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
> index 1fa833840e..817a167767 100644
> --- a/tcg/i386/tcg-target.inc.c
> +++ b/tcg/i386/tcg-target.inc.c
> @@ -809,12 +809,12 @@ static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src)
> tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src);
> }
>
> -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> {
> int rexw = 0;
>
> if (arg == ret) {
> - return;
> + return true;
> }
> switch (type) {
> case TCG_TYPE_I64:
> @@ -852,6 +852,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> default:
> g_assert_not_reached();
> }
> + return true;
> }
>
> static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
> diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
> index 8a92e916dd..f31ebb43bf 100644
> --- a/tcg/mips/tcg-target.inc.c
> +++ b/tcg/mips/tcg-target.inc.c
> @@ -558,13 +558,14 @@ static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
> tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
> }
>
> -static inline void tcg_out_mov(TCGContext *s, TCGType type,
> +static inline bool tcg_out_mov(TCGContext *s, TCGType type,
> TCGReg ret, TCGReg arg)
> {
> /* Simple reg-reg move, optimising out the 'do nothing' case */
> if (ret != arg) {
> tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
> }
> + return true;
> }
>
> static void tcg_out_movi(TCGContext *s, TCGType type,
> diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
> index 773690f1d9..ec8e336be8 100644
> --- a/tcg/ppc/tcg-target.inc.c
> +++ b/tcg/ppc/tcg-target.inc.c
> @@ -566,12 +566,13 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
> static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
> TCGReg base, tcg_target_long offset);
>
> -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> {
> tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
> if (ret != arg) {
> tcg_out32(s, OR | SAB(arg, ret, arg));
> }
> + return true;
> }
>
> static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
> diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
> index b785f4acb7..e2bf1c2c6e 100644
> --- a/tcg/riscv/tcg-target.inc.c
> +++ b/tcg/riscv/tcg-target.inc.c
> @@ -515,10 +515,10 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
> * TCG intrinsics
> */
>
> -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> {
> if (ret == arg) {
> - return;
> + return true;
> }
> switch (type) {
> case TCG_TYPE_I32:
> @@ -528,6 +528,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> default:
> g_assert_not_reached();
> }
> + return true;
> }
>
> static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
> diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
> index 7db90b3bae..eb22188d1d 100644
> --- a/tcg/s390/tcg-target.inc.c
> +++ b/tcg/s390/tcg-target.inc.c
> @@ -548,7 +548,7 @@ static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
> tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm);
> }
>
> -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
> +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
> {
> if (src != dst) {
> if (type == TCG_TYPE_I32) {
> @@ -557,6 +557,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
> tcg_out_insn(s, RRE, LGR, dst, src);
> }
> }
> + return true;
> }
>
> static const S390Opcode lli_insns[4] = {
> diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
> index 7a61839dc1..83295955a7 100644
> --- a/tcg/sparc/tcg-target.inc.c
> +++ b/tcg/sparc/tcg-target.inc.c
> @@ -407,12 +407,13 @@ static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1,
> | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
> }
>
> -static inline void tcg_out_mov(TCGContext *s, TCGType type,
> +static inline bool tcg_out_mov(TCGContext *s, TCGType type,
> TCGReg ret, TCGReg arg)
> {
> if (ret != arg) {
> tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
> }
> + return true;
> }
>
> static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg)
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 4f77a957b0..b083faacd2 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -102,7 +102,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
> const char *ct_str, TCGType type);
> static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
> intptr_t arg2);
> -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
> +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
> static void tcg_out_movi(TCGContext *s, TCGType type,
> TCGReg ret, tcg_target_long arg);
> static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> @@ -3372,7 +3372,9 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
> allocated_regs, preferred_regs,
> ots->indirect_base);
> }
> - tcg_out_mov(s, otype, ots->reg, ts->reg);
> + if (!tcg_out_mov(s, otype, ots->reg, ts->reg)) {
> + abort();
> + }
> }
> ots->val_type = TEMP_VAL_REG;
> ots->mem_coherent = 0;
> @@ -3472,7 +3474,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
> i_allocated_regs, 0);
> reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
> o_preferred_regs, ts->indirect_base);
> - tcg_out_mov(s, ts->type, reg, ts->reg);
> + if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
> + abort();
> + }
> }
> new_args[i] = reg;
> const_args[i] = 0;
> @@ -3629,7 +3633,9 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
> if (ts->val_type == TEMP_VAL_REG) {
> if (ts->reg != reg) {
> tcg_reg_free(s, reg, allocated_regs);
> - tcg_out_mov(s, ts->type, reg, ts->reg);
> + if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
> + abort();
> + }
> }
> } else {
> TCGRegSet arg_set = 0;
> diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c
> index 0015a98485..992d50cb1e 100644
> --- a/tcg/tci/tcg-target.inc.c
> +++ b/tcg/tci/tcg-target.inc.c
> @@ -509,7 +509,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
> old_code_ptr[1] = s->code_ptr - old_code_ptr;
> }
>
> -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> {
> uint8_t *old_code_ptr = s->code_ptr;
> tcg_debug_assert(ret != arg);
> @@ -521,6 +521,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> tcg_out_r(s, ret);
> tcg_out_r(s, arg);
> old_code_ptr[1] = s->code_ptr - old_code_ptr;
> + return true;
> }
>
> static void tcg_out_movi(TCGContext *s, TCGType type,
>
next prev parent reply other threads:[~2019-04-20 10:56 UTC|newest]
Thread overview: 138+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-20 7:34 [Qemu-devel] [PATCH 00/38] tcg vector improvements Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 01/38] target/arm: Fill in .opc for cmtst_op Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-23 8:00 ` David Hildenbrand
2019-04-23 8:00 ` David Hildenbrand
2019-04-20 7:34 ` [Qemu-devel] [PATCH 02/38] tcg: Assert fixed_reg is read-only Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-23 8:03 ` David Hildenbrand
2019-04-23 8:03 ` David Hildenbrand
2019-04-20 7:34 ` [Qemu-devel] [PATCH 03/38] tcg: Return bool success from tcg_out_mov Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 10:56 ` Philippe Mathieu-Daudé [this message]
2019-04-20 10:56 ` Philippe Mathieu-Daudé
2019-04-23 8:27 ` David Hildenbrand
2019-04-23 8:27 ` David Hildenbrand
2019-04-20 7:34 ` [Qemu-devel] [PATCH 04/38] tcg: Support cross-class moves without instruction support Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-23 8:29 ` David Hildenbrand
2019-04-23 8:29 ` David Hildenbrand
2019-04-20 7:34 ` [Qemu-devel] [PATCH 05/38] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-23 8:33 ` David Hildenbrand
2019-04-23 8:33 ` David Hildenbrand
2019-04-20 7:34 ` [Qemu-devel] [PATCH 06/38] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 07/38] tcg: Manually expand INDEX_op_dup_vec Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 08/38] tcg: Add tcg_out_dupm_vec to the backend interface Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 09/38] tcg/i386: Implement tcg_out_dupm_vec Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 10/38] tcg/aarch64: " Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 11/38] tcg: Add INDEX_op_dup_mem_vec Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 12/38] tcg: Add gvec expanders for variable shift Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-23 19:04 ` David Hildenbrand
2019-04-23 19:04 ` David Hildenbrand
2019-04-23 19:28 ` Richard Henderson
2019-04-23 19:28 ` Richard Henderson
2019-04-23 21:02 ` David Hildenbrand
2019-04-23 21:02 ` David Hildenbrand
2019-04-23 21:40 ` Richard Henderson
2019-04-23 21:40 ` Richard Henderson
2019-04-23 21:57 ` David Hildenbrand
2019-04-23 21:57 ` David Hildenbrand
2019-04-20 7:34 ` [Qemu-devel] [PATCH 13/38] tcg/i386: Support vector variable shift opcodes Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 14/38] tcg/aarch64: " Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 15/38] tcg: Implement tcg_gen_gvec_3i() Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 16/38] tcg: Specify optional vector requirements with a list Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 17/38] tcg: Add gvec expanders for vector shift by scalar Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-23 18:58 ` David Hildenbrand
2019-04-23 18:58 ` David Hildenbrand
2019-04-23 19:21 ` Richard Henderson
2019-04-23 19:21 ` Richard Henderson
2019-04-23 21:05 ` David Hildenbrand
2019-04-23 21:05 ` David Hildenbrand
2019-04-20 7:34 ` [Qemu-devel] [PATCH 18/38] tcg/i386: Support vector scalar shift opcodes Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 19/38] tcg: Add support for integer absolute value Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-23 8:52 ` Philippe Mathieu-Daudé
2019-04-23 8:52 ` Philippe Mathieu-Daudé
2019-04-23 18:37 ` David Hildenbrand
2019-04-23 18:37 ` David Hildenbrand
2019-04-23 22:09 ` Philippe Mathieu-Daudé
2019-04-23 22:09 ` Philippe Mathieu-Daudé
2019-04-23 22:29 ` Richard Henderson
2019-04-23 22:29 ` Richard Henderson
2019-04-23 23:05 ` Philippe Mathieu-Daudé
2019-04-23 23:05 ` Philippe Mathieu-Daudé
2019-04-20 7:34 ` [Qemu-devel] [PATCH 20/38] tcg: Add support for vector " Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-23 18:35 ` David Hildenbrand
2019-04-23 18:35 ` David Hildenbrand
2019-04-20 7:34 ` [Qemu-devel] [PATCH 21/38] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 22/38] target/cris: Use tcg_gen_abs_tl Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-23 10:09 ` Philippe Mathieu-Daudé
2019-04-23 10:09 ` Philippe Mathieu-Daudé
2019-04-20 7:34 ` [Qemu-devel] [PATCH 23/38] target/ppc: " Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 24/38] target/s390x: Use tcg_gen_abs_i64 Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-23 18:40 ` David Hildenbrand
2019-04-23 18:40 ` David Hildenbrand
2019-04-23 22:12 ` Philippe Mathieu-Daudé
2019-04-23 22:12 ` Philippe Mathieu-Daudé
2019-04-20 7:34 ` [Qemu-devel] [PATCH 25/38] target/xtensa: Use tcg_gen_abs_i32 Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-23 22:14 ` Philippe Mathieu-Daudé
2019-04-23 22:14 ` Philippe Mathieu-Daudé
2019-04-20 7:34 ` [Qemu-devel] [PATCH 26/38] tcg/i386: Support vector absolute value Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 27/38] tcg/aarch64: " Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 28/38] tcg: Add support for vector comparison select Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 29/38] tcg/i386: Support vector comparison select value Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 30/38] tcg/aarch64: " Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 31/38] target/ppc: Use vector variable shifts for VS{L, R, RA}{B, H, W, D} Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 32/38] target/arm: Vectorize USHL and SSHL Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 33/38] tcg/aarch64: Do not advertise minmax for MO_64 Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 34/38] tcg: Do not recreate INDEX_op_neg_vec unless supported Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 35/38] tcg: Introduce do_op3_nofail for vector expansion Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 36/38] tcg: Expand vector minmax using cmp+cmpsel Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 37/38] tcg/aarch64: Use MVNI for expansion of dupi Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 7:34 ` [Qemu-devel] [PATCH 38/38] tcg/aarch64: Use ORRI and BICI for vector logical operations Richard Henderson
2019-04-20 7:34 ` Richard Henderson
2019-04-20 8:09 ` [Qemu-devel] [PATCH 00/38] tcg vector improvements no-reply
2019-04-20 8:09 ` no-reply
2019-04-23 19:15 ` David Hildenbrand
2019-04-23 19:15 ` David Hildenbrand
2019-04-23 20:26 ` Richard Henderson
2019-04-23 20:26 ` Richard Henderson
2019-04-23 20:31 ` David Hildenbrand
2019-04-23 20:31 ` David Hildenbrand
2019-04-29 19:28 ` David Hildenbrand
2019-04-29 19:28 ` David Hildenbrand
2019-04-29 20:19 ` Richard Henderson
2019-04-29 20:19 ` Richard Henderson
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for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).