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From: Jiangyifei <jiangyifei@huawei.com>
To: Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: Zhanghailiang <zhang.zhanghailiang@huawei.com>,
	"sagark@eecs.berkeley.edu" <sagark@eecs.berkeley.edu>,
	"kbastian@mail.uni-paderborn.de" <kbastian@mail.uni-paderborn.de>,
	"Zhangxiaofeng \(F\)" <victor.zhangxiaofeng@huawei.com>,
	"Alistair.Francis@wdc.com" <Alistair.Francis@wdc.com>,
	yinyipeng <yinyipeng1@huawei.com>,
	"palmer@dabbelt.com" <palmer@dabbelt.com>,
	"Wubin \(H\)" <wu.wubin@huawei.com>,
	"dengkai \(A\)" <dengkai1@huawei.com>
Subject: RE: [PATCH V2] target/riscv: raise exception to HS-mode at get_physical_address
Date: Wed, 14 Oct 2020 10:11:21 +0000	[thread overview]
Message-ID: <ae815b3a9fda468e839cecf6fbfc0a6e@huawei.com> (raw)
In-Reply-To: <26316865-1a25-0e12-ee65-76d79e26603d@linaro.org>


> -----Original Message-----
> From: Richard Henderson [mailto:richard.henderson@linaro.org]
> Sent: Friday, October 9, 2020 10:34 PM
> To: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org;
> qemu-riscv@nongnu.org
> Cc: Zhanghailiang <zhang.zhanghailiang@huawei.com>;
> sagark@eecs.berkeley.edu; kbastian@mail.uni-paderborn.de; Zhangxiaofeng
> (F) <victor.zhangxiaofeng@huawei.com>; Alistair.Francis@wdc.com; yinyipeng
> <yinyipeng1@huawei.com>; palmer@dabbelt.com; Wubin (H)
> <wu.wubin@huawei.com>; dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH V2] target/riscv: raise exception to HS-mode at
> get_physical_address
> 
> On 10/9/20 2:57 AM, Yifei Jiang wrote:
> >  #define TRANSLATE_FAIL 1
> >  #define TRANSLATE_SUCCESS 0
> >  #define MMU_USER_IDX 3
> > +#define TRANSLATE_G_STAGE_FAIL 4
> 
> Note that you're interleaving TRANSLATE_* around an unrelated define.
> Perhaps rearrange to
> 
> enum {
>     TRANSLATE_SUCCESS = 0,
>     TRANSLATE_FAIL,
>     TRANSLATE_PMP_FAIL,
>     TRANSLATE_G_STAGE_FAIL,
> };
> 

OK

> 
> > +++ b/target/riscv/cpu_helper.c
> > @@ -451,7 +451,10 @@ restart:
> >                                                   mmu_idx,
> false,
> > true);
> >
> >              if (vbase_ret != TRANSLATE_SUCCESS) {
> > -                return vbase_ret;
> > +                env->guest_phys_fault_addr = (base |
> > +                                              (addr &
> > +
> (TARGET_PAGE_SIZE - 1))) >> 2;
> > +                return TRANSLATE_G_STAGE_FAIL;
> >              }
> 
> I don't think you can make this change to cpu state, as this function is also used
> by gdb.  I think you'll need to add a new (target_ulong *) parameter to
> get_physical_address to return this.
> 
> The usage in riscv_cpu_tlb_fill could pass &env->guest_phys_fault_addr, and
> the usage in riscv_cpu_get_phys_page_debug could pass the address of a local
> variable (which it then ignores).
> 

OK

> Also, isn't the offset more naturally written idx * ptesize, as seen just a few
> lines below?

OK

> 
> > +        if (ret != TRANSLATE_FAIL && ret != TRANSLATE_G_STAGE_FAIL) {
> 
> Should this not be ret == TRANSLATE_SUCCESS?
> This looks buggy with TRANSLATE_PMP_FAIL...

On TRANSLATE_PMP_FAIL, it should not execute G-stage translation.
So I think it is ok for 'ret == TRANSLATE_SUCCESS'

I will send V3.

Yifei

> 
> 
> r~

      reply	other threads:[~2020-10-14 10:13 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-09  7:57 [PATCH V2] target/riscv: raise exception to HS-mode at get_physical_address Yifei Jiang
2020-10-09 14:34 ` Richard Henderson
2020-10-14 10:11   ` Jiangyifei [this message]

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