From: Richard Henderson <richard.henderson@linaro.org>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>, qemu-devel@nongnu.org
Cc: foss@percivaleng.com, qemu-arm@nongnu.org,
Gustavo Romero <gustavo.romero@linaro.org>
Subject: Re: [PATCH 04/12] target/arm: Fill in TCGCPUOps.pointer_wrap
Date: Tue, 27 May 2025 08:33:40 +0100 [thread overview]
Message-ID: <ae9e0a75-bafe-4d66-a8f2-9c3371315279@linaro.org> (raw)
In-Reply-To: <e8176be8-dbe9-4cf4-a23c-a6100d530c0b@linaro.org>
On 5/26/25 19:21, Philippe Mathieu-Daudé wrote:
> +Gustavo
>
> On 4/5/25 22:57, Richard Henderson wrote:
>> For a-profile, check A32 vs A64 state.
>> For m-profile, use cpu_pointer_wrap_uint32.
>>
>> Cc: qemu-arm@nongnu.org
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/cpu.c | 24 ++++++++++++++++++++++++
>> target/arm/tcg/cpu-v7m.c | 1 +
>> 2 files changed, 25 insertions(+)
>>
>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
>> index 45cb6fd7ee..18edcf49c6 100644
>> --- a/target/arm/cpu.c
>> +++ b/target/arm/cpu.c
>> @@ -2710,6 +2710,29 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
>> #endif
>> #ifdef CONFIG_TCG
>> +#ifndef CONFIG_USER_ONLY
>> +static vaddr aprofile_pointer_wrap(CPUState *cs, int mmu_idx,
>> + vaddr result, vaddr base)
>> +{
>> + /*
>> + * The Stage2 and Phys indexes are only used for ptw on arm32,
>> + * and all pte's are aligned, so we never produce a wrap for these.
>> + * Double check that we're not truncating a 40-bit physical address.
>> + */
>> + assert((unsigned)mmu_idx < (ARMMMUIdx_Stage2_S & ARM_MMU_IDX_COREIDX_MASK));
>> +
>> + if (!is_a64(cpu_env(cs))) {
>> + return (uint32_t)result;
>> + }
>> +
>> + /*
>> + * TODO: For FEAT_CPA2, decide how to we want to resolve
>> + * Unpredictable_CPACHECK in AddressIncrement.
>> + */
>> + return result;
>> +}
>> +#endif /* !CONFIG_USER_ONLY */
>> +
>> static const TCGCPUOps arm_tcg_ops = {
>> .mttcg_supported = true,
>> /* ARM processors have a weak memory model */
>> @@ -2729,6 +2752,7 @@ static const TCGCPUOps arm_tcg_ops = {
>> .untagged_addr = aarch64_untagged_addr,
>> #else
>> .tlb_fill_align = arm_cpu_tlb_fill_align,
>> + .pointer_wrap = aprofile_pointer_wrap,
>
> IIUC this is also used by non A-profiles (R-profiles and
> non Cortex cores).
Yes, r-profile is mostly a-profile. Those non-cortex cores are also a-profile: armv[456].
The point is the separation between m-profile and not. In particular, the mmu indexes are
different between A and M (see ARM_MMU_IDX_TYPE_MASK). The assert would not be valid for
m-profile. We can avoid a check vs ARM_FEATURE_M by only using this function for
not-m-profile.
r~
next prev parent reply other threads:[~2025-05-27 7:35 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-04 20:57 [PATCH 00/12] accel/tcg: Fix cross-page pointer wrapping issue Richard Henderson
2025-05-04 20:57 ` [PATCH 01/12] accel/tcg: Add TCGCPUOps.pointer_wrap Richard Henderson
2025-05-05 9:26 ` Philippe Mathieu-Daudé
2025-05-04 20:57 ` [PATCH 02/12] target: Use cpu_pointer_wrap_notreached for strict align targets Richard Henderson
2025-05-05 9:26 ` Philippe Mathieu-Daudé
2025-05-04 20:57 ` [PATCH 03/12] target: Use cpu_pointer_wrap_uint32 for 32-bit targets Richard Henderson
2025-05-05 9:26 ` Philippe Mathieu-Daudé
2025-05-05 11:34 ` Edgar E. Iglesias
2025-05-08 6:40 ` Bastian Koppelmann
2025-05-04 20:57 ` [PATCH 04/12] target/arm: Fill in TCGCPUOps.pointer_wrap Richard Henderson
2025-05-26 18:21 ` Philippe Mathieu-Daudé
2025-05-27 7:33 ` Richard Henderson [this message]
2025-05-04 20:57 ` [PATCH 05/12] target/i386: " Richard Henderson
2025-05-05 16:52 ` Philippe Mathieu-Daudé
2025-05-04 20:57 ` [PATCH 06/12] target/loongarch: " Richard Henderson
2025-05-26 18:17 ` Philippe Mathieu-Daudé
2025-05-27 0:57 ` Bibo Mao
2025-05-27 4:04 ` gaosong
2025-05-04 20:57 ` [PATCH 07/12] target/mips: " Richard Henderson
2025-05-05 14:59 ` Philippe Mathieu-Daudé
2025-05-04 20:57 ` [PATCH 08/12] target/ppc: " Richard Henderson
2025-05-05 16:50 ` Philippe Mathieu-Daudé
2025-05-05 19:00 ` Richard Henderson
2025-05-04 20:57 ` [PATCH 09/12] target/riscv: " Richard Henderson
2025-05-05 16:47 ` Philippe Mathieu-Daudé
2025-05-05 18:59 ` Richard Henderson
2025-05-26 18:15 ` Philippe Mathieu-Daudé
2025-05-19 0:17 ` Alistair Francis
2025-05-04 20:57 ` [PATCH 10/12] target/s390x: " Richard Henderson
2025-05-05 14:41 ` Philippe Mathieu-Daudé
2025-05-05 16:16 ` Richard Henderson
2025-05-26 18:16 ` Philippe Mathieu-Daudé
2025-05-04 20:57 ` [PATCH 11/12] target/sparc: " Richard Henderson
2025-05-05 14:54 ` Philippe Mathieu-Daudé
2025-05-05 16:16 ` Richard Henderson
2025-05-04 20:57 ` [PATCH 12/12] accel/tcg: Assert TCGCPUOps.pointer_wrap is set Richard Henderson
2025-05-05 9:27 ` Philippe Mathieu-Daudé
2025-05-07 16:38 ` [PATCH 00/12] accel/tcg: Fix cross-page pointer wrapping issue FOSS
2025-05-07 17:32 ` Richard Henderson
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